WO2023186093A1 - Gating tube, preparation method for gating tube, and memory - Google Patents

Abstract

Embodiments of the present application provide a gating tube, a preparation method for the gating tube, and a memory. The gating tube comprises a first material layer, a gating tube material layer, and a second material layer. A first surface of the first material layer is in contact with a first surface of the gating tube material layer, a first surface of the second material layer is in contact with a second surface of the gating tube material layer, and the first material layer and the gating tube material layer form a potential barrier; and/or, the second material layer and the gating tube material layer form a potential barrier. According to the solution of the present application, electrons can be localized at the potential barrier, such that a leakage current of the gating tube can be reduced.

Description

Gate tube, preparation method of gate tube and memory

This application claims the priority of the Chinese patent application submitted to the China Patent Office on March 31, 2022, with the application number 202210346270.2 and the invention name "Gate tube, gate tube preparation method and memory". The patent application The entire contents are incorporated herein by reference.

Technical field

Embodiments of the present application relate to the field of semiconductor technology, and more specifically, to a gate tube, a gate tube preparation method, and a memory.

Background technique

With the vigorous development of the big data, cloud computing and Internet of Things industries, along with the explosive growth of massive information and expanding market demand, higher requirements have been placed on the storage density and capacity of memories. Various new high-performance storage Technologies have also emerged, such as cross array storage technology.

In various storage technologies, it is usually necessary to use a gate tube to gate the memory unit. Specifically, an electrical signal is used to control the switch of the gate tube. When an electrical signal is applied to the gate tube, the gate tube material changes from a high resistance state to a gate tube. When the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, and the gate tube is in a closed state. However, the leakage current of most strobes currently developed is usually at the nanoampere (nA) level, which cannot meet commercial requirements and needs to be further reduced.

Contents of the invention

Embodiments of the present application provide a gate tube, a gate tube preparation method and a memory, which can reduce the leakage current of the gate tube.

In a first aspect, a gate tube is provided, including: a first material layer, a gate tube material layer and a second material layer, wherein the first surface of the first material layer is in contact with the third surface of the gate tube material layer. A surface contact, the first surface of the second material layer is in contact with the second surface of the gate material layer, the first material layer and the gate material layer form a potential barrier; and/or the second material The layer forms a potential barrier with the gate material layer.

The gate tube provided by the embodiment of the present application includes a first material layer, a gate tube material layer and a second material layer, wherein the first material layer and the gate tube material layer form a potential barrier; and/or, the second material The layer and the gate material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby reducing the leakage current of the gate tube.

The above-mentioned first material layer and the gate tube material layer form a potential barrier, which can also be described as an interface barrier formed between the first material layer and the gate tube material layer; similarly, the above-mentioned second material layer and the gate tube material layer form an interface barrier. Forming a potential barrier can also be described as forming an interface potential barrier between the second material layer and the gate material layer.

In connection with the first aspect, in some implementations of the first aspect, the difference between the first work functions of the first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the second material layer The difference from the second work function of the gate material layer is greater than or equal to 0.3 eV.

It should be understood that if the difference in the first work function of the first material layer and the gate material layer is greater than or equal to 0.3eV, a potential barrier will be formed between the first material layer and the gate material layer; if the second material layer The difference between the second work function and the gate material layer is greater than or equal to 0.3eV, which will cause the second material layer and the gate material layer to form a potential barrier, so that electrons can be localized in the potential barrier , thereby reducing the leakage current of the gate tube.

It should be understood that the difference in the first work function is the difference between the work function of the first material layer and the work function of the gate tube material layer; the difference in the second work function is the difference between the work function of the second material layer and the gate tube material layer. The difference in work functions.

Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second material layer.

In conjunction with the first aspect, in some implementations of the first aspect, the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.

In connection with the first aspect, in some implementations of the first aspect, the first material layer includes a first multi-level thermal conductivity, the first multi-level thermal conductivity is from the second surface of the first material layer to the The first surface of the first material layer gradually decreases; and/or the second material layer includes a second multi-level thermal conductivity from the second surface of the second material layer to the second multi-level thermal conductivity. The first surface of the second material layer is gradually reduced.

In this embodiment of the present application, the first material layer may include a first multi-level thermal conductivity that gradually decreases from the second surface of the first material layer to the first surface of the first material layer. ; and/or, the second material layer may include a second multi-level thermal conductivity, and the second multi-level thermal conductivity gradually decreases from the second surface of the second material layer to the first surface of the second material layer, so that It blocks the heat transfer from the outside to the material layer of the gate tube and improves the thermal stability of the gate tube.

In conjunction with the first aspect, in some implementations of the first aspect, the first material layer includes a first buffer layer and a first electrode layer, and the first surface of the first buffer layer serves as the first surface of the first material layer. surface, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer rate; and/or, the second material layer includes a second buffer layer and a second electrode layer, the first surface of the second buffer layer serves as the first surface of the second material layer, and the first surface of the second electrode layer The surface is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.

In this embodiment of the present application, if the first material layer includes a first buffer layer and a first electrode layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, On the one hand, the introduction of the first buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can be generated between the first buffer layer and the gate tube material layer, thereby reducing the first buffer layer. The thermal conductivity between the layer and the gate tube material layer can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the first multi-level thermal conductivity includes the The thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer, which can also block the external flow to the gate material layer. Heat transfer to improve the thermal stability of the gate tube.

In this embodiment of the present application, if the second material layer includes a second buffer layer and a second electrode layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, On the one hand, the introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can be generated between the second buffer layer and the gate tube material layer, thereby reducing the second buffer layer. The thermal conductivity between the layer and the gate tube material layer can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the second multi-level thermal conductivity includes the The thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer, which can also block the external flow to the gate tube material layer. Heat transfer to improve the thermal stability of the gate tube.

Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first buffer layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second buffer layer.

In conjunction with the first aspect, in some implementations of the first aspect, the first material layer includes a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer; and/ Or, the second material layer includes a fourth electrode layer, and the second plurality of The level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer.

In this embodiment of the present application, if the first material layer includes a third electrode layer, the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity is derived from the third electrode layer. The second surface to the first surface of the third electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate tube material layer and improving the thermal stability of the gate tube.

In this embodiment of the present application, if the second material layer includes a fourth electrode layer, the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity is from the fourth electrode layer. The second surface to the first surface of the fourth electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate tube material layer and improving the thermal stability of the gate tube.

Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the third electrode layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the fourth electrode layer.

Optionally, the work function from the first surface of the third electrode layer to the second surface of the third electrode layer may decrease in a gradient; the work function from the first surface of the fourth electrode layer to the second surface of the fourth electrode layer may be Can be gradient reduced.

In connection with the first aspect, in some implementations of the first aspect, the first buffer layer and/or the second buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe ₂ , MoS ₂ , MnTe , any one or more of H _f O ₂ /TaO, WTe ₂ , WS _2, etc.

In conjunction with the first aspect, in some implementations of the first aspect, the thickness of the first buffer layer and/or the second buffer layer may be 5-20 nm.

In connection with the first aspect, in some implementations of the first aspect, the above-mentioned electrode layer (any one or more of the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer) may include Pt , any one or more of Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO ₂ , ITO and IZO, etc., the thickness of the electrode layer can be 35-100nm.

In conjunction with the first aspect, in some implementations of the first aspect, the gate material layer may include Te, Se or S-based binary or multi-element bidirectional threshold switch OTS materials. The thickness of the gate material layer Can be 10-30nm.

In connection with the first aspect, in some implementations of the first aspect, the OTS material may include any of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc. one or more.

In connection with the first aspect, in some implementations of the first aspect, the gate material layer may also include doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, etc. one or more of them.

In a second aspect, a method for preparing a gate tube is provided, including: forming a first material layer; forming a gate tube material layer on the first surface of the first material layer, and the first surface of the first material layer in contact with the first surface of the gate material layer; forming a second material layer on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer Surface contact, wherein the first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.

The preparation method provided by the embodiment of the present application includes forming a first material layer; forming a gate tube material layer on the first surface of the first material layer, and the first surface of the first material layer is in contact with the third layer of the gate tube material layer. A surface contact; a second material layer is formed on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer, wherein the first material layer and the gate The tube material layer forms a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby reducing the leakage current of the gate tube.

In conjunction with the second aspect, in some implementations of the second aspect, the difference in the first work function of the first material layer and the gate material layer may be greater than or equal to 0.3eV; and/or, the second material The difference between the second work function of the layer and the gate material layer may be greater than or equal to 0.3 eV.

Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be made by adjusting the gate material layer Or any one or more of the stoichiometric ratio, doping, thickness, etc. of the second material layer.

Combined with the second aspect, in some implementations of the second aspect, the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.

In conjunction with the second aspect, in some implementations of the second aspect, the first material layer includes a first multi-level thermal conductivity, the first multi-level thermal conductivity is from the second surface of the first material layer to the The first surface of the first material layer gradually decreases; and/or the second material layer includes a second multi-level thermal conductivity from the second surface of the second material layer to the second multi-level thermal conductivity. The first surface of the second material layer is gradually reduced.

In this embodiment of the present application, the first material layer may include a first multi-level thermal conductivity that gradually decreases from the second surface of the first material layer to the first surface of the first material layer. ; and/or, the second material layer may include a second multi-level thermal conductivity, and the second multi-level thermal conductivity gradually decreases from the second surface of the second material layer to the first surface of the second material layer, so that It blocks the heat transfer from the outside to the material layer of the gate tube and improves the thermal stability of the gate tube.

In conjunction with the second aspect, in some implementations of the second aspect, forming the first material layer includes: forming a first electrode layer; forming a first buffer layer on the first surface of the first electrode layer, the first The first surface of the buffer layer serves as the first surface of the first material layer, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the first The thermal conductivity of the buffer layer and the thermal conductivity of the first electrode layer; and/or forming the second material layer on the second surface of the gate material layer includes: A second buffer layer is formed on both surfaces, and the first surface of the second buffer layer serves as the first surface of the second material layer; a second electrode layer is formed on the second surface of the second buffer layer, and the second electrode The first surface of the layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.

In conjunction with the second aspect, in some implementations of the second aspect, forming the first material layer includes: forming a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer. ; and/or, forming a second material layer on the second surface of the gate material layer includes: forming a fourth electrode layer on the second surface of the gate material layer, the second multi-level thermal conductor is the multi-level thermal conductivity of the fourth electrode layer.

In conjunction with the second aspect, in some implementations of the second aspect, the first buffer layer and/or the second buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe ₂ , MoS ₂ , MnTe , any one or more of H _f O ₂ /TaO, WTe ₂ , WS _2, etc.

In conjunction with the second aspect, in some implementations of the second aspect, the thickness of the first buffer layer and/or the second buffer layer may be 5-20 nm.

In connection with the second aspect, in some implementations of the second aspect, the above-mentioned electrode layer (any one or more of the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer) may include Pt , any one or more of Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO ₂ , ITO, IZO, etc., the thickness of the electrode layer may be 35-100 nm.

In connection with the second aspect, in some implementations of the second aspect, the gate material layer may include a Te, Se or S-based binary or multi-element bidirectional threshold switch OTS material, and the thickness of the gate material layer may be is 10-30nm.

Combined with the second aspect, in some implementations of the second aspect, the OTS material may include any of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc. one or more.

In conjunction with the second aspect, in some implementations of the second aspect, the gate material layer may also include doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, etc. one or more of them.

In connection with the second aspect, in some implementations of the second aspect, the method of forming the first material layer, the gate material layer or the second material layer may include evaporation, sputtering, and atomic layer deposition. Any one or more of chemical vapor deposition, pulsed laser deposition, molecular beam epitaxy, etc.

In a third aspect, a memory chip is provided, including a plurality of memory units and a plurality of memory cells as described in the first aspect or any of the In one possible implementation of the strobe tube, each storage unit corresponds to one strobe tube.

Optionally, the memory chip may include a cross-array storage structure, and the cross-array structure storage may be a two-dimensional cross-array storage structure or a three-dimensional cross-array storage structure, without limitation.

A fourth aspect provides a memory, including: a memory chip as described in the third aspect; and a peripheral circuit for reading and writing data in the memory chip.

In a fifth aspect, an electronic device is provided, including the memory as described in the fourth aspect. Optionally, the electronic device may include, for example, a desktop computer, a notebook computer, a smartphone, a tablet, a personal digital assistant (PDA), a wearable device, a smart speaker, a television, a drone, a vehicle, or a vehicle-mounted device. (such as car machines, car computers, car chips, etc.) or robots, etc.

Description of drawings

Figure 1 is an example diagram of a memory provided by an embodiment of the present application.

FIG. 2 is an example diagram of a cross array storage structure provided by an embodiment of the present application.

Figure 3 is an example diagram of a gate tube provided by an embodiment of the present application.

Figure 4 is an example diagram of another gate tube provided by the embodiment of the present application.

Figure 5 is an example diagram of yet another gate tube provided by the embodiment of the present application.

Figure 6 is a flow chart of a method for preparing a gate tube provided by an embodiment of the present application.

FIG. 7 is an example diagram of yet another gate tube provided by the embodiment of the present application.

Figure 8 is an example diagram of the microstructure of a gate tube provided by the embodiment of the present application.

FIG. 9 is an example diagram of a voltage-current curve of a strobe provided by an embodiment of the present application.

FIG. 10 is an example diagram of a voltage-current curve of another strobe provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

First of all, it should be noted that the gate tube provided in the embodiment of the present application can be applied to the field of semiconductor technology, specifically to memories in the field of semiconductor technology, to realize gating of memory cells; it can also be applied to other circuits ( For example, integrated circuits) to turn the circuit on and off. For the convenience of description, the following uses application to memory as an example.

Figure 1 is an example diagram of a memory provided by an embodiment of the present application. As shown in FIG. 1 , the memory 100 includes a peripheral circuit 110 and a memory chip 120 . The memory chip 120 includes a plurality of memory units. The peripheral circuit 110 and each memory unit in the memory chip 120 can communicate with each other. The peripheral circuit 110 can communicate with each other. 110 may include a row decoder, an amplifier, a column decoder, and other control circuits, so that the peripheral circuit 110 may control the read and write operations of each memory unit and other operations. For example, the peripheral circuit 110 can write data in each storage unit; for another example, the peripheral circuit 110 can read data from each storage unit.

With the vigorous development of the big data, cloud computing and Internet of Things industries, along with the explosive growth of massive information and expanding market demand, higher requirements have been placed on the storage density and capacity of memories. Various new high-performance storage Technologies also emerged, such as cross-array storage technology. The following takes the cross-array memory structure 121 shown in FIG. 2 as an example to introduce the structure of the memory chip 120 . FIG. 2 is an example diagram of a cross array storage structure provided by an embodiment of the present application. As shown in Figure 2, the cross array memory structure 121 includes a gate array and a memory cell array. The strobe tubes in the strobe tube array and the memory cells in the memory cell array are connected in series in a one-to-one correspondence. It should be understood that BL and WL in Figure 2 can be used to identify the locations of memory cells and gate tubes in the crossbar array. Among them, BL0 and BL1 are the bit lines where the memory cells and strobe tubes are located in the cross array, and WL0 and WL1 are the word lines where the memory cells and strobe tubes are located in the cross array. For example For example, the positions of the gate tube 10 and the memory unit 20 in FIG. 2 can be expressed as (BL0, WL1). Optionally, the memory unit involved in this application may be a phase change memory unit, a resistive switching memory unit, a magnetic memory unit or a ferroelectric memory unit, etc. This application does not limit this. It should be understood that the gate tube in the cross array is mainly used to gate the memory cells. Specifically, electrical signals are used to control the switching of the gate tube. When an electrical signal is applied to the gate tube, the gate tube material is formed by high resistance. When the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, and the gate tube is in a closed state. However, the leakage current of gate tubes currently developed is usually at the nanoampere (nA) level, which cannot meet commercial requirements and needs to be further reduced.

Based on this, embodiments of the present application form a potential barrier by designing the gate material layer and other material layers in the gate tube, so that electrons can be localized at the potential barrier to reduce the leakage current of the gate tube.

Figure 3 is an example diagram of a gate tube provided by an embodiment of the present application. It should be understood that the gate tube 300 shown in FIG. 3 can be applied to the memory 100 shown in FIG. 1 or the cross array memory structure 121 shown in FIG. 2 . As shown in FIG. 3 , the gate tube 300 includes a first material layer 310 , a gate tube material layer 320 and a second material layer 330 .

The first surface 311 of the first material layer 310 is in contact with the first surface 321 of the gate material layer 320 , and the first surface 331 of the second material layer 330 is in contact with the second surface 322 of the gate material layer 320 . It should be understood that the first surface 321 of the gate material layer 320 and the second surface 322 of the gate material layer 320 are two opposite surfaces of the gate material layer 320 .

Wherein, the first material layer 310 and the gate material layer 320 form a potential barrier; and/or the second material layer 330 and the gate material layer 320 form a potential barrier, so that electrons can be localized at the potential barrier, thereby enabling Reduce the leakage current of the gate tube.

The above-mentioned first material layer 310 and the gate tube material layer 320 form a potential barrier, which can also be described as forming an interface barrier between the first material layer 310 and the gate tube material layer 320; similarly, the above-mentioned second material layer 330 and the gate tube material layer 320 form an interface barrier. The gate material layer 320 forms a potential barrier, which can also be described as an interface barrier formed between the second material layer 330 and the gate material layer 320 .

Optionally, in actual operation, from the perspective of work function, the gate material layer 320 and other material layers can be designed to have work function differences, so that a potential barrier is formed between the gate material layer 320 and other material layers, so that the electrons It can be localized at the potential barrier to reduce the leakage current of the gate tube.

Specifically, it can be designed that the work function of the first material layer 310 is greater than the work function of the gate material layer 320, and the difference between the first work functions of the first material layer 310 and the gate material layer 320 is greater than or equal to 0.3 eV, This allows the first material layer 310 and the gate material layer 320 to form a potential barrier; and/or the work function of the second material layer 330 can be designed to be greater than the work function of the gate material layer 320, and the second material layer 330 If the difference between the second work function and the gate material layer 320 is greater than or equal to 0.3 eV, the second material layer 330 and the gate material layer 320 can form a potential barrier, so that electrons can be localized at the potential barrier, thereby It can reduce the leakage current of the gate tube.

It should be understood that the difference of the first work function is the difference between the work function of the first material layer 310 and the work function of the gate material layer 320; the difference of the second work function is the difference between the work function of the second material layer 330 and the gate material layer 320. The difference in work function of the tube material layer 320.

It should be understood that in the gate 300, the difference between the first work function can be greater than or equal to 0.3eV, the difference between the second work function can be greater than or equal to 0.3eV, or the difference between the first work function and the second work function can be greater than or equal to 0.3eV. The difference between the two work functions is greater than or equal to 0.3eV at the same time.

It should be understood that the difference in work functions in the embodiments of the present application can also be described as a difference in Fermi level or bandgap width.

Optionally, the difference between the first work function and the second work function may be the same or different, and this application does not limit this.

For example, the difference between the first work function is 0.3eV, and the difference between the second work function is 0eV; or, the difference between the first work function is 0.2eV, and the difference between the second work function is 0.5eV; or, the difference between the first work function and the second work function is 0.5eV. The difference between the functions is 0.4eV, and the difference between the second work function is 0.3eV; or, the difference between the first work function and the second work function is both 0.3eV; or, the difference between the first work function and the second work function is 0.3eV. The differences in work functions are all 0.6eV.

Optionally, the difference in the first work function may be greater than or equal to 0.5eV and less than or equal to 0.65eV. By way of example, the difference in the first work functions may be 0.5, 0.55, 0.6 or 0.65. Optionally, the difference in the second work function can also satisfy the following range: 0.5-0.65eV. For example, the difference between the second work functions may also be 0.5, 0.55, 0.6 or 0.65. It should be understood that the values of the difference between the first work function and the second work function can both meet the range of 0.5-0.65eV, or one of them can meet the above range; the difference between the first work function and the second work function The values of can be the same or different.

Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second material layer.

In actual operation, the interface barrier formed between different material layers can also be used to regulate the threshold voltage of the gate tube.

Optionally, the first material layer 310 may include a first multi-level thermal conductivity, the first multi-level thermal conductivity is gradually from the second surface 312 of the first material layer 310 to the first surface 311 of the first material layer 310 . and/or the second material layer 330 may include a second multi-level thermal conductivity from the second surface 332 of the second material layer 330 to a first Surface 331 decreases step by step.

In the embodiment of the present application, the first material layer 310 may include a first multi-level thermal conductivity from the second surface 312 of the first material layer 310 to a first surface of the first material layer 310 . The surface 311 gradually decreases; and/or the second material layer 330 may include a second multi-level thermal conductivity from the second surface 332 of the second material layer 330 to the second material layer 330 The first surface 331 gradually decreases, thereby blocking the heat transfer from the outside to the gate tube material layer 320 and improving the thermal stability of the gate tube.

For the first material layer 310: In one implementation, the first material layer 310 may include a first buffer layer and a first electrode layer, wherein the first surface of the first buffer layer serves as the first surface of the first material layer 310. The first surface 311, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer. It should be understood that the first surface of the first buffer layer and the second surface of the first buffer layer are two opposite surfaces of the first buffer layer. It should be understood that the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, which means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.

In this embodiment of the present application, the first material layer 310 may include a first buffer layer and a first electrode layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer. , on the one hand, the introduction of the first buffer layer introduces more interfaces to the gate tube, so that the interface effect (ie, phonon scattering) can be generated between the first buffer layer and the gate tube material layer 320, thereby reducing the third The thermal conductivity between a buffer layer and the gate tube material layer 320 can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the first multi-level thermal conductivity The thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, which means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer, and can also prevent the outside world from reaching the gate tube. The heat transfer of the material layer 320 improves the thermal stability of the gate tube.

In this case, the difference in the first work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the first buffer layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the first buffer layer can also be adjusted simultaneously to achieve the difference in the first work function.

It should be understood that adjusting the stoichiometric ratio means adjusting the atomic percentage of each element in the material layer. For example, the gate material Ge ₅₀ S ₅₀ of the gate material layer 320 can be adjusted to Ge ₃₀ S ₇₀ . It should be understood that when adjusting the stoichiometric ratio or doping, the stoichiometric ratio or doping of the entire via material layer 320 and/or the entire first buffer layer can be adjusted, or only the via material layer 320 and the first buffer layer can be adjusted. The stoichiometry or doping of the contact surface of a buffer layer is not limited.

Alternatively, the first buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe ₂ , MoS ₂ , MnTe, Any one or more of H _f O ₂ /TaO, WTe ₂ , WS ₂ , etc.

Optionally, the thickness of the first buffer layer may be 5-20 nm.

Alternatively, the first electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO ₂ , ITO, IZO, and the like.

Optionally, the thickness of the first electrode layer may be 35-100 nm.

In another implementation, the first material layer 310 may include a third electrode layer, wherein the first surface of the third electrode layer serves as the first surface 311 of the first material layer 310, and the first multi-level thermal conductivity is Multi-level thermal conductivity of the third electrode layer. It should be understood that the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity gradually decreases from the second surface of the third electrode layer to the first surface of the third electrode layer.

In this embodiment of the present application, the first material layer 310 may include a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity is from the third electrode layer. The second surface to the first surface of the third electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate material layer 320 and improving the thermal stability of the gate tube.

In this case, the difference in the first work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, and thickness of the gate material layer 320 or the third electrode layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the third electrode layer can also be adjusted simultaneously to achieve the difference in the first work function.

It should be understood that when adjusting the stoichiometric ratio or doping, the stoichiometric ratio or doping of the entire via tube material layer 320 and/or the entire third electrode layer can be adjusted, or only the via tube material layer 320 and/or the via tube material layer 320 and/or the entire third electrode layer can be adjusted. Or the stoichiometric ratio or doping of the contact surface layer of the third electrode layer is not limited.

Optionally, the work function from the first surface of the third electrode layer to the second surface of the third electrode layer decreases in a gradient. It should be understood that the first surface of the third electrode layer and the second surface of the third electrode layer are two opposite surfaces of the third electrode layer. It should be understood that the work function of the third electrode layer may also exhibit other distributions without limitation.

Optionally, the third electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO ₂ , ITO, IZO, and the like.

Optionally, the thickness of the third electrode layer may be 35-100 nm.

For the second material layer 330: In one implementation, the second material layer 330 may include a second buffer layer and a second electrode layer, and the first surface of the second buffer layer serves as the first surface of the second material layer 330. Surface 331, the first surface of the second electrode layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer. It should be understood that the first surface of the second buffer layer and the second surface of the second buffer layer are two opposite surfaces of the second buffer layer. It should be understood that the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, which means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.

In this embodiment of the present application, if the second material layer 330 includes a second buffer layer and a second electrode layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer , on the one hand, the introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (ie, phonon scattering) can be generated between the second buffer layer and the gate tube material layer 320, thereby reducing the third The thermal conductivity between the second buffer layer and the gate tube material layer 320 can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the second multi-level thermal conductivity The thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, which means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer, and can also prevent the outside world from reaching the gate tube. The heat transfer of the material layer 320 improves the thermal stability of the gate tube.

In this case, the difference in the second work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the second buffer layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the second buffer layer can also be adjusted simultaneously to achieve the difference in the second work function.

It should be understood that when adjusting the stoichiometric ratio or doping, the entire via material layer 320 and/or the entire third The stoichiometric ratio or doping of the two buffer layers can also only be adjusted to the stoichiometric ratio or doping of the via material layer 320 and/or the contact surface layer of the second buffer layer, without limitation.

Optionally, the second buffer layer may include any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe ₂ , MoS ₂ , MnTe, H _f O ₂ /TaO, WTe ₂ , WS _2, etc. kind.

Optionally, the thickness of the second buffer layer may be 5-20 nm.

Optionally, the second electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO ₂ , ITO, IZO, and the like.

Optionally, the thickness of the second electrode layer may be 35-100 nm.

In another implementation, the second material layer 330 may include a fourth electrode layer, the first surface of the fourth electrode layer serves as the first surface 331 of the second material layer 330, and the second multi-level thermal conductivity is the fourth Multilevel thermal conductivity of electrode layers. It should be understood that the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity gradually decreases from the second surface of the fourth electrode layer to the first surface of the fourth electrode layer.

In this embodiment of the present application, the second material layer 330 may include a fourth electrode layer, and the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity is from the fourth electrode layer. The second surface to the first surface of the fourth electrode layer gradually decreases, thereby blocking the heat transfer from the outside to the gate material layer 320 and improving the thermal stability of the gate tube.

In this case, the difference in the second work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the fourth electrode layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the fourth electrode layer can also be adjusted simultaneously to realize the difference in the second work function.

It should be understood that when adjusting the stoichiometric ratio or doping, the stoichiometric ratio or doping of the entire via tube material layer 320 and/or the entire fourth electrode layer can be adjusted, or only the via tube material layer 320 and/or the via tube material layer 320 and/or the entire fourth electrode layer can be adjusted. Or the stoichiometric ratio or doping of the contact surface layer of the fourth electrode layer is not limited.

Optionally, the work function from the first surface of the fourth electrode layer to the second surface of the fourth electrode layer may decrease in a gradient. It should be understood that the first surface of the fourth electrode layer and the second surface of the fourth electrode layer are two opposite surfaces of the fourth electrode layer. It should be understood that the work function of the fourth electrode layer may also exhibit other distributions without limitation.

Optionally, the fourth electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO ₂ , ITO, IZO, and the like.

Optionally, the thickness of the fourth electrode layer may be 35-100 nm.

It should be understood that the embodiments of the present application do not limit the specific combination of the first material layer and the second material layer. Exemplarily, the first material layer 310 includes a first buffer layer and a first electrode layer, and the second material layer 330 includes a second buffer layer and a second electrode layer, see FIG. 4 ; or, the first material layer 310 includes a third Electrode layer, the second material layer 330 includes a fourth electrode layer, see FIG. 5; or, the first material layer 310 includes a first buffer layer and a first electrode layer, and the second material layer 330 includes a fourth electrode layer; or, the first The material layer 310 includes a third electrode layer, and the second material layer 330 includes a second buffer layer and a second electrode layer. For ease of description, the first two examples are used as examples for description below, but it should be understood that actual applications may not be limited to these.

Regarding the gate material layer 320: Optionally, the gate material layer 320 may include a Te, Se or S-based binary or multi-element bidirectional threshold switching (ovonic threshold switching, OTS) material.

Optionally, the thickness of the gate material layer 320 may be 10-30 nm.

Alternatively, the OTS material may include any one or more of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc.

Optionally, the gate material layer 320 may also include one or more of doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, and the like.

The following takes FIG. 4 and FIG. 5 as examples to introduce the structure of the gate tube 300 .

Figure 4 is an example diagram of another gate tube provided by the embodiment of the present application. As shown in Figure 4, the gate tube 400 includes a bottom electrode layer 410 (i.e., the above-mentioned first electrode layer), a first buffer layer 420 (i.e., the above-mentioned first buffer layer), and a gate tube material layer 430 (i.e., the above-mentioned gate tube material layer 320), a second buffer layer 440 (ie, the above-mentioned second buffer layer), and a top electrode layer 450 (ie, the above-mentioned second electrode layer).

The first surface 411 of the bottom electrode layer 410 is in contact with the second surface 422 of the first buffer layer 420, and the first surface 421 of the first buffer layer 420 is in contact with the first surface 431 of the gate material layer 430. The second surface 432 of the tube material layer 430 is in contact with the first surface 441 of the second buffer layer 440 , and the first surface 451 of the top electrode layer 450 is in contact with the second surface 442 of the second buffer layer 440 .

Optionally, the first buffer layer 420 and the gate material layer 430 form a potential barrier; or the second buffer layer 440 and the gate material layer 430 form a potential barrier; or the first buffer layer 420 and the gate material layer The layer 430 and the second buffer layer 440 and the gate material layer 430 all form a potential barrier.

Optionally, the difference in work functions between the first buffer layer 420 and the gate material layer 430 is greater than or equal to 0.3 eV; or, the difference in work functions between the second buffer layer 440 and the gate material layer 430 is greater than or equal to 0.3 eV; alternatively, the difference between the work functions of the first buffer layer 420 and the gate material layer 430 and the difference between the work functions of the second buffer layer 440 and the gate material layer 430 are both greater than or equal to 0.3 eV.

Optionally, the thermal conductivity of the first buffer layer 420 is less than the thermal conductivity of the bottom electrode layer 410; or, the thermal conductivity of the second buffer layer 440 is less than the thermal conductivity of the top electrode layer 450; or, the first buffer layer The thermal conductivity of 420 is less than that of the bottom electrode layer 410 and the thermal conductivity of the second buffer layer 440 is less than that of the top electrode layer 450 .

Regarding the materials and thickness definitions of the bottom electrode layer 410, the first buffer layer 420, the gate material layer 430, the second buffer layer 440, and the top electrode layer 450, please refer to the above section about the first electrode layer and the first gate tube 300. The relevant descriptions of the buffer layer, the gate material layer 320, the second buffer layer, and the second electrode layer will not be described again.

Figure 5 is an example diagram of yet another gate tube provided by the embodiment of the present application. As shown in Figure 5, the gate tube 500 includes a bottom electrode layer 510 (i.e., the above-mentioned third electrode layer), a gate tube material layer 520 (i.e., the above-mentioned gate tube material layer 320), and a top electrode layer 530 (i.e., the above-mentioned third electrode layer). four electrode layers).

The first surface 511 of the bottom electrode layer 510 is in contact with the first surface 521 of the gate material layer 520 , and the first surface 531 of the top electrode layer 530 is in contact with the second surface 522 of the gate material layer 520 .

Optionally, the bottom electrode layer 510 and the gate material layer 520 form a potential barrier; or the top electrode layer 530 and the gate material layer 520 form a potential barrier; or the bottom electrode layer 510 and the gate material layer 520 and The top electrode layer 530 and the gate material layer 520 both form a potential barrier.

Optionally, the difference in the work functions of the bottom electrode layer 510 and the gate material layer 520 is greater than or equal to 0.3eV; or, the difference in the work functions of the top electrode layer 530 and the gate material layer 520 is greater than or equal to 0.3eV; Alternatively, the difference between the work functions of the bottom electrode layer 510 and the gate material layer 520 and the difference between the work functions of the top electrode layer 530 and the gate material layer 520 are both greater than or equal to 0.3 eV.

Optionally, the bottom electrode layer 510 includes a multi-level thermal conductivity that gradually decreases from the second surface 512 of the bottom electrode layer 510 to the first surface 511 of the bottom electrode layer 510; or, the top electrode layer 530 includes multiple levels of thermal conductivity that gradually decrease from the second surface 532 of the top electrode layer 530 to the first surface 531 of the top electrode layer 530; alternatively, the bottom electrode layer 510 includes multiple levels of thermal conductivity. , the multi-level thermal conductivity gradually decreases from the second surface 512 of the bottom electrode layer 510 to the first surface 511 of the bottom electrode layer 510 and the top electrode layer 530 includes multi-level thermal conductivity, the multi-level thermal conductivity starts from the top The second surface 532 of the electrode layer 530 to the first surface 531 of the top electrode layer 530 gradually decreases.

Regarding the materials and thickness limits of the bottom electrode layer 510 , the gate material layer 520 , and the top electrode layer 530 , please refer to the relevant descriptions of the third electrode layer, the gate material layer 320 , and the fourth electrode layer in the gate tube 300 above. ,No longer.

Embodiments of the present invention also provide a method for preparing a gate tube. FIG. 6 is a flow chart of a method for preparing a gate tube provided by embodiments of the present application. As shown in Figure 6, the method 600 includes steps S610 to S630, and these steps are introduced below.

S610, form a first material layer.

Optionally, the first material layer may include multi-level thermal conductivity (ie, the above-mentioned first multi-level thermal conductivity), the multi-level thermal conductivity from the second surface of the first material layer to the first material layer The first surface gradually decreases, thereby blocking heat transfer from the outside to the material layer of the gate tube and improving the thermal stability of the gate tube.

In one implementation, forming the first material layer may include: forming a first electrode layer; forming a first buffer layer on the first surface of the first electrode layer, wherein the first surface of the first buffer layer serves as the first The first surface of the material layer and the first surface of the first electrode layer are in contact with the second surface of the first buffer layer, and the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.

In this embodiment of the present application, forming the first material layer may include forming a first buffer layer and a first electrode layer, and the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer. On the one hand, the first buffer layer The introduction of the layer introduces more interfaces to the gate tube, so that the interface effect (that is, phonon scattering) can be generated between the first buffer layer and the gate tube material layer, thereby reducing the The thermal conductivity between the layers can hinder the heat transfer from the outside to the gate material layer and improve the thermal stability of the gate tube; on the other hand, the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer. The conductivity can also hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.

It should be understood that regarding the materials and thicknesses of the first buffer layer and the first electrode layer, reference may be made to the relevant descriptions above and will not be described again.

In another implementation, forming the first material layer may include: forming a third electrode layer, wherein the first surface of the third electrode layer serves as the first surface of the first material layer, and the third electrode layer includes a plurality of The multi-level thermal conductivity gradually decreases from the second surface of the third electrode layer to the first surface of the third electrode layer, which can hinder the heat transfer from the outside to the gate tube material layer and improve the gate. Thermal stability of the tube.

It should be understood that regarding the material and thickness of the third electrode layer, please refer to the relevant description above and will not be described again.

S620: Form a gate material layer on the first surface of the first material layer, and the first surface of the first material layer is in contact with the first surface of the gate material layer.

It should be understood that regarding the material and thickness of the gate material layer, please refer to the relevant description above and will not be described again.

S630: Form a second material layer on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer.

Optionally, the second material layer may include a multi-level thermal conductivity (and the above-mentioned second multi-level thermal conductivity), the multi-level thermal conductivity from the second surface of the second material layer to the second surface of the second material layer. The first surface gradually decreases, thereby blocking heat transfer from the outside to the material layer of the gate tube and improving the thermal stability of the gate tube.

In one implementation, forming the second material layer on the second surface of the gate material layer may include: forming a second buffer layer on the second surface of the gate material layer, the second buffer layer having a A surface serves as the first surface of the second material layer; a second electrode layer is formed on the second surface of the second buffer layer, and the first surface of the second electrode layer is in contact with the second surface of the second buffer layer , the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.

In this embodiment of the present application, forming the second material layer may include forming a second buffer layer and a second electrode layer, and the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer. On the one hand, the second buffer layer The introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can occur between the second buffer layer and the gate tube material layer, thereby reducing the The thermal conductivity between the layers can hinder the heat transfer from the outside to the gate material layer and improve the thermal stability of the gate tube; on the other hand, the thermal conductivity of the second buffer layer is smaller than that of the second electrode layer. The conductivity can also hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.

It should be understood that regarding the materials and thicknesses of the second buffer layer and the second electrode layer, reference may be made to the relevant descriptions above and will not be described again.

In another implementation, forming the second material layer on the second surface of the gate material layer may include: forming a fourth electrode layer on the second surface of the gate material layer, the fourth The first surface of the electrode layer serves as the first surface of the second material layer, and the fourth electrode layer may include multi-level thermal conductivity from the second surface of the fourth electrode layer to the fourth electrode. The first surface of the layer decreases step by step, which can hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.

It should also be noted that the above-mentioned first material layer and the gate material layer form a potential barrier; and/or the second material layer and the gate material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby It can reduce the leakage current of the gate tube.

Optionally, the difference in the first work function of the above-mentioned first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the difference in the second work function of the second material layer and the gate material layer is greater than or equal to 0.3eV. It should be understood that the specific description of the work function can be found above and will not be described again.

Optionally, the method of forming the first material layer, the gate material layer or the second material layer may include evaporation, sputtering, atomic layer deposition, chemical vapor deposition, pulsed laser deposition, and molecular beam epitaxy. any one or more of the following.

It should be understood that the same method or different methods can be used to form the first material layer, the gate material layer and the second material layer, which is not limited in this application.

Optionally, referring to FIG. 7 , before forming the first material layer in step S610 , the electrode layer 720 and the insulating layer 730 may be sequentially prepared on the substrate 710 , and then features may be formed on the insulating layer 730 through photolithography and etching processes. For small holes with a size of 80-500 nm, step S610 is performed again. In one implementation, referring to (a) in FIG. 7 , a first electrode layer 410 is formed in a small hole, the surface is planarized through a chemical polishing process, and then a first electrode layer 410 is formed on the first electrode layer 410 on the planarized surface. A buffer layer 420, continue to perform steps S620 and S630 on the first buffer layer 420, for example, the gate material layer 430, the second buffer layer 440 and the second electrode layer 450 can be sequentially formed on the first buffer layer 420; In another implementation, see (b) in FIG. 7 , the third electrode layer 510 is formed in the small hole, and the surface is planarized through a chemical polishing process, and then continues on the third electrode layer 510 with the planarized surface. Steps S620 and S630 are performed, for example, the gate material layer 520 and the fourth electrode layer 530 may be sequentially formed on the third electrode layer 510 . Optionally, after completing the above steps, photolithography and etching techniques can also be used to form a gate tube with a final specified size, for example, a gate tube with a characteristic size of 50 nm.

Alternatively, the above-mentioned substrate may be a Si substrate or SiO ₂ substrate. It should be understood that the above characteristic dimensions can be understood as the length, width or diameter of the gate tube surface, and are not limited thereto.

The following takes the strobe shown in Figure 8 as an example, and introduces the test performance (ie, leakage current and thermal stability) of the strobe in conjunction with Figures 9 and 10.

FIG. 8 is an example diagram of the microstructure of a gate tube provided by an embodiment of the present application. It should be understood that the gate tube shown in FIG. 8 is an example of the gate tube shown in FIG. 4 . As shown in FIG. 8 , in this gate tube, the material selected for the bottom electrode layer 410 is W, the material selected for the first buffer layer 420 is a C-S compound, and the material selected for the gate material layer 430 is a Ge-S compound. The material selected for the second buffer layer 440 is C-S compound, and the material selected for the top electrode layer 450 is TiN.

It should be understood that in this example, an interface barrier is formed between the first buffer layer 420 and the gate material layer 430 and between the second buffer layer 440 and the gate material layer 430; the first buffer layer 420 and the gate material layer 430 form an interface barrier. The difference in work functions of the pass tube material layer 430 and the difference in work functions of the second buffer layer 440 and the gate tube material layer 430 are both approximately greater than 0.3 eV; the thermal conductivity of the first buffer layer 420 is smaller than that of the bottom electrode layer 410 The conductivity and thermal conductivity of the second buffer layer 440 are less than the thermal conductivity of the top electrode layer 450 .

It should also be noted that the microstructure shown in Figure 8 is the microstructure of the gate tube after annealing at 400°C. It can be seen from Figure 8 that the first buffer layer CS, the gate tube material layer Ge-S and the second The sandwich heterostructure formed by the buffer layer CS remains in an amorphous state after annealing and does not undergo crystalline phase change, which means that the gate tube has high thermal stability. This is because, on the one hand, the introduction of the first buffer layer and the second buffer layer introduces more interfaces to the gate tube, so that the buffer layer and the gate tube material The interface effect (i.e. phonon scattering) can be produced between the layers, which can reduce the thermal conductivity between the buffer layer and the gate material layer, thereby hindering the heat transfer from the outside to the gate material layer and improving the gate. Thermal stability of the tube; on the other hand, the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the bottom electrode layer and the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the top electrode layer, hindering the external access to the gate The heat transfer of the tube material layer further improves the thermal stability of the gate tube.

FIG. 9 is an example diagram of a voltage-current curve of a strobe provided by an embodiment of the present application. Specifically, FIG. 9 is an example diagram of the voltage-current curve tested after the gate tube shown in FIG. 8 was annealed at 400° C. for 30 minutes. As shown in Figure 9, it can be seen that the gate tube can still maintain stable switching characteristics after annealing at 400°C for 30 minutes. FIG. 10 is an example diagram of a voltage-current curve of another strobe provided by an embodiment of the present application. Specifically, FIG. 10 is a partial enlarged view of FIG. 9 , and it can be seen that the leakage current of the gate tube is less than 400 pA. This is because the contact surface between the first buffer layer and the gate material layer and the contact surface between the second buffer layer and the gate material layer both have differences in work functions, thus forming an interface barrier, allowing electrons to be localized in barrier, thereby reducing leakage current. In summary, the gate tube provided by the embodiment of the present application has the advantages of high thermal stability and low leakage current. And the leakage current is reduced to the pA level, so it can meet the needs of high-density integration of memory cells.

An embodiment of the present application also provides a memory chip, which includes a plurality of memory units and a plurality of strobe tubes provided in the embodiments of the present application, with each memory unit corresponding to a strobe tube.

Optionally, the memory chip may include a cross-array storage structure, and the cross-array storage structure may be a two-dimensional cross-array storage structure or a three-dimensional cross-array storage structure, without limitation.

An embodiment of the present application also provides a memory, which includes: the memory chip provided in the embodiment of the present application; and a peripheral circuit for reading and writing data in the memory chip.

An embodiment of the present application also provides an electronic device, including the memory provided in the embodiment of the present application. Optionally, the electronic device may include, for example, a desktop computer, a notebook computer, a smartphone, a tablet, a personal digital assistant (PDA), a wearable device, a smart speaker, a television, a drone, a vehicle, or a vehicle-mounted device. (such as car machines, car computers, car chips, etc.) or robots, etc.

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims (12)

1. A gate tube, characterized in that it includes: a first material layer, a gate tube material layer and a second material layer,

   Wherein, the first surface of the first material layer is in contact with the first surface of the gate tube material layer, and the first surface of the second material layer is in contact with the second surface of the gate tube material layer, The first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.
2. The gate tube according to claim 1, wherein the difference between the first work functions of the first material layer and the gate tube material layer is greater than or equal to 0.3eV; and/or, the second The difference between the second work functions of the material layer and the gate material layer is greater than or equal to 0.3 eV.
3. The gate tube according to claim 2, wherein the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.
4. The gate tube according to any one of claims 1 to 3, characterized in that the first material layer includes a first multi-level thermal conductivity, the first multi-level thermal conductivity is from the first The second surface of the material layer decreases gradually from the first surface of the first material layer; and/or the second material layer includes a second multi-level thermal conductivity, and the second multi-level thermal conductivity decreases from The distance from the second surface of the second material layer to the first surface of the second material layer gradually decreases.
5. The gate tube according to claim 4, wherein the first material layer includes a first buffer layer and a first electrode layer, and the first surface of the first buffer layer serves as the first material layer. a first surface, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the The thermal conductivity of the first electrode layer; and/or the second material layer includes a second buffer layer and a second electrode layer, and the first surface of the second buffer layer serves as the first surface of the second material layer. surface, the first surface of the second electrode layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the second Thermal conductivity of the electrode layer.
6. The gate tube according to claim 4, wherein the first material layer includes a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer; And/or, the second material layer includes a fourth electrode layer, and the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer.
7. The gate tube according to claim 5, characterized in that the first buffer layer and/or the second buffer layer include amorphous carbon, SiC, CS, TeC, TeCS, MoTe ₂ , MoS ₂ , MnTe , any one or more of H _f O ₂ /TaO, WTe ₂ and WS ₂ .
8. A method for preparing a gate tube, characterized in that it includes:

   forming a first material layer;

   forming a gate tube material layer on the first surface of the first material layer, the first surface of the first material layer being in contact with the first surface of the gate tube material layer;

   A second material layer is formed on the second surface of the gate tube material layer, and the first surface of the second material layer is in contact with the second surface of the gate tube material layer,

   Wherein, the first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.
9. The preparation method according to claim 8, characterized in that the difference between the first work functions of the first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the second material The difference between the second work function of the layer and the gate material layer is greater than or equal to 0.3 eV.
10. The preparation method according to claim 8 or 9, characterized in that the first material layer includes a first multi-level thermal conductivity, and the first multi-level thermal conductivity is obtained from a second layer of the first material layer. The surface to the first surface of the first material layer gradually decreases; and/or the second material layer includes a second multi-level thermal conductivity, the second multi-level thermal conductivity is from the second material layer to the first surface of the first material layer. The second surface of the layer gradually decreases to the first surface of the second material layer.
11. A memory chip includes a plurality of memory units and a plurality of strobe tubes according to any one of claims 1 to 7, each memory unit corresponding to a strobe tube.
12. A memory, characterized in that it includes:

    The memory chip according to claim 11;

    Peripheral circuit, used for reading and writing data in the memory chip.