WO2023186093A1 - Gating tube, preparation method for gating tube, and memory - Google Patents
Gating tube, preparation method for gating tube, and memory Download PDFInfo
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- WO2023186093A1 WO2023186093A1 PCT/CN2023/085470 CN2023085470W WO2023186093A1 WO 2023186093 A1 WO2023186093 A1 WO 2023186093A1 CN 2023085470 W CN2023085470 W CN 2023085470W WO 2023186093 A1 WO2023186093 A1 WO 2023186093A1
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
Definitions
- Embodiments of the present application relate to the field of semiconductor technology, and more specifically, to a gate tube, a gate tube preparation method, and a memory.
- a gate tube In various storage technologies, it is usually necessary to use a gate tube to gate the memory unit. Specifically, an electrical signal is used to control the switch of the gate tube. When an electrical signal is applied to the gate tube, the gate tube material changes from a high resistance state to a gate tube. When the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, and the gate tube is in a closed state.
- the leakage current of most strobes currently developed is usually at the nanoampere (nA) level, which cannot meet commercial requirements and needs to be further reduced.
- Embodiments of the present application provide a gate tube, a gate tube preparation method and a memory, which can reduce the leakage current of the gate tube.
- a gate tube including: a first material layer, a gate tube material layer and a second material layer, wherein the first surface of the first material layer is in contact with the third surface of the gate tube material layer.
- a surface contact, the first surface of the second material layer is in contact with the second surface of the gate material layer, the first material layer and the gate material layer form a potential barrier; and/or the second material The layer forms a potential barrier with the gate material layer.
- the gate tube provided by the embodiment of the present application includes a first material layer, a gate tube material layer and a second material layer, wherein the first material layer and the gate tube material layer form a potential barrier; and/or, the second material The layer and the gate material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby reducing the leakage current of the gate tube.
- the above-mentioned first material layer and the gate tube material layer form a potential barrier, which can also be described as an interface barrier formed between the first material layer and the gate tube material layer; similarly, the above-mentioned second material layer and the gate tube material layer form an interface barrier. Forming a potential barrier can also be described as forming an interface potential barrier between the second material layer and the gate material layer.
- the difference between the first work functions of the first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the second material layer The difference from the second work function of the gate material layer is greater than or equal to 0.3 eV.
- the difference in the first work function of the first material layer and the gate material layer is greater than or equal to 0.3eV, a potential barrier will be formed between the first material layer and the gate material layer; if the second material layer The difference between the second work function and the gate material layer is greater than or equal to 0.3eV, which will cause the second material layer and the gate material layer to form a potential barrier, so that electrons can be localized in the potential barrier , thereby reducing the leakage current of the gate tube.
- the difference in the first work function is the difference between the work function of the first material layer and the work function of the gate tube material layer; the difference in the second work function is the difference between the work function of the second material layer and the gate tube material layer.
- the difference in work functions is the difference between the work function of the first material layer and the work function of the gate tube material layer.
- the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second material layer.
- the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.
- the first material layer includes a first multi-level thermal conductivity
- the first multi-level thermal conductivity is from the second surface of the first material layer to the The first surface of the first material layer gradually decreases
- the second material layer includes a second multi-level thermal conductivity from the second surface of the second material layer to the second multi-level thermal conductivity. The first surface of the second material layer is gradually reduced.
- the first material layer may include a first multi-level thermal conductivity that gradually decreases from the second surface of the first material layer to the first surface of the first material layer.
- the second material layer may include a second multi-level thermal conductivity, and the second multi-level thermal conductivity gradually decreases from the second surface of the second material layer to the first surface of the second material layer, so that It blocks the heat transfer from the outside to the material layer of the gate tube and improves the thermal stability of the gate tube.
- the first material layer includes a first buffer layer and a first electrode layer, and the first surface of the first buffer layer serves as the first surface of the first material layer. surface, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer rate; and/or, the second material layer includes a second buffer layer and a second electrode layer, the first surface of the second buffer layer serves as the first surface of the second material layer, and the first surface of the second electrode layer The surface is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.
- the introduction of the first buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can be generated between the first buffer layer and the gate tube material layer, thereby reducing the first buffer layer.
- the first multi-level thermal conductivity includes the The thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer, which can also block the external flow to the gate material layer. Heat transfer to improve the thermal stability of the gate tube.
- the second material layer includes a second buffer layer and a second electrode layer
- the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer
- the introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can be generated between the second buffer layer and the gate tube material layer, thereby reducing the second buffer layer.
- the second multi-level thermal conductivity includes the The thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer, which can also block the external flow to the gate tube material layer. Heat transfer to improve the thermal stability of the gate tube.
- the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first buffer layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second buffer layer.
- the first material layer includes a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer; and/ Or, the second material layer includes a fourth electrode layer, and the second plurality of The level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer.
- the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity is derived from the third electrode layer.
- the second surface to the first surface of the third electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate tube material layer and improving the thermal stability of the gate tube.
- the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity is from the fourth electrode layer.
- the second surface to the first surface of the fourth electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate tube material layer and improving the thermal stability of the gate tube.
- the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the third electrode layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the fourth electrode layer.
- the work function from the first surface of the third electrode layer to the second surface of the third electrode layer may decrease in a gradient; the work function from the first surface of the fourth electrode layer to the second surface of the fourth electrode layer may be Can be gradient reduced.
- the first buffer layer and/or the second buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe , any one or more of H f O 2 /TaO, WTe 2 , WS 2, etc.
- the thickness of the first buffer layer and/or the second buffer layer may be 5-20 nm.
- the above-mentioned electrode layer may include Pt , any one or more of Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO and IZO, etc., the thickness of the electrode layer can be 35-100nm.
- the gate material layer may include Te, Se or S-based binary or multi-element bidirectional threshold switch OTS materials.
- the thickness of the gate material layer Can be 10-30nm.
- the OTS material may include any of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc. one or more.
- the gate material layer may also include doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, etc. one or more of them.
- a method for preparing a gate tube including: forming a first material layer; forming a gate tube material layer on the first surface of the first material layer, and the first surface of the first material layer in contact with the first surface of the gate material layer; forming a second material layer on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer Surface contact, wherein the first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.
- the preparation method provided by the embodiment of the present application includes forming a first material layer; forming a gate tube material layer on the first surface of the first material layer, and the first surface of the first material layer is in contact with the third layer of the gate tube material layer.
- the tube material layer forms a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby reducing the leakage current of the gate tube.
- the difference in the first work function of the first material layer and the gate material layer may be greater than or equal to 0.3eV; and/or, the second material The difference between the second work function of the layer and the gate material layer may be greater than or equal to 0.3 eV.
- the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be made by adjusting the gate material layer Or any one or more of the stoichiometric ratio, doping, thickness, etc. of the second material layer.
- the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.
- the first material layer includes a first multi-level thermal conductivity
- the first multi-level thermal conductivity is from the second surface of the first material layer to the The first surface of the first material layer gradually decreases
- the second material layer includes a second multi-level thermal conductivity from the second surface of the second material layer to the second multi-level thermal conductivity. The first surface of the second material layer is gradually reduced.
- the first material layer may include a first multi-level thermal conductivity that gradually decreases from the second surface of the first material layer to the first surface of the first material layer.
- the second material layer may include a second multi-level thermal conductivity, and the second multi-level thermal conductivity gradually decreases from the second surface of the second material layer to the first surface of the second material layer, so that It blocks the heat transfer from the outside to the material layer of the gate tube and improves the thermal stability of the gate tube.
- forming the first material layer includes: forming a first electrode layer; forming a first buffer layer on the first surface of the first electrode layer, the first The first surface of the buffer layer serves as the first surface of the first material layer, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the first The thermal conductivity of the buffer layer and the thermal conductivity of the first electrode layer; and/or forming the second material layer on the second surface of the gate material layer includes: A second buffer layer is formed on both surfaces, and the first surface of the second buffer layer serves as the first surface of the second material layer; a second electrode layer is formed on the second surface of the second buffer layer, and the second electrode The first surface of the layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.
- forming the first material layer includes: forming a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer. ; and/or, forming a second material layer on the second surface of the gate material layer includes: forming a fourth electrode layer on the second surface of the gate material layer, the second multi-level thermal conductor is the multi-level thermal conductivity of the fourth electrode layer.
- the first buffer layer and/or the second buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe , any one or more of H f O 2 /TaO, WTe 2 , WS 2, etc.
- the thickness of the first buffer layer and/or the second buffer layer may be 5-20 nm.
- the above-mentioned electrode layer (any one or more of the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer) may include Pt , any one or more of Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, etc., the thickness of the electrode layer may be 35-100 nm.
- the gate material layer may include a Te, Se or S-based binary or multi-element bidirectional threshold switch OTS material, and the thickness of the gate material layer may be is 10-30nm.
- the OTS material may include any of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc. one or more.
- the gate material layer may also include doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, etc. one or more of them.
- the method of forming the first material layer, the gate material layer or the second material layer may include evaporation, sputtering, and atomic layer deposition. Any one or more of chemical vapor deposition, pulsed laser deposition, molecular beam epitaxy, etc.
- a memory chip including a plurality of memory units and a plurality of memory cells as described in the first aspect or any of the In one possible implementation of the strobe tube, each storage unit corresponds to one strobe tube.
- the memory chip may include a cross-array storage structure
- the cross-array structure storage may be a two-dimensional cross-array storage structure or a three-dimensional cross-array storage structure, without limitation.
- a fourth aspect provides a memory, including: a memory chip as described in the third aspect; and a peripheral circuit for reading and writing data in the memory chip.
- an electronic device including the memory as described in the fourth aspect.
- the electronic device may include, for example, a desktop computer, a notebook computer, a smartphone, a tablet, a personal digital assistant (PDA), a wearable device, a smart speaker, a television, a drone, a vehicle, or a vehicle-mounted device. (such as car machines, car computers, car chips, etc.) or robots, etc.
- Figure 1 is an example diagram of a memory provided by an embodiment of the present application.
- FIG. 2 is an example diagram of a cross array storage structure provided by an embodiment of the present application.
- Figure 3 is an example diagram of a gate tube provided by an embodiment of the present application.
- Figure 4 is an example diagram of another gate tube provided by the embodiment of the present application.
- Figure 5 is an example diagram of yet another gate tube provided by the embodiment of the present application.
- Figure 6 is a flow chart of a method for preparing a gate tube provided by an embodiment of the present application.
- FIG. 7 is an example diagram of yet another gate tube provided by the embodiment of the present application.
- Figure 8 is an example diagram of the microstructure of a gate tube provided by the embodiment of the present application.
- FIG. 9 is an example diagram of a voltage-current curve of a strobe provided by an embodiment of the present application.
- FIG. 10 is an example diagram of a voltage-current curve of another strobe provided by an embodiment of the present application.
- the gate tube provided in the embodiment of the present application can be applied to the field of semiconductor technology, specifically to memories in the field of semiconductor technology, to realize gating of memory cells; it can also be applied to other circuits (for example, integrated circuits) to turn the circuit on and off.
- the following uses application to memory as an example.
- Figure 1 is an example diagram of a memory provided by an embodiment of the present application.
- the memory 100 includes a peripheral circuit 110 and a memory chip 120 .
- the memory chip 120 includes a plurality of memory units.
- the peripheral circuit 110 and each memory unit in the memory chip 120 can communicate with each other.
- the peripheral circuit 110 can communicate with each other.
- 110 may include a row decoder, an amplifier, a column decoder, and other control circuits, so that the peripheral circuit 110 may control the read and write operations of each memory unit and other operations.
- the peripheral circuit 110 can write data in each storage unit; for another example, the peripheral circuit 110 can read data from each storage unit.
- FIG. 2 is an example diagram of a cross array storage structure provided by an embodiment of the present application.
- the cross array memory structure 121 includes a gate array and a memory cell array.
- the strobe tubes in the strobe tube array and the memory cells in the memory cell array are connected in series in a one-to-one correspondence.
- BL and WL in Figure 2 can be used to identify the locations of memory cells and gate tubes in the crossbar array.
- BL0 and BL1 are the bit lines where the memory cells and strobe tubes are located in the cross array
- WL0 and WL1 are the word lines where the memory cells and strobe tubes are located in the cross array.
- the positions of the gate tube 10 and the memory unit 20 in FIG. 2 can be expressed as (BL0, WL1).
- the memory unit involved in this application may be a phase change memory unit, a resistive switching memory unit, a magnetic memory unit or a ferroelectric memory unit, etc. This application does not limit this.
- the gate tube in the cross array is mainly used to gate the memory cells. Specifically, electrical signals are used to control the switching of the gate tube.
- the gate tube material is formed by high resistance.
- the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, and the gate tube is in a closed state.
- the leakage current of gate tubes currently developed is usually at the nanoampere (nA) level, which cannot meet commercial requirements and needs to be further reduced.
- embodiments of the present application form a potential barrier by designing the gate material layer and other material layers in the gate tube, so that electrons can be localized at the potential barrier to reduce the leakage current of the gate tube.
- FIG. 3 is an example diagram of a gate tube provided by an embodiment of the present application. It should be understood that the gate tube 300 shown in FIG. 3 can be applied to the memory 100 shown in FIG. 1 or the cross array memory structure 121 shown in FIG. 2 . As shown in FIG. 3 , the gate tube 300 includes a first material layer 310 , a gate tube material layer 320 and a second material layer 330 .
- the first surface 311 of the first material layer 310 is in contact with the first surface 321 of the gate material layer 320
- the first surface 331 of the second material layer 330 is in contact with the second surface 322 of the gate material layer 320 . It should be understood that the first surface 321 of the gate material layer 320 and the second surface 322 of the gate material layer 320 are two opposite surfaces of the gate material layer 320 .
- the first material layer 310 and the gate material layer 320 form a potential barrier; and/or the second material layer 330 and the gate material layer 320 form a potential barrier, so that electrons can be localized at the potential barrier, thereby enabling Reduce the leakage current of the gate tube.
- the above-mentioned first material layer 310 and the gate tube material layer 320 form a potential barrier, which can also be described as forming an interface barrier between the first material layer 310 and the gate tube material layer 320; similarly, the above-mentioned second material layer 330 and the gate tube material layer 320 form an interface barrier.
- the gate material layer 320 forms a potential barrier, which can also be described as an interface barrier formed between the second material layer 330 and the gate material layer 320 .
- the gate material layer 320 and other material layers can be designed to have work function differences, so that a potential barrier is formed between the gate material layer 320 and other material layers, so that the electrons It can be localized at the potential barrier to reduce the leakage current of the gate tube.
- the work function of the first material layer 310 is greater than the work function of the gate material layer 320, and the difference between the first work functions of the first material layer 310 and the gate material layer 320 is greater than or equal to 0.3 eV, This allows the first material layer 310 and the gate material layer 320 to form a potential barrier; and/or the work function of the second material layer 330 can be designed to be greater than the work function of the gate material layer 320, and the second material layer 330 If the difference between the second work function and the gate material layer 320 is greater than or equal to 0.3 eV, the second material layer 330 and the gate material layer 320 can form a potential barrier, so that electrons can be localized at the potential barrier, thereby It can reduce the leakage current of the gate tube.
- the difference of the first work function is the difference between the work function of the first material layer 310 and the work function of the gate material layer 320; the difference of the second work function is the difference between the work function of the second material layer 330 and the gate material layer 320.
- the difference between the first work function can be greater than or equal to 0.3eV
- the difference between the second work function can be greater than or equal to 0.3eV
- the difference between the first work function and the second work function can be greater than or equal to 0.3eV.
- the difference between the two work functions is greater than or equal to 0.3eV at the same time.
- the difference between the first work function and the second work function may be the same or different, and this application does not limit this.
- the difference between the first work function is 0.3eV, and the difference between the second work function is 0eV; or, the difference between the first work function is 0.2eV, and the difference between the second work function is 0.5eV; or, the difference between the first work function and the second work function is 0.5eV.
- the difference between the functions is 0.4eV, and the difference between the second work function is 0.3eV; or, the difference between the first work function and the second work function is both 0.3eV; or, the difference between the first work function and the second work function is 0.3eV.
- the differences in work functions are all 0.6eV.
- the difference in the first work function may be greater than or equal to 0.5eV and less than or equal to 0.65eV.
- the difference in the first work functions may be 0.5, 0.55, 0.6 or 0.65.
- the difference in the second work function can also satisfy the following range: 0.5-0.65eV.
- the difference between the second work functions may also be 0.5, 0.55, 0.6 or 0.65. It should be understood that the values of the difference between the first work function and the second work function can both meet the range of 0.5-0.65eV, or one of them can meet the above range; the difference between the first work function and the second work function The values of can be the same or different.
- the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second material layer.
- the interface barrier formed between different material layers can also be used to regulate the threshold voltage of the gate tube.
- the first material layer 310 may include a first multi-level thermal conductivity
- the first multi-level thermal conductivity is gradually from the second surface 312 of the first material layer 310 to the first surface 311 of the first material layer 310
- the second material layer 330 may include a second multi-level thermal conductivity from the second surface 332 of the second material layer 330 to a first Surface 331 decreases step by step.
- the first material layer 310 may include a first multi-level thermal conductivity from the second surface 312 of the first material layer 310 to a first surface of the first material layer 310 .
- the surface 311 gradually decreases; and/or the second material layer 330 may include a second multi-level thermal conductivity from the second surface 332 of the second material layer 330 to the second material layer 330
- the first surface 331 gradually decreases, thereby blocking the heat transfer from the outside to the gate tube material layer 320 and improving the thermal stability of the gate tube.
- the first material layer 310 may include a first buffer layer and a first electrode layer, wherein the first surface of the first buffer layer serves as the first surface of the first material layer 310.
- the first surface 311, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer.
- the first surface of the first buffer layer and the second surface of the first buffer layer are two opposite surfaces of the first buffer layer.
- the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, which means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.
- the first material layer 310 may include a first buffer layer and a first electrode layer
- the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer.
- the introduction of the first buffer layer introduces more interfaces to the gate tube, so that the interface effect (ie, phonon scattering) can be generated between the first buffer layer and the gate tube material layer 320, thereby reducing the third
- the thermal conductivity between a buffer layer and the gate tube material layer 320 can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube;
- the thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, which means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer, and can also prevent the outside world from reaching the gate tube.
- the heat transfer of the material layer 320 improves the thermal stability of the gate tube
- the difference in the first work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the first buffer layer.
- any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the first buffer layer can also be adjusted simultaneously to achieve the difference in the first work function.
- adjusting the stoichiometric ratio means adjusting the atomic percentage of each element in the material layer.
- the gate material Ge 50 S 50 of the gate material layer 320 can be adjusted to Ge 30 S 70 .
- the stoichiometric ratio or doping of the entire via material layer 320 and/or the entire first buffer layer can be adjusted, or only the via material layer 320 and the first buffer layer can be adjusted.
- the stoichiometry or doping of the contact surface of a buffer layer is not limited.
- the first buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe, Any one or more of H f O 2 /TaO, WTe 2 , WS 2 , etc.
- the thickness of the first buffer layer may be 5-20 nm.
- the first electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
- the thickness of the first electrode layer may be 35-100 nm.
- the first material layer 310 may include a third electrode layer, wherein the first surface of the third electrode layer serves as the first surface 311 of the first material layer 310, and the first multi-level thermal conductivity is Multi-level thermal conductivity of the third electrode layer. It should be understood that the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity gradually decreases from the second surface of the third electrode layer to the first surface of the third electrode layer.
- the first material layer 310 may include a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity is from the third electrode layer.
- the second surface to the first surface of the third electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate material layer 320 and improving the thermal stability of the gate tube.
- the difference in the first work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, and thickness of the gate material layer 320 or the third electrode layer.
- any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the third electrode layer can also be adjusted simultaneously to achieve the difference in the first work function.
- the stoichiometric ratio or doping of the entire via tube material layer 320 and/or the entire third electrode layer can be adjusted, or only the via tube material layer 320 and/or the via tube material layer 320 and/or the entire third electrode layer can be adjusted.
- the stoichiometric ratio or doping of the contact surface layer of the third electrode layer is not limited.
- the work function from the first surface of the third electrode layer to the second surface of the third electrode layer decreases in a gradient. It should be understood that the first surface of the third electrode layer and the second surface of the third electrode layer are two opposite surfaces of the third electrode layer. It should be understood that the work function of the third electrode layer may also exhibit other distributions without limitation.
- the third electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
- the thickness of the third electrode layer may be 35-100 nm.
- the second material layer 330 may include a second buffer layer and a second electrode layer, and the first surface of the second buffer layer serves as the first surface of the second material layer 330.
- Surface 331 the first surface of the second electrode layer is in contact with the second surface of the second buffer layer
- the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.
- the first surface of the second buffer layer and the second surface of the second buffer layer are two opposite surfaces of the second buffer layer.
- the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, which means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.
- the second material layer 330 includes a second buffer layer and a second electrode layer
- the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer
- the introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (ie, phonon scattering) can be generated between the second buffer layer and the gate tube material layer 320, thereby reducing the third
- the thermal conductivity between the second buffer layer and the gate tube material layer 320 can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube;
- the thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, which means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer, and can also prevent the outside world from reaching the gate tube.
- the heat transfer of the material layer 320 improves the thermal stability of the gate tube
- the difference in the second work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the second buffer layer.
- any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the second buffer layer can also be adjusted simultaneously to achieve the difference in the second work function.
- the entire via material layer 320 and/or the entire third can also only be adjusted to the stoichiometric ratio or doping of the via material layer 320 and/or the contact surface layer of the second buffer layer, without limitation.
- the second buffer layer may include any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe, H f O 2 /TaO, WTe 2 , WS 2, etc. kind.
- the thickness of the second buffer layer may be 5-20 nm.
- the second electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
- the thickness of the second electrode layer may be 35-100 nm.
- the second material layer 330 may include a fourth electrode layer, the first surface of the fourth electrode layer serves as the first surface 331 of the second material layer 330, and the second multi-level thermal conductivity is the fourth Multilevel thermal conductivity of electrode layers. It should be understood that the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity gradually decreases from the second surface of the fourth electrode layer to the first surface of the fourth electrode layer.
- the second material layer 330 may include a fourth electrode layer, and the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity is from the fourth electrode layer.
- the second surface to the first surface of the fourth electrode layer gradually decreases, thereby blocking the heat transfer from the outside to the gate material layer 320 and improving the thermal stability of the gate tube.
- the difference in the second work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the fourth electrode layer.
- any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the fourth electrode layer can also be adjusted simultaneously to realize the difference in the second work function.
- the stoichiometric ratio or doping of the entire via tube material layer 320 and/or the entire fourth electrode layer can be adjusted, or only the via tube material layer 320 and/or the via tube material layer 320 and/or the entire fourth electrode layer can be adjusted.
- the stoichiometric ratio or doping of the contact surface layer of the fourth electrode layer is not limited.
- the work function from the first surface of the fourth electrode layer to the second surface of the fourth electrode layer may decrease in a gradient. It should be understood that the first surface of the fourth electrode layer and the second surface of the fourth electrode layer are two opposite surfaces of the fourth electrode layer. It should be understood that the work function of the fourth electrode layer may also exhibit other distributions without limitation.
- the fourth electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
- the thickness of the fourth electrode layer may be 35-100 nm.
- the embodiments of the present application do not limit the specific combination of the first material layer and the second material layer.
- the first material layer 310 includes a first buffer layer and a first electrode layer
- the second material layer 330 includes a second buffer layer and a second electrode layer, see FIG. 4 ; or, the first material layer 310 includes a third Electrode layer
- the second material layer 330 includes a fourth electrode layer, see FIG. 5; or, the first material layer 310 includes a first buffer layer and a first electrode layer, and the second material layer 330 includes a fourth electrode layer; or, the first The material layer 310 includes a third electrode layer
- the second material layer 330 includes a second buffer layer and a second electrode layer.
- the first two examples are used as examples for description below, but it should be understood that actual applications may not be limited to these.
- the gate material layer 320 may include a Te, Se or S-based binary or multi-element bidirectional threshold switching (ovonic threshold switching, OTS) material.
- OTS ovonic threshold switching
- the thickness of the gate material layer 320 may be 10-30 nm.
- the OTS material may include any one or more of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc.
- the gate material layer 320 may also include one or more of doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, and the like.
- FIG. 4 and FIG. 5 The following takes FIG. 4 and FIG. 5 as examples to introduce the structure of the gate tube 300 .
- FIG 4 is an example diagram of another gate tube provided by the embodiment of the present application.
- the gate tube 400 includes a bottom electrode layer 410 (i.e., the above-mentioned first electrode layer), a first buffer layer 420 (i.e., the above-mentioned first buffer layer), and a gate tube material layer 430 (i.e., the above-mentioned gate tube material layer 320), a second buffer layer 440 (ie, the above-mentioned second buffer layer), and a top electrode layer 450 (ie, the above-mentioned second electrode layer).
- a bottom electrode layer 410 i.e., the above-mentioned first electrode layer
- a first buffer layer 420 i.e., the above-mentioned first buffer layer
- a gate tube material layer 430 i.e., the above-mentioned gate tube material layer 320
- a second buffer layer 440 ie, the above-mentioned second buffer layer
- the first surface 411 of the bottom electrode layer 410 is in contact with the second surface 422 of the first buffer layer 420, and the first surface 421 of the first buffer layer 420 is in contact with the first surface 431 of the gate material layer 430.
- the second surface 432 of the tube material layer 430 is in contact with the first surface 441 of the second buffer layer 440 , and the first surface 451 of the top electrode layer 450 is in contact with the second surface 442 of the second buffer layer 440 .
- the first buffer layer 420 and the gate material layer 430 form a potential barrier; or the second buffer layer 440 and the gate material layer 430 form a potential barrier; or the first buffer layer 420 and the gate material layer
- the layer 430 and the second buffer layer 440 and the gate material layer 430 all form a potential barrier.
- the difference in work functions between the first buffer layer 420 and the gate material layer 430 is greater than or equal to 0.3 eV; or, the difference in work functions between the second buffer layer 440 and the gate material layer 430 is greater than or equal to 0.3 eV; alternatively, the difference between the work functions of the first buffer layer 420 and the gate material layer 430 and the difference between the work functions of the second buffer layer 440 and the gate material layer 430 are both greater than or equal to 0.3 eV.
- the thermal conductivity of the first buffer layer 420 is less than the thermal conductivity of the bottom electrode layer 410; or, the thermal conductivity of the second buffer layer 440 is less than the thermal conductivity of the top electrode layer 450; or, the first buffer layer
- the thermal conductivity of 420 is less than that of the bottom electrode layer 410 and the thermal conductivity of the second buffer layer 440 is less than that of the top electrode layer 450 .
- the bottom electrode layer 410 the first buffer layer 420, the gate material layer 430, the second buffer layer 440, and the top electrode layer 450
- the relevant descriptions of the buffer layer, the gate material layer 320, the second buffer layer, and the second electrode layer will not be described again.
- FIG 5 is an example diagram of yet another gate tube provided by the embodiment of the present application.
- the gate tube 500 includes a bottom electrode layer 510 (i.e., the above-mentioned third electrode layer), a gate tube material layer 520 (i.e., the above-mentioned gate tube material layer 320), and a top electrode layer 530 (i.e., the above-mentioned third electrode layer). four electrode layers).
- the first surface 511 of the bottom electrode layer 510 is in contact with the first surface 521 of the gate material layer 520
- the first surface 531 of the top electrode layer 530 is in contact with the second surface 522 of the gate material layer 520 .
- the bottom electrode layer 510 and the gate material layer 520 form a potential barrier; or the top electrode layer 530 and the gate material layer 520 form a potential barrier; or the bottom electrode layer 510 and the gate material layer 520 and The top electrode layer 530 and the gate material layer 520 both form a potential barrier.
- the difference in the work functions of the bottom electrode layer 510 and the gate material layer 520 is greater than or equal to 0.3eV; or, the difference in the work functions of the top electrode layer 530 and the gate material layer 520 is greater than or equal to 0.3eV; Alternatively, the difference between the work functions of the bottom electrode layer 510 and the gate material layer 520 and the difference between the work functions of the top electrode layer 530 and the gate material layer 520 are both greater than or equal to 0.3 eV.
- the bottom electrode layer 510 includes a multi-level thermal conductivity that gradually decreases from the second surface 512 of the bottom electrode layer 510 to the first surface 511 of the bottom electrode layer 510; or, the top electrode layer 530 includes multiple levels of thermal conductivity that gradually decrease from the second surface 532 of the top electrode layer 530 to the first surface 531 of the top electrode layer 530; alternatively, the bottom electrode layer 510 includes multiple levels of thermal conductivity.
- the multi-level thermal conductivity gradually decreases from the second surface 512 of the bottom electrode layer 510 to the first surface 511 of the bottom electrode layer 510 and the top electrode layer 530 includes multi-level thermal conductivity, the multi-level thermal conductivity starts from the top The second surface 532 of the electrode layer 530 to the first surface 531 of the top electrode layer 530 gradually decreases.
- the materials and thickness limits of the bottom electrode layer 510 , the gate material layer 520 , and the top electrode layer 530 please refer to the relevant descriptions of the third electrode layer, the gate material layer 320 , and the fourth electrode layer in the gate tube 300 above. ,No longer.
- Embodiments of the present invention also provide a method for preparing a gate tube.
- FIG. 6 is a flow chart of a method for preparing a gate tube provided by embodiments of the present application. As shown in Figure 6, the method 600 includes steps S610 to S630, and these steps are introduced below.
- the first material layer may include multi-level thermal conductivity (ie, the above-mentioned first multi-level thermal conductivity), the multi-level thermal conductivity from the second surface of the first material layer to the first material layer The first surface gradually decreases, thereby blocking heat transfer from the outside to the material layer of the gate tube and improving the thermal stability of the gate tube.
- multi-level thermal conductivity ie, the above-mentioned first multi-level thermal conductivity
- forming the first material layer may include: forming a first electrode layer; forming a first buffer layer on the first surface of the first electrode layer, wherein the first surface of the first buffer layer serves as the first The first surface of the material layer and the first surface of the first electrode layer are in contact with the second surface of the first buffer layer, and the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.
- forming the first material layer may include forming a first buffer layer and a first electrode layer, and the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.
- the first buffer layer The introduction of the layer introduces more interfaces to the gate tube, so that the interface effect (that is, phonon scattering) can be generated between the first buffer layer and the gate tube material layer, thereby reducing the The thermal conductivity between the layers can hinder the heat transfer from the outside to the gate material layer and improve the thermal stability of the gate tube; on the other hand, the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer. The conductivity can also hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.
- forming the first material layer may include: forming a third electrode layer, wherein the first surface of the third electrode layer serves as the first surface of the first material layer, and the third electrode layer includes a plurality of The multi-level thermal conductivity gradually decreases from the second surface of the third electrode layer to the first surface of the third electrode layer, which can hinder the heat transfer from the outside to the gate tube material layer and improve the gate. Thermal stability of the tube.
- S620 Form a gate material layer on the first surface of the first material layer, and the first surface of the first material layer is in contact with the first surface of the gate material layer.
- S630 Form a second material layer on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer.
- the second material layer may include a multi-level thermal conductivity (and the above-mentioned second multi-level thermal conductivity), the multi-level thermal conductivity from the second surface of the second material layer to the second surface of the second material layer.
- the first surface gradually decreases, thereby blocking heat transfer from the outside to the material layer of the gate tube and improving the thermal stability of the gate tube.
- forming the second material layer on the second surface of the gate material layer may include: forming a second buffer layer on the second surface of the gate material layer, the second buffer layer having a A surface serves as the first surface of the second material layer; a second electrode layer is formed on the second surface of the second buffer layer, and the first surface of the second electrode layer is in contact with the second surface of the second buffer layer , the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.
- forming the second material layer may include forming a second buffer layer and a second electrode layer, and the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.
- the second buffer layer The introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can occur between the second buffer layer and the gate tube material layer, thereby reducing the The thermal conductivity between the layers can hinder the heat transfer from the outside to the gate material layer and improve the thermal stability of the gate tube; on the other hand, the thermal conductivity of the second buffer layer is smaller than that of the second electrode layer. The conductivity can also hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.
- forming the second material layer on the second surface of the gate material layer may include: forming a fourth electrode layer on the second surface of the gate material layer, the fourth The first surface of the electrode layer serves as the first surface of the second material layer, and the fourth electrode layer may include multi-level thermal conductivity from the second surface of the fourth electrode layer to the fourth electrode.
- the first surface of the layer decreases step by step, which can hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.
- first material layer and the gate material layer form a potential barrier; and/or the second material layer and the gate material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby It can reduce the leakage current of the gate tube.
- the difference in the first work function of the above-mentioned first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the difference in the second work function of the second material layer and the gate material layer is greater than or equal to 0.3eV. It should be understood that the specific description of the work function can be found above and will not be described again.
- the method of forming the first material layer, the gate material layer or the second material layer may include evaporation, sputtering, atomic layer deposition, chemical vapor deposition, pulsed laser deposition, and molecular beam epitaxy. any one or more of the following.
- first material layer the gate material layer and the second material layer, which is not limited in this application.
- the electrode layer 720 and the insulating layer 730 may be sequentially prepared on the substrate 710 , and then features may be formed on the insulating layer 730 through photolithography and etching processes. For small holes with a size of 80-500 nm, step S610 is performed again.
- a first electrode layer 410 is formed in a small hole, the surface is planarized through a chemical polishing process, and then a first electrode layer 410 is formed on the first electrode layer 410 on the planarized surface.
- a buffer layer 420 continue to perform steps S620 and S630 on the first buffer layer 420, for example, the gate material layer 430, the second buffer layer 440 and the second electrode layer 450 can be sequentially formed on the first buffer layer 420;
- the third electrode layer 510 is formed in the small hole, and the surface is planarized through a chemical polishing process, and then continues on the third electrode layer 510 with the planarized surface.
- Steps S620 and S630 are performed, for example, the gate material layer 520 and the fourth electrode layer 530 may be sequentially formed on the third electrode layer 510 .
- photolithography and etching techniques can also be used to form a gate tube with a final specified size, for example, a gate tube with a characteristic size of 50 nm.
- the above-mentioned substrate may be a Si substrate or SiO 2 substrate. It should be understood that the above characteristic dimensions can be understood as the length, width or diameter of the gate tube surface, and are not limited thereto.
- FIG. 8 is an example diagram of the microstructure of a gate tube provided by an embodiment of the present application. It should be understood that the gate tube shown in FIG. 8 is an example of the gate tube shown in FIG. 4 . As shown in FIG. 8 , in this gate tube, the material selected for the bottom electrode layer 410 is W, the material selected for the first buffer layer 420 is a C-S compound, and the material selected for the gate material layer 430 is a Ge-S compound. The material selected for the second buffer layer 440 is C-S compound, and the material selected for the top electrode layer 450 is TiN.
- an interface barrier is formed between the first buffer layer 420 and the gate material layer 430 and between the second buffer layer 440 and the gate material layer 430; the first buffer layer 420 and the gate material layer 430 form an interface barrier.
- the difference in work functions of the pass tube material layer 430 and the difference in work functions of the second buffer layer 440 and the gate tube material layer 430 are both approximately greater than 0.3 eV; the thermal conductivity of the first buffer layer 420 is smaller than that of the bottom electrode layer 410 The conductivity and thermal conductivity of the second buffer layer 440 are less than the thermal conductivity of the top electrode layer 450 .
- the microstructure shown in Figure 8 is the microstructure of the gate tube after annealing at 400°C. It can be seen from Figure 8 that the first buffer layer CS, the gate tube material layer Ge-S and the second The sandwich heterostructure formed by the buffer layer CS remains in an amorphous state after annealing and does not undergo crystalline phase change, which means that the gate tube has high thermal stability. This is because, on the one hand, the introduction of the first buffer layer and the second buffer layer introduces more interfaces to the gate tube, so that the buffer layer and the gate tube material The interface effect (i.e.
- thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the bottom electrode layer and the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the top electrode layer, hindering the external access to the gate
- the heat transfer of the tube material layer further improves the thermal stability of the gate tube.
- FIG. 9 is an example diagram of a voltage-current curve of a strobe provided by an embodiment of the present application. Specifically, FIG. 9 is an example diagram of the voltage-current curve tested after the gate tube shown in FIG. 8 was annealed at 400° C. for 30 minutes. As shown in Figure 9, it can be seen that the gate tube can still maintain stable switching characteristics after annealing at 400°C for 30 minutes.
- FIG. 10 is an example diagram of a voltage-current curve of another strobe provided by an embodiment of the present application. Specifically, FIG. 10 is a partial enlarged view of FIG. 9 , and it can be seen that the leakage current of the gate tube is less than 400 pA.
- the gate tube provided by the embodiment of the present application has the advantages of high thermal stability and low leakage current. And the leakage current is reduced to the pA level, so it can meet the needs of high-density integration of memory cells.
- An embodiment of the present application also provides a memory chip, which includes a plurality of memory units and a plurality of strobe tubes provided in the embodiments of the present application, with each memory unit corresponding to a strobe tube.
- the memory chip may include a cross-array storage structure
- the cross-array storage structure may be a two-dimensional cross-array storage structure or a three-dimensional cross-array storage structure, without limitation.
- An embodiment of the present application also provides a memory, which includes: the memory chip provided in the embodiment of the present application; and a peripheral circuit for reading and writing data in the memory chip.
- An embodiment of the present application also provides an electronic device, including the memory provided in the embodiment of the present application.
- the electronic device may include, for example, a desktop computer, a notebook computer, a smartphone, a tablet, a personal digital assistant (PDA), a wearable device, a smart speaker, a television, a drone, a vehicle, or a vehicle-mounted device. (such as car machines, car computers, car chips, etc.) or robots, etc.
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Abstract
Embodiments of the present application provide a gating tube, a preparation method for the gating tube, and a memory. The gating tube comprises a first material layer, a gating tube material layer, and a second material layer. A first surface of the first material layer is in contact with a first surface of the gating tube material layer, a first surface of the second material layer is in contact with a second surface of the gating tube material layer, and the first material layer and the gating tube material layer form a potential barrier; and/or, the second material layer and the gating tube material layer form a potential barrier. According to the solution of the present application, electrons can be localized at the potential barrier, such that a leakage current of the gating tube can be reduced.
Description
本申请要求于2022年3月31日提交中国专利局、申请号为202210346270.2、发明名称为“选通管、选通管的制备方法及存储器”的中国专利申请的优先权,所述专利申请的全部内容通过引用结合在本申请中。This application claims the priority of the Chinese patent application submitted to the China Patent Office on March 31, 2022, with the application number 202210346270.2 and the invention name "Gate tube, gate tube preparation method and memory". The patent application The entire contents are incorporated herein by reference.
本申请实施例涉及半导体技术领域,并且更具体地,涉及一种选通管、选通管的制备方法及存储器。Embodiments of the present application relate to the field of semiconductor technology, and more specifically, to a gate tube, a gate tube preparation method, and a memory.
随着大数据、云计算和物联网行业的蓬勃发展,伴随着海量信息爆炸式增长和不断膨胀的市场需求,对存储器的存储密度及容量都提出了更高的要求,各种新型高性能存储技术也应运而生,例如交叉阵列存储技术等。With the vigorous development of the big data, cloud computing and Internet of Things industries, along with the explosive growth of massive information and expanding market demand, higher requirements have been placed on the storage density and capacity of memories. Various new high-performance storage Technologies have also emerged, such as cross array storage technology.
在各种存储技术中,通常需要采用选通管对存储单元进行选通,具体地,利用电学信号控制选通管的开关,当施加电学信号于选通管时,选通管材料由高阻态向低阻态转变,选通管处于开启状态;当撤去电学信号时,选通管材料又由低阻态转变成高阻态,选通管处于关闭状态。然而,目前所研发的大多数选通管的泄露电流通常处于纳安(nA)级别,无法满足商用要求,有待进一步降低。In various storage technologies, it is usually necessary to use a gate tube to gate the memory unit. Specifically, an electrical signal is used to control the switch of the gate tube. When an electrical signal is applied to the gate tube, the gate tube material changes from a high resistance state to a gate tube. When the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, and the gate tube is in a closed state. However, the leakage current of most strobes currently developed is usually at the nanoampere (nA) level, which cannot meet commercial requirements and needs to be further reduced.
发明内容Contents of the invention
本申请实施例提供一种选通管、选通管的制备方法及存储器,能够降低选通管的泄露电流。Embodiments of the present application provide a gate tube, a gate tube preparation method and a memory, which can reduce the leakage current of the gate tube.
第一方面,提供了一种选通管,包括:第一材料层、选通管材料层和第二材料层,其中,该第一材料层的第一表面与该选通管材料层的第一表面接触,该第二材料层的第一表面与该选通管材料层的第二表面接触,该第一材料层与该选通管材料层形成势垒;和/或,该第二材料层与该选通管材料层形成势垒。In a first aspect, a gate tube is provided, including: a first material layer, a gate tube material layer and a second material layer, wherein the first surface of the first material layer is in contact with the third surface of the gate tube material layer. A surface contact, the first surface of the second material layer is in contact with the second surface of the gate material layer, the first material layer and the gate material layer form a potential barrier; and/or the second material The layer forms a potential barrier with the gate material layer.
本申请实施例所提供的选通管包括第一材料层、选通管材料层和第二材料层,其中,第一材料层与选通管材料层形成势垒;和/或,第二材料层与选通管材料层形成势垒,使得电子可以局域在势垒处,从而能够降低选通管的泄露电流。The gate tube provided by the embodiment of the present application includes a first material layer, a gate tube material layer and a second material layer, wherein the first material layer and the gate tube material layer form a potential barrier; and/or, the second material The layer and the gate material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby reducing the leakage current of the gate tube.
上述第一材料层与选通管材料层形成势垒,也可以描述为第一材料层与选通管材料层之间形成界面势垒;同样地,上述第二材料层与选通管材料层形成势垒,也可以描述为第二材料层与选通管材料层之间形成界面势垒。The above-mentioned first material layer and the gate tube material layer form a potential barrier, which can also be described as an interface barrier formed between the first material layer and the gate tube material layer; similarly, the above-mentioned second material layer and the gate tube material layer form an interface barrier. Forming a potential barrier can also be described as forming an interface potential barrier between the second material layer and the gate material layer.
结合第一方面,在第一方面的某些实现方式中,该第一材料层与该选通管材料层的第一功函数之差大于或等于0.3eV;和/或,该第二材料层与该选通管材料层的第二功函数之差大于或等于0.3eV。In connection with the first aspect, in some implementations of the first aspect, the difference between the first work functions of the first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the second material layer The difference from the second work function of the gate material layer is greater than or equal to 0.3 eV.
应理解,若第一材料层与选通管材料层的第一功函数之差大于或等于0.3eV,就会使得在第一材料层与选通管材料层形成势垒;若第二材料层与选通管材料层的第二功函数之差大于或等于0.3eV,就会使得第二材料层与选通管材料层形成势垒,使得电子可以局域在势垒
处,从而能够降低选通管的泄露电流。It should be understood that if the difference in the first work function of the first material layer and the gate material layer is greater than or equal to 0.3eV, a potential barrier will be formed between the first material layer and the gate material layer; if the second material layer The difference between the second work function and the gate material layer is greater than or equal to 0.3eV, which will cause the second material layer and the gate material layer to form a potential barrier, so that electrons can be localized in the potential barrier , thereby reducing the leakage current of the gate tube.
应理解,第一功函数之差为第一材料层的功函数与选通管材料层的功函数的差值;第二功函数之差为第二材料层的功函数与选通管材料层的功函数的差值。It should be understood that the difference in the first work function is the difference between the work function of the first material layer and the work function of the gate tube material layer; the difference in the second work function is the difference between the work function of the second material layer and the gate tube material layer. The difference in work functions.
可选地,第一功函数之差可以是通过调节该选通管材料层或者第一材料层的化学计量比、掺杂、厚度等中的任意一种或多种实现的;第二功函数之差可以是通过调节该选通管材料层或者第二材料层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second material layer.
结合第一方面,在第一方面的某些实现方式中,该第一功函数之差和/或该第二功函数之差大于或等于0.5eV,且小于或等于0.65eV。In conjunction with the first aspect, in some implementations of the first aspect, the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.
结合第一方面,在第一方面的某些实现方式中,该第一材料层包括第一多级热导率,该第一多级热导率从该第一材料层的第二表面至该第一材料层的第一表面逐级递减;和/或,该第二材料层包括第二多级热导率,该第二多级热导率从该第二材料层的第二表面至该第二材料层的第一表面逐级递减。In connection with the first aspect, in some implementations of the first aspect, the first material layer includes a first multi-level thermal conductivity, the first multi-level thermal conductivity is from the second surface of the first material layer to the The first surface of the first material layer gradually decreases; and/or the second material layer includes a second multi-level thermal conductivity from the second surface of the second material layer to the second multi-level thermal conductivity. The first surface of the second material layer is gradually reduced.
在本申请实施例中,第一材料层可以包括第一多级热导率,该第一多级热导率从第一材料层的第二表面至第一材料层的第一表面逐级递减;和/或,第二材料层可以包括第二多级热导率,第二多级热导率从第二材料层的第二表面至第二材料层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, the first material layer may include a first multi-level thermal conductivity that gradually decreases from the second surface of the first material layer to the first surface of the first material layer. ; and/or, the second material layer may include a second multi-level thermal conductivity, and the second multi-level thermal conductivity gradually decreases from the second surface of the second material layer to the first surface of the second material layer, so that It blocks the heat transfer from the outside to the material layer of the gate tube and improves the thermal stability of the gate tube.
结合第一方面,在第一方面的某些实现方式中,该第一材料层包括第一缓冲层和第一电极层,该第一缓冲层的第一表面作为该第一材料层的第一表面,该第一电极层的第一表面与该第一缓冲层的第二表面接触,该第一多级热导率包括该第一缓冲层的热导率和该第一电极层的热导率;和/或,该第二材料层包括第二缓冲层和第二电极层,该第二缓冲层的第一表面作为该第二材料层的第一表面,该第二电极层的第一表面与该第二缓冲层的第二表面接触,该第二多级热导率包括该第二缓冲层的热导率和该第二电极层的热导率。In conjunction with the first aspect, in some implementations of the first aspect, the first material layer includes a first buffer layer and a first electrode layer, and the first surface of the first buffer layer serves as the first surface of the first material layer. surface, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer rate; and/or, the second material layer includes a second buffer layer and a second electrode layer, the first surface of the second buffer layer serves as the first surface of the second material layer, and the first surface of the second electrode layer The surface is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.
在本申请实施例中,若第一材料层包括第一缓冲层和第一电极层,且第一多级热导率包括第一缓冲层的热导率和第一电极层的热导率,一方面,第一缓冲层的引入为选通管引入了更多的界面,使得第一缓冲层与选通管材料层之间可以产生界面效应(即声子散射),从而能够降低第一缓冲层与选通管材料层之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性;另一方面,第一多级热导率包括该第一缓冲层的热导率和该第一电极层的热导率,意味着第一缓冲层的热导率小于第一电极层的热导率,也可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, if the first material layer includes a first buffer layer and a first electrode layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, On the one hand, the introduction of the first buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can be generated between the first buffer layer and the gate tube material layer, thereby reducing the first buffer layer. The thermal conductivity between the layer and the gate tube material layer can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the first multi-level thermal conductivity includes the The thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer, which can also block the external flow to the gate material layer. Heat transfer to improve the thermal stability of the gate tube.
在本申请实施例中,若第二材料层包括第二缓冲层和第二电极层,且第二多级热导率包括第二缓冲层的热导率和第二电极层的热导率,一方面,第二缓冲层的引入为选通管引入了更多的界面,使得第二缓冲层与选通管材料层之间可以产生界面效应(即声子散射),从而能够降低第二缓冲层与选通管材料层之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性;另一方面,第二多级热导率包括该第二缓冲层的热导率和该第二电极层的热导率,意味着第二缓冲层的热导率小于第二电极层的热导率,也可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, if the second material layer includes a second buffer layer and a second electrode layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, On the one hand, the introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can be generated between the second buffer layer and the gate tube material layer, thereby reducing the second buffer layer. The thermal conductivity between the layer and the gate tube material layer can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the second multi-level thermal conductivity includes the The thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer, which can also block the external flow to the gate tube material layer. Heat transfer to improve the thermal stability of the gate tube.
可选地,第一功函数之差可以是通过调节该选通管材料层或者第一缓冲层的化学计量比、掺杂、厚度等中的任意一种或多种实现的;第二功函数之差可以是通过调节选通管材料层或者第二缓冲层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first buffer layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second buffer layer.
结合第一方面,在第一方面的某些实现方式中,该第一材料层包括第三电极层,该第一多级热导率为该第三电极层的多级热导率;和/或,该第二材料层包括第四电极层,该第二多
级热导率为该第四电极层的多级热导率。In conjunction with the first aspect, in some implementations of the first aspect, the first material layer includes a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer; and/ Or, the second material layer includes a fourth electrode layer, and the second plurality of The level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer.
在本申请实施例中,若第一材料层包括第三电极层,该第一多级热导率为该第三电极层的多级热导率,意味着热导率从第三电极层的第二表面至第三电极层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, if the first material layer includes a third electrode layer, the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity is derived from the third electrode layer. The second surface to the first surface of the third electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate tube material layer and improving the thermal stability of the gate tube.
在本申请实施例中,若第二材料层包括第四电极层,该第二多级热导率为该第四电极层的多级热导率,意味着热导率从第四电极层的第二表面至第四电极层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, if the second material layer includes a fourth electrode layer, the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity is from the fourth electrode layer. The second surface to the first surface of the fourth electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate tube material layer and improving the thermal stability of the gate tube.
可选地,第一功函数之差可以是通过调节该选通管材料层或者第三电极层的化学计量比、掺杂、厚度等中的任意一种或多种实现的;第二功函数之差可以是通过调节选通管材料层或者第四电极层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the third electrode layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the fourth electrode layer.
可选地,第三电极层的第一表面至该第三电极层的第二表面的功函数可以呈梯度递减;第四电极层的第一表面至第四电极层的第二表面的功函数可以呈梯度递减。Optionally, the work function from the first surface of the third electrode layer to the second surface of the third electrode layer may decrease in a gradient; the work function from the first surface of the fourth electrode layer to the second surface of the fourth electrode layer may be Can be gradient reduced.
结合第一方面,在第一方面的某些实现方式中,该第一缓冲层和/或该第二缓冲层可以包括非晶碳、SiC、CS、TeC、TeCS、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2等中的任意一种或多种。In connection with the first aspect, in some implementations of the first aspect, the first buffer layer and/or the second buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe , any one or more of H f O 2 /TaO, WTe 2 , WS 2, etc.
结合第一方面,在第一方面的某些实现方式中,该第一缓冲层和/或该第二缓冲层的厚度可以为5-20nm。In conjunction with the first aspect, in some implementations of the first aspect, the thickness of the first buffer layer and/or the second buffer layer may be 5-20 nm.
结合第一方面,在第一方面的某些实现方式中,上述电极层(第一电极层、第二电极层、第三电极层及第四电极层中的任意一个或多个)可以包括Pt、Ti、W、Au、Ru、Al、TiW、TiN、TaN、IrO2、ITO以及IZO等中的任意一种或多种,电极层的厚度可以为35-100nm。In connection with the first aspect, in some implementations of the first aspect, the above-mentioned electrode layer (any one or more of the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer) may include Pt , any one or more of Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO and IZO, etc., the thickness of the electrode layer can be 35-100nm.
结合第一方面,在第一方面的某些实现方式中,该选通管材料层可以包括Te、Se或S基等的二元或者多元双向阈值开关OTS材料,该选通管材料层的厚度可以为10-30nm。In conjunction with the first aspect, in some implementations of the first aspect, the gate material layer may include Te, Se or S-based binary or multi-element bidirectional threshold switch OTS materials. The thickness of the gate material layer Can be 10-30nm.
结合第一方面,在第一方面的某些实现方式中,该OTS材料可以包括GeTe、CTe、BTe、SiTe、AlTe、ZnTe、CdTe、NTe、MgTe、CaTe、GaTe、GeS、GeSe等中的任意一种或多种。In connection with the first aspect, in some implementations of the first aspect, the OTS material may include any of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc. one or more.
结合第一方面,在第一方面的某些实现方式中,该选通管材料层还可以包括掺杂元素B、C、N、Ge、Si、Al、Zn、Ga、S、Se、As等中的一种或多种。In connection with the first aspect, in some implementations of the first aspect, the gate material layer may also include doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, etc. one or more of them.
第二方面,提供了一种选通管的制备方法,包括:形成第一材料层;在该第一材料层的第一表面上形成选通管材料层,该第一材料层的第一表面与该选通管材料层的第一表面接触;在该选通管材料层的第二表面上形成第二材料层,该第二材料层的第一表面与该选通管材料层的第二表面接触,其中,该第一材料层与该选通管材料层形成势垒;和/或,该第二材料层与该选通管材料层形成势垒。In a second aspect, a method for preparing a gate tube is provided, including: forming a first material layer; forming a gate tube material layer on the first surface of the first material layer, and the first surface of the first material layer in contact with the first surface of the gate material layer; forming a second material layer on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer Surface contact, wherein the first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.
本申请实施例所提供的制备方法包括形成第一材料层;在第一材料层的第一表面上形成选通管材料层,第一材料层的第一表面与该选通管材料层的第一表面接触;在选通管材料层的第二表面上形成第二材料层,第二材料层的第一表面与选通管材料层的第二表面接触,其中,第一材料层与选通管材料层形成势垒;和/或,第二材料层与选通管材料层形成势垒,使得电子可以局域在势垒处,从而能够降低选通管的泄露电流。The preparation method provided by the embodiment of the present application includes forming a first material layer; forming a gate tube material layer on the first surface of the first material layer, and the first surface of the first material layer is in contact with the third layer of the gate tube material layer. A surface contact; a second material layer is formed on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer, wherein the first material layer and the gate The tube material layer forms a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby reducing the leakage current of the gate tube.
结合第二方面,在第二方面的某些实现方式中,该第一材料层与该选通管材料层的第一功函数之差可以大于或等于0.3eV;和/或,该第二材料层与该选通管材料层的第二功函数之差可以大于或等于0.3eV。In conjunction with the second aspect, in some implementations of the second aspect, the difference in the first work function of the first material layer and the gate material layer may be greater than or equal to 0.3eV; and/or, the second material The difference between the second work function of the layer and the gate material layer may be greater than or equal to 0.3 eV.
可选地,第一功函数之差可以是通过调节该选通管材料层或者第一材料层的化学计量比、掺杂、厚度等中的任意一种或多种实现的;第二功函数之差可以是通过调节该选通管材料层
或者第二材料层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be made by adjusting the gate material layer Or any one or more of the stoichiometric ratio, doping, thickness, etc. of the second material layer.
结合第二方面,在第二方面的某些实现方式中,该第一功函数之差和/或该第二功函数之差大于或等于0.5eV,且小于或等于0.65eV。Combined with the second aspect, in some implementations of the second aspect, the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.
结合第二方面,在第二方面的某些实现方式中,该第一材料层包括第一多级热导率,该第一多级热导率从该第一材料层的第二表面至该第一材料层的第一表面逐级递减;和/或,该第二材料层包括第二多级热导率,该第二多级热导率从该第二材料层的第二表面至该第二材料层的第一表面逐级递减。In conjunction with the second aspect, in some implementations of the second aspect, the first material layer includes a first multi-level thermal conductivity, the first multi-level thermal conductivity is from the second surface of the first material layer to the The first surface of the first material layer gradually decreases; and/or the second material layer includes a second multi-level thermal conductivity from the second surface of the second material layer to the second multi-level thermal conductivity. The first surface of the second material layer is gradually reduced.
在本申请实施例中,第一材料层可以包括第一多级热导率,该第一多级热导率从第一材料层的第二表面至第一材料层的第一表面逐级递减;和/或,第二材料层可以包括第二多级热导率,第二多级热导率从第二材料层的第二表面至第二材料层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, the first material layer may include a first multi-level thermal conductivity that gradually decreases from the second surface of the first material layer to the first surface of the first material layer. ; and/or, the second material layer may include a second multi-level thermal conductivity, and the second multi-level thermal conductivity gradually decreases from the second surface of the second material layer to the first surface of the second material layer, so that It blocks the heat transfer from the outside to the material layer of the gate tube and improves the thermal stability of the gate tube.
结合第二方面,在第二方面的某些实现方式中,该形成第一材料层包括:形成第一电极层;在该第一电极层的第一表面上形成第一缓冲层,该第一缓冲层的第一表面作为该第一材料层的第一表面,该第一电极层的第一表面与该第一缓冲层的第二表面接触,该第一多级热导率包括该第一缓冲层的热导率和该第一电极层的热导率;和/或,该在该选通管材料层的第二表面上形成第二材料层包括:在该选通管材料层的第二表面上形成第二缓冲层,该第二缓冲层的第一表面作为该第二材料层的第一表面;在该第二缓冲层的第二表面上形成第二电极层,该第二电极层的第一表面与该第二缓冲层的第二表面接触,该第二多级热导率包括该第二缓冲层的热导率和该第二电极层的热导率。In conjunction with the second aspect, in some implementations of the second aspect, forming the first material layer includes: forming a first electrode layer; forming a first buffer layer on the first surface of the first electrode layer, the first The first surface of the buffer layer serves as the first surface of the first material layer, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the first The thermal conductivity of the buffer layer and the thermal conductivity of the first electrode layer; and/or forming the second material layer on the second surface of the gate material layer includes: A second buffer layer is formed on both surfaces, and the first surface of the second buffer layer serves as the first surface of the second material layer; a second electrode layer is formed on the second surface of the second buffer layer, and the second electrode The first surface of the layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer.
结合第二方面,在第二方面的某些实现方式中,该形成第一材料层包括:形成第三电极层,该第一多级热导率为该第三电极层的多级热导率;和/或,该在该选通管材料层的第二表面上形成第二材料层包括:在该选通管材料层的第二表面上形成第四电极层,该第二多级热导率为该第四电极层的多级热导率。In conjunction with the second aspect, in some implementations of the second aspect, forming the first material layer includes: forming a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer. ; and/or, forming a second material layer on the second surface of the gate material layer includes: forming a fourth electrode layer on the second surface of the gate material layer, the second multi-level thermal conductor is the multi-level thermal conductivity of the fourth electrode layer.
结合第二方面,在第二方面的某些实现方式中,该第一缓冲层和/或该第二缓冲层可以包括非晶碳、SiC、CS、TeC、TeCS、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2等中的任意一种或多种。In conjunction with the second aspect, in some implementations of the second aspect, the first buffer layer and/or the second buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe , any one or more of H f O 2 /TaO, WTe 2 , WS 2, etc.
结合第二方面,在第二方面的某些实现方式中,该第一缓冲层和/或该第二缓冲层的厚度可以为5-20nm。In conjunction with the second aspect, in some implementations of the second aspect, the thickness of the first buffer layer and/or the second buffer layer may be 5-20 nm.
结合第二方面,在第二方面的某些实现方式中,上述电极层(第一电极层、第二电极层、第三电极层及第四电极层中的任意一个或多个)可以包括Pt、Ti、W、Au、Ru、Al、TiW、TiN、TaN、IrO2、ITO以及IZO等中的任意一种或多种,该电极层的厚度可以为35-100nm。In connection with the second aspect, in some implementations of the second aspect, the above-mentioned electrode layer (any one or more of the first electrode layer, the second electrode layer, the third electrode layer and the fourth electrode layer) may include Pt , any one or more of Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, etc., the thickness of the electrode layer may be 35-100 nm.
结合第二方面,在第二方面的某些实现方式中,该选通管材料层可以包括Te、Se或S基的二元或者多元双向阈值开关OTS材料,该选通管材料层的厚度可以为10-30nm。In connection with the second aspect, in some implementations of the second aspect, the gate material layer may include a Te, Se or S-based binary or multi-element bidirectional threshold switch OTS material, and the thickness of the gate material layer may be is 10-30nm.
结合第二方面,在第二方面的某些实现方式中,该OTS材料可以包括GeTe、CTe、BTe、SiTe、AlTe、ZnTe、CdTe、NTe、MgTe、CaTe、GaTe、GeS、GeSe等中的任意一种或多种。Combined with the second aspect, in some implementations of the second aspect, the OTS material may include any of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc. one or more.
结合第二方面,在第二方面的某些实现方式中,该选通管材料层还可以包括掺杂元素B、C、N、Ge、Si、Al、Zn、Ga、S、Se、As等中的一种或多种。In conjunction with the second aspect, in some implementations of the second aspect, the gate material layer may also include doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, etc. one or more of them.
结合第二方面,在第二方面的某些实现方式中,形成该第一材料层、该选通管材料层或该第二材料层的方法可以包括蒸镀法、溅射法、原子层沉积法、化学气相沉积法、脉冲激光沉积法、分子束外延法等中的任意一种或多种。In connection with the second aspect, in some implementations of the second aspect, the method of forming the first material layer, the gate material layer or the second material layer may include evaporation, sputtering, and atomic layer deposition. Any one or more of chemical vapor deposition, pulsed laser deposition, molecular beam epitaxy, etc.
第三方面,提供了一种存储芯片,包括多个存储单元和多个如第一方面或第一方面中任
一可能实现方式中的选通管,每个存储单元对应一个选通管。In a third aspect, a memory chip is provided, including a plurality of memory units and a plurality of memory cells as described in the first aspect or any of the In one possible implementation of the strobe tube, each storage unit corresponds to one strobe tube.
可选地,该存储芯片可以包括交叉阵列存储结构,该交叉阵列结构存储可以为二维交叉阵列存储结构,也可以为三维交叉阵列存储结构,不做限定。Optionally, the memory chip may include a cross-array storage structure, and the cross-array structure storage may be a two-dimensional cross-array storage structure or a three-dimensional cross-array storage structure, without limitation.
第四方面,提供了一种存储器,包括:如第三方面所述的存储芯片;外围电路,用于对存储芯片中的数据进行读写操作。A fourth aspect provides a memory, including: a memory chip as described in the third aspect; and a peripheral circuit for reading and writing data in the memory chip.
第五方面,提供了一种电子设备,包括如第四方面所述的存储器。可选地,该电子设备例如可以包括台式电脑、笔记本电脑、智能手机、平板电脑、个人数字助理(personal digital assistant,PDA)、可穿戴设备、智能音箱、电视、无人机、车辆、车载装置(例如车机、车载电脑、车载芯片等)或机器人等等。In a fifth aspect, an electronic device is provided, including the memory as described in the fourth aspect. Optionally, the electronic device may include, for example, a desktop computer, a notebook computer, a smartphone, a tablet, a personal digital assistant (PDA), a wearable device, a smart speaker, a television, a drone, a vehicle, or a vehicle-mounted device. (such as car machines, car computers, car chips, etc.) or robots, etc.
图1是本申请实施例提供的一种存储器的示例图。Figure 1 is an example diagram of a memory provided by an embodiment of the present application.
图2是本申请实施例提供的一种交叉阵列存储结构示例图。FIG. 2 is an example diagram of a cross array storage structure provided by an embodiment of the present application.
图3是本申请实施例提供的一种选通管的示例图。Figure 3 is an example diagram of a gate tube provided by an embodiment of the present application.
图4是本申请实施例提供的另一种选通管的示例图。Figure 4 is an example diagram of another gate tube provided by the embodiment of the present application.
图5是本申请实施例提供的又一种选通管的示例图。Figure 5 is an example diagram of yet another gate tube provided by the embodiment of the present application.
图6是本申请实施例提供的一种选通管的制备方法的流程图。Figure 6 is a flow chart of a method for preparing a gate tube provided by an embodiment of the present application.
图7是本申请实施例提供的再一种选通管的示例图。FIG. 7 is an example diagram of yet another gate tube provided by the embodiment of the present application.
图8是本申请实施例提供的一种选通管的微观结构示例图Figure 8 is an example diagram of the microstructure of a gate tube provided by the embodiment of the present application.
图9是本申请实施例提供的一种选通管的电压-电流曲线示例图。FIG. 9 is an example diagram of a voltage-current curve of a strobe provided by an embodiment of the present application.
图10是本申请实施例提供的另一种选通管的电压-电流曲线示例图。FIG. 10 is an example diagram of a voltage-current curve of another strobe provided by an embodiment of the present application.
下面将结合附图,对本申请实施例中的技术方案进行描述。The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.
首先需要说明的是,本申请实施例所提供的选通管可以应用于半导体技术领域,具体可以应用于半导体技术领域中的存储器,以实现存储单元的选通;也可以应用于其他电路中(例如,集成电路),以实现电路的开启和关闭。为便于描述,下文以应用于存储器为例进行介绍。First of all, it should be noted that the gate tube provided in the embodiment of the present application can be applied to the field of semiconductor technology, specifically to memories in the field of semiconductor technology, to realize gating of memory cells; it can also be applied to other circuits ( For example, integrated circuits) to turn the circuit on and off. For the convenience of description, the following uses application to memory as an example.
图1是本申请实施例提供的一种存储器的示例图。如图1所示,该存储器100包括外围电路110和存储芯片120,其中,存储芯片120包括多个存储单元,外围电路110与存储芯片120中的每个存储单元之间可以相互通信,外围电路110可以包括行译码器、放大器、列译码器以及其他控制电路等,从而,外围电路110可以控制每个存储单元的读写操作以及其他操作。例如,外围电路110可以在每个存储单元中写入数据;再例如,外围电路110可以从每个存储单元中读取数据。Figure 1 is an example diagram of a memory provided by an embodiment of the present application. As shown in FIG. 1 , the memory 100 includes a peripheral circuit 110 and a memory chip 120 . The memory chip 120 includes a plurality of memory units. The peripheral circuit 110 and each memory unit in the memory chip 120 can communicate with each other. The peripheral circuit 110 can communicate with each other. 110 may include a row decoder, an amplifier, a column decoder, and other control circuits, so that the peripheral circuit 110 may control the read and write operations of each memory unit and other operations. For example, the peripheral circuit 110 can write data in each storage unit; for another example, the peripheral circuit 110 can read data from each storage unit.
随着大数据、云计算和物联网行业的蓬勃发展,伴随着海量信息爆炸式增长和不断膨胀的市场需求,对存储器的存储密度及容量都提出了更高的要求,各种新型高性能存储技术也应运而生,例如,交叉阵列存储技术。下面以图2所示的交叉阵列存储结构121为例对存储芯片120的结构进行示例性介绍。图2是本申请实施例提供的一种交叉阵列存储结构的示例图。如图2所示,交叉阵列存储结构121包括选通管阵列和存储单元阵列。选通管阵列中的选通管与存储单元阵列中的存储单元一一对应串联连接。应理解,图2中的BL和WL可以用于标识存储单元和选通管在交叉阵列中所处的位置。其中,BL0、BL1为存储单元和选通管在交叉阵列中所处的位线,WL0、WL1为存储单元和选通管在交叉阵列中所处的字线,例
如,图2中的选通管10和存储单元20的位置可以表示为(BL0,WL1)。可选地,本申请所涉及的存储单元可以是相变存储单元、阻变存储单元、磁存储单元或铁电存储单元等,本申请对此不做限定。应理解,交叉阵列中的选通管主要用于对存储单元进行选通,具体地,利用电学信号控制选通管的开关,当施加电学信号于选通管时,选通管材料由高阻态向低阻态转变,选通管处于开启状态;当撤去电学信号时,选通管材料又由低阻态转变成高阻态,选通管处于关闭状态。然而,目前所研发的选通管的泄露电流通常处于纳安(nA)级别,无法满足商用要求,有待进一步降低。With the vigorous development of the big data, cloud computing and Internet of Things industries, along with the explosive growth of massive information and expanding market demand, higher requirements have been placed on the storage density and capacity of memories. Various new high-performance storage Technologies also emerged, such as cross-array storage technology. The following takes the cross-array memory structure 121 shown in FIG. 2 as an example to introduce the structure of the memory chip 120 . FIG. 2 is an example diagram of a cross array storage structure provided by an embodiment of the present application. As shown in Figure 2, the cross array memory structure 121 includes a gate array and a memory cell array. The strobe tubes in the strobe tube array and the memory cells in the memory cell array are connected in series in a one-to-one correspondence. It should be understood that BL and WL in Figure 2 can be used to identify the locations of memory cells and gate tubes in the crossbar array. Among them, BL0 and BL1 are the bit lines where the memory cells and strobe tubes are located in the cross array, and WL0 and WL1 are the word lines where the memory cells and strobe tubes are located in the cross array. For example For example, the positions of the gate tube 10 and the memory unit 20 in FIG. 2 can be expressed as (BL0, WL1). Optionally, the memory unit involved in this application may be a phase change memory unit, a resistive switching memory unit, a magnetic memory unit or a ferroelectric memory unit, etc. This application does not limit this. It should be understood that the gate tube in the cross array is mainly used to gate the memory cells. Specifically, electrical signals are used to control the switching of the gate tube. When an electrical signal is applied to the gate tube, the gate tube material is formed by high resistance. When the electrical signal is removed, the gate material changes from a low-resistance state to a high-resistance state, and the gate tube is in a closed state. However, the leakage current of gate tubes currently developed is usually at the nanoampere (nA) level, which cannot meet commercial requirements and needs to be further reduced.
基于此,本申请实施例通过设计选通管中的选通管材料层与其他材料层形成势垒,使得电子可以局域在势垒处,以降低选通管的泄露电流。Based on this, embodiments of the present application form a potential barrier by designing the gate material layer and other material layers in the gate tube, so that electrons can be localized at the potential barrier to reduce the leakage current of the gate tube.
图3是本申请实施例提供的一种选通管的示例图。应理解,图3所示的选通管300可以应用于图1所示的存储器100中,也可以应用于图2所示的交叉阵列存储结构121中。如图3所示,选通管300包括第一材料层310、选通管材料层320和第二材料层330。Figure 3 is an example diagram of a gate tube provided by an embodiment of the present application. It should be understood that the gate tube 300 shown in FIG. 3 can be applied to the memory 100 shown in FIG. 1 or the cross array memory structure 121 shown in FIG. 2 . As shown in FIG. 3 , the gate tube 300 includes a first material layer 310 , a gate tube material layer 320 and a second material layer 330 .
其中,第一材料层310的第一表面311与选通管材料层320的第一表面321接触,第二材料层330的第一表面331与选通管材料层320的第二表面322接触。应理解,选通管材料层320的第一表面321和选通管材料层320的第二表面322为选通管材料层320的两个相对的表面。The first surface 311 of the first material layer 310 is in contact with the first surface 321 of the gate material layer 320 , and the first surface 331 of the second material layer 330 is in contact with the second surface 322 of the gate material layer 320 . It should be understood that the first surface 321 of the gate material layer 320 and the second surface 322 of the gate material layer 320 are two opposite surfaces of the gate material layer 320 .
其中,第一材料层310与选通管材料层320形成势垒;和/或,第二材料层330与选通管材料层320形成势垒,使得电子可以局域在势垒处,从而能够降低选通管的泄露电流。Wherein, the first material layer 310 and the gate material layer 320 form a potential barrier; and/or the second material layer 330 and the gate material layer 320 form a potential barrier, so that electrons can be localized at the potential barrier, thereby enabling Reduce the leakage current of the gate tube.
上述第一材料层310与选通管材料层320形成势垒,也可以描述为第一材料层310与选通管材料层320之间形成界面势垒;同样地,上述第二材料层330与选通管材料层320形成势垒,也可以描述为第二材料层330与选通管材料层320之间形成界面势垒。The above-mentioned first material layer 310 and the gate tube material layer 320 form a potential barrier, which can also be described as forming an interface barrier between the first material layer 310 and the gate tube material layer 320; similarly, the above-mentioned second material layer 330 and the gate tube material layer 320 form an interface barrier. The gate material layer 320 forms a potential barrier, which can also be described as an interface barrier formed between the second material layer 330 and the gate material layer 320 .
可选地,实际操作中,可以从功函数角度出发,设计选通管材料层320与其他材料层具有功函数差异,使得在选通管材料层320与其他材料层形成势垒,从而使得电子可以局域在势垒处,以降低选通管的泄露电流。Optionally, in actual operation, from the perspective of work function, the gate material layer 320 and other material layers can be designed to have work function differences, so that a potential barrier is formed between the gate material layer 320 and other material layers, so that the electrons It can be localized at the potential barrier to reduce the leakage current of the gate tube.
具体地,可以设计第一材料层310的功函数大于选通管材料层320的功函数,且第一材料层310与选通管材料层320的第一功函数之差大于或等于0.3eV,就可以使得第一材料层310与选通管材料层320形成势垒;和/或,可以设计第二材料层330的功函数大于选通管材料层320的功函数,且第二材料层330与选通管材料层320的第二功函数之差大于或等于0.3eV,就可以使得第二材料层330与选通管材料层320形成势垒,使得电子可以局域在势垒处,从而能够降低选通管的泄露电流。Specifically, it can be designed that the work function of the first material layer 310 is greater than the work function of the gate material layer 320, and the difference between the first work functions of the first material layer 310 and the gate material layer 320 is greater than or equal to 0.3 eV, This allows the first material layer 310 and the gate material layer 320 to form a potential barrier; and/or the work function of the second material layer 330 can be designed to be greater than the work function of the gate material layer 320, and the second material layer 330 If the difference between the second work function and the gate material layer 320 is greater than or equal to 0.3 eV, the second material layer 330 and the gate material layer 320 can form a potential barrier, so that electrons can be localized at the potential barrier, thereby It can reduce the leakage current of the gate tube.
应理解,第一功函数之差为第一材料层310的功函数与选通管材料层320的功函数的差值;第二功函数之差为第二材料层330的功函数与选通管材料层320的功函数的差值。It should be understood that the difference of the first work function is the difference between the work function of the first material layer 310 and the work function of the gate material layer 320; the difference of the second work function is the difference between the work function of the second material layer 330 and the gate material layer 320. The difference in work function of the tube material layer 320.
应理解,在选通管300中,可以是第一功函数之差大于或等于0.3eV,也可以是第二功函数之差大于或等于0.3eV,还可以是第一功函数之差和第二功函数之差同时大于或等于0.3eV。It should be understood that in the gate 300, the difference between the first work function can be greater than or equal to 0.3eV, the difference between the second work function can be greater than or equal to 0.3eV, or the difference between the first work function and the second work function can be greater than or equal to 0.3eV. The difference between the two work functions is greater than or equal to 0.3eV at the same time.
应理解,本申请实施例中的功函数之差也可以描述为费米能级或禁带宽度差异。It should be understood that the difference in work functions in the embodiments of the present application can also be described as a difference in Fermi level or bandgap width.
可选地,第一功函数之差和第二功函数之差可以相同,也可以不同,本申请对此不做限定。Optionally, the difference between the first work function and the second work function may be the same or different, and this application does not limit this.
示例性地,第一功函数之差为0.3eV,第二功函数之差为0eV;或者,第一功函数之差为0.2eV,第二功函数之差为0.5eV;或者,第一功函数之差为0.4eV,第二功函数之差为0.3eV;或者,第一功函数之差和第二功函数之差均为0.3eV;或者,第一功函数之差和第二
功函数之差均为0.6eV。For example, the difference between the first work function is 0.3eV, and the difference between the second work function is 0eV; or, the difference between the first work function is 0.2eV, and the difference between the second work function is 0.5eV; or, the difference between the first work function and the second work function is 0.5eV. The difference between the functions is 0.4eV, and the difference between the second work function is 0.3eV; or, the difference between the first work function and the second work function is both 0.3eV; or, the difference between the first work function and the second work function is 0.3eV. The differences in work functions are all 0.6eV.
可选地,第一功函数之差可以大于或等于0.5eV,且小于或等于0.65eV。示例性地,第一功函数之差可以为0.5、0.55、0.6或0.65。可选地,第二功函数之差也可以满足如下范围:0.5-0.65eV。示例性地,第二功函数之差也可以为0.5、0.55、0.6或0.65。应理解,第一功函数之差和第二功函数之差的取值可以均满足范围0.5-0.65eV,也可以是其中一个满足上述范围;第一功函数之差和第二功函数之差的取值可以相同也可以不同。Optionally, the difference in the first work function may be greater than or equal to 0.5eV and less than or equal to 0.65eV. By way of example, the difference in the first work functions may be 0.5, 0.55, 0.6 or 0.65. Optionally, the difference in the second work function can also satisfy the following range: 0.5-0.65eV. For example, the difference between the second work functions may also be 0.5, 0.55, 0.6 or 0.65. It should be understood that the values of the difference between the first work function and the second work function can both meet the range of 0.5-0.65eV, or one of them can meet the above range; the difference between the first work function and the second work function The values of can be the same or different.
可选地,第一功函数之差可以是通过调节该选通管材料层或者第一材料层的化学计量比、掺杂、厚度等中的任意一种或多种实现的;第二功函数之差可以是通过调节该选通管材料层或者第二材料层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。Optionally, the difference in the first work function can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the first material layer; the second work function The difference can be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer or the second material layer.
在实际操作中,还可以利用不同材料层之间形成的界面势垒来调控选通管阈值电压的大小。In actual operation, the interface barrier formed between different material layers can also be used to regulate the threshold voltage of the gate tube.
可选地,第一材料层310可以包括第一多级热导率,该第一多级热导率从第一材料层310的第二表面312至第一材料层310的第一表面311逐级递减;和/或,第二材料层330可以包括第二多级热导率,该第二多级热导率从第二材料层330的第二表面332至第二材料层330的第一表面331逐级递减。Optionally, the first material layer 310 may include a first multi-level thermal conductivity, the first multi-level thermal conductivity is gradually from the second surface 312 of the first material layer 310 to the first surface 311 of the first material layer 310 . and/or the second material layer 330 may include a second multi-level thermal conductivity from the second surface 332 of the second material layer 330 to a first Surface 331 decreases step by step.
在本申请实施例中,第一材料层310可以包括第一多级热导率,该第一多级热导率从第一材料层310的第二表面312至第一材料层310的第一表面311逐级递减;和/或,第二材料层330可以包括第二多级热导率,该第二多级热导率从第二材料层330的第二表面332至第二材料层330的第一表面331逐级递减,从而可以阻碍外界至选通管材料层320的热传递,提高选通管的热稳定性。In the embodiment of the present application, the first material layer 310 may include a first multi-level thermal conductivity from the second surface 312 of the first material layer 310 to a first surface of the first material layer 310 . The surface 311 gradually decreases; and/or the second material layer 330 may include a second multi-level thermal conductivity from the second surface 332 of the second material layer 330 to the second material layer 330 The first surface 331 gradually decreases, thereby blocking the heat transfer from the outside to the gate tube material layer 320 and improving the thermal stability of the gate tube.
对于第一材料层310而言:在一种实现方式中,第一材料层310可以包括第一缓冲层和第一电极层,其中,第一缓冲层的第一表面作为第一材料层310的第一表面311,第一电极层的第一表面与第一缓冲层的第二表面接触,第一多级热导率包括第一缓冲层的热导率和第一电极层的热导率。应理解,第一缓冲层的第一表面和第一缓冲层的第二表面为第一缓冲层的两个相对的表面。应理解,第一多级热导率包括第一缓冲层的热导率和第一电极层的热导率意味着第一缓冲层的热导率小于第一电极层的热导率。For the first material layer 310: In one implementation, the first material layer 310 may include a first buffer layer and a first electrode layer, wherein the first surface of the first buffer layer serves as the first surface of the first material layer 310. The first surface 311, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer. It should be understood that the first surface of the first buffer layer and the second surface of the first buffer layer are two opposite surfaces of the first buffer layer. It should be understood that the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, which means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.
在本申请实施例中,第一材料层310可以包括第一缓冲层和第一电极层,且第一多级热导率包括第一缓冲层的热导率和第一电极层的热导率,一方面,第一缓冲层的引入为选通管引入了更多的界面,使得第一缓冲层与选通管材料层320之间可以产生界面效应(即声子散射),从而能够降低第一缓冲层与选通管材料层320之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性;另一方面,第一多级热导率包括该第一缓冲层的热导率和该第一电极层的热导率,意味着第一缓冲层的热导率小于第一电极层的热导率,也可以阻碍外界至选通管材料层320的热传递,提高选通管的热稳定性。In this embodiment of the present application, the first material layer 310 may include a first buffer layer and a first electrode layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer. , on the one hand, the introduction of the first buffer layer introduces more interfaces to the gate tube, so that the interface effect (ie, phonon scattering) can be generated between the first buffer layer and the gate tube material layer 320, thereby reducing the third The thermal conductivity between a buffer layer and the gate tube material layer 320 can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the first multi-level thermal conductivity The thermal conductivity includes the thermal conductivity of the first buffer layer and the thermal conductivity of the first electrode layer, which means that the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer, and can also prevent the outside world from reaching the gate tube. The heat transfer of the material layer 320 improves the thermal stability of the gate tube.
这种情况下,第一功函数之差可以是通过调节选通管材料层320或者第一缓冲层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。可选地,也可以同时调节选通管材料层320和第一缓冲层的化学计量比、掺杂、厚度等中的任意一种或多种实现第一功函数之差。In this case, the difference in the first work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the first buffer layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the first buffer layer can also be adjusted simultaneously to achieve the difference in the first work function.
应理解,调节化学计量比是指调节材料层中各个元素的原子百分比,例如,可以将选通管材料层320的选通管材料Ge50S50调节为Ge30S70。应理解,在进行化学计量比或掺杂的调控时,可以调控整个通管材料层320和/或整个第一缓冲层的化学计量比或掺杂,也可以仅调控通管材料层320与第一缓冲层的接触表层的化学计量比或掺杂,不做限定。It should be understood that adjusting the stoichiometric ratio means adjusting the atomic percentage of each element in the material layer. For example, the gate material Ge 50 S 50 of the gate material layer 320 can be adjusted to Ge 30 S 70 . It should be understood that when adjusting the stoichiometric ratio or doping, the stoichiometric ratio or doping of the entire via material layer 320 and/or the entire first buffer layer can be adjusted, or only the via material layer 320 and the first buffer layer can be adjusted. The stoichiometry or doping of the contact surface of a buffer layer is not limited.
可选地,第一缓冲层可以包括非晶碳、SiC、CS、TeC、TeCS、MoTe2、MoS2、MnTe、
HfO2/TaO、WTe2、WS2等中的任意一种或多种。Alternatively, the first buffer layer may include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe, Any one or more of H f O 2 /TaO, WTe 2 , WS 2 , etc.
可选地,第一缓冲层的厚度可以为5-20nm。Optionally, the thickness of the first buffer layer may be 5-20 nm.
可选地,第一电极层可以包括Pt、Ti、W、Au、Ru、Al、TiW、TiN、TaN、IrO2、ITO以及IZO等中的任意一种或多种。Alternatively, the first electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
可选地,第一电极层的厚度可以为35-100nm。Optionally, the thickness of the first electrode layer may be 35-100 nm.
在另一种实现方式中,第一材料层310可以包括第三电极层,其中,第三电极层的第一表面作为第一材料层310的第一表面311,第一多级热导率为该第三电极层的多级热导率。应理解,第一多级热导率为该第三电极层的多级热导率意味着热导率从第三电极层的第二表面至该第三电极层的第一表面逐级递减。In another implementation, the first material layer 310 may include a third electrode layer, wherein the first surface of the third electrode layer serves as the first surface 311 of the first material layer 310, and the first multi-level thermal conductivity is Multi-level thermal conductivity of the third electrode layer. It should be understood that the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity gradually decreases from the second surface of the third electrode layer to the first surface of the third electrode layer.
在本申请实施例中,第一材料层310可以包括第三电极层,该第一多级热导率为该第三电极层的多级热导率,意味着热导率从第三电极层的第二表面至第三电极层的第一表面逐级递减,从而可以阻碍外界至选通管材料层320的热传递,提高选通管的热稳定性。In this embodiment of the present application, the first material layer 310 may include a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer, which means that the thermal conductivity is from the third electrode layer. The second surface to the first surface of the third electrode layer gradually decreases, thereby blocking heat transfer from the outside to the gate material layer 320 and improving the thermal stability of the gate tube.
这种情况下,第一功函数之差可以是通过调节选通管材料层320或者第三电极层的化学计量比、掺杂、厚度中的任意一种或多种实现的。可选地,也可以同时调节选通管材料层320和第三电极层的化学计量比、掺杂、厚度等中的任意一种或多种实现第一功函数之差。In this case, the difference in the first work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, and thickness of the gate material layer 320 or the third electrode layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the third electrode layer can also be adjusted simultaneously to achieve the difference in the first work function.
应理解,在进行化学计量比或掺杂的调控时,可以调控整个通管材料层320和/或整个第三电极层的化学计量比或掺杂,也可以仅调控通管材料层320和/或第三电极层的接触表层的化学计量比或掺杂,不做限定。It should be understood that when adjusting the stoichiometric ratio or doping, the stoichiometric ratio or doping of the entire via tube material layer 320 and/or the entire third electrode layer can be adjusted, or only the via tube material layer 320 and/or the via tube material layer 320 and/or the entire third electrode layer can be adjusted. Or the stoichiometric ratio or doping of the contact surface layer of the third electrode layer is not limited.
可选地,第三电极层的第一表面至第三电极层的第二表面的功函数呈梯度递减。应理解,第三电极层的第一表面和第三电极层的第二表面为第三电极层的两个相对的表面。应理解,第三电极层的功函数也可以呈现出其他分布,不做限定。Optionally, the work function from the first surface of the third electrode layer to the second surface of the third electrode layer decreases in a gradient. It should be understood that the first surface of the third electrode layer and the second surface of the third electrode layer are two opposite surfaces of the third electrode layer. It should be understood that the work function of the third electrode layer may also exhibit other distributions without limitation.
可选地,第三电极层可以包括Pt、Ti、W、Au、Ru、Al、TiW、TiN、TaN、IrO2、ITO以及IZO等中的任意一种或多种。Optionally, the third electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
可选地,第三电极层的厚度可以为35-100nm。Optionally, the thickness of the third electrode layer may be 35-100 nm.
对于第二材料层330而言:在一种实现方式中,第二材料层330可以包括第二缓冲层和第二电极层,第二缓冲层的第一表面作为第二材料层330的第一表面331,第二电极层的第一表面与第二缓冲层的第二表面接触,第二多级热导率包括第二缓冲层的热导率和第二电极层的热导率。应理解,第二缓冲层的第一表面和第二缓冲层的第二表面为第二缓冲层的两个相对的表面。应理解,第二多级热导率包括第二缓冲层的热导率和第二电极层的热导率意味着第二缓冲层的热导率小于第二电极层的热导率。For the second material layer 330: In one implementation, the second material layer 330 may include a second buffer layer and a second electrode layer, and the first surface of the second buffer layer serves as the first surface of the second material layer 330. Surface 331, the first surface of the second electrode layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer. It should be understood that the first surface of the second buffer layer and the second surface of the second buffer layer are two opposite surfaces of the second buffer layer. It should be understood that the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, which means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.
在本申请实施例中,若第二材料层330包括第二缓冲层和第二电极层,且第二多级热导率包括第二缓冲层的热导率和第二电极层的热导率,一方面,第二缓冲层的引入为选通管引入了更多的界面,使得第二缓冲层与选通管材料层320之间可以产生界面效应(即声子散射),从而能够降低第二缓冲层与选通管材料层320之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性;另一方面,第二多级热导率包括该第二缓冲层的热导率和该第二电极层的热导率,意味着第二缓冲层的热导率小于第二电极层的热导率,也可以阻碍外界至选通管材料层320的热传递,提高选通管的热稳定性。In this embodiment of the present application, if the second material layer 330 includes a second buffer layer and a second electrode layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer , on the one hand, the introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (ie, phonon scattering) can be generated between the second buffer layer and the gate tube material layer 320, thereby reducing the third The thermal conductivity between the second buffer layer and the gate tube material layer 320 can hinder the heat transfer from the outside to the gate tube material layer and improve the thermal stability of the gate tube; on the other hand, the second multi-level thermal conductivity The thermal conductivity includes the thermal conductivity of the second buffer layer and the thermal conductivity of the second electrode layer, which means that the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer, and can also prevent the outside world from reaching the gate tube. The heat transfer of the material layer 320 improves the thermal stability of the gate tube.
这种情况下,第二功函数之差可以是通过调节选通管材料层320或者第二缓冲层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。可选地,也可以同时调节选通管材料层320和第二缓冲层的化学计量比、掺杂、厚度等中的任意一种或多种实现第二功函数之差。In this case, the difference in the second work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the second buffer layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the second buffer layer can also be adjusted simultaneously to achieve the difference in the second work function.
应理解,在进行化学计量比或掺杂的调控时,可以调控整个通管材料层320和/或整个第
二缓冲层的化学计量比或掺杂,也可以仅调控通管材料层320和/或第二缓冲层的接触表层的化学计量比或掺杂,不做限定。It should be understood that when adjusting the stoichiometric ratio or doping, the entire via material layer 320 and/or the entire third The stoichiometric ratio or doping of the two buffer layers can also only be adjusted to the stoichiometric ratio or doping of the via material layer 320 and/or the contact surface layer of the second buffer layer, without limitation.
可选地,第二缓冲层可以包括非晶碳、SiC、CS、TeC、TeCS、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2等中的任意一种或多种。Optionally, the second buffer layer may include any one or more of amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe, H f O 2 /TaO, WTe 2 , WS 2, etc. kind.
可选地,第二缓冲层的厚度可以为5-20nm。Optionally, the thickness of the second buffer layer may be 5-20 nm.
可选地,第二电极层可以包括Pt、Ti、W、Au、Ru、Al、TiW、TiN、TaN、IrO2、ITO以及IZO等中的任意一种或多种。Optionally, the second electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
可选地,第二电极层的厚度可以为35-100nm。Optionally, the thickness of the second electrode layer may be 35-100 nm.
在另一种实现方式中,第二材料层330可以包括第四电极层,第四电极层的第一表面作为第二材料层330的第一表面331,第二多级热导率为第四电极层的多级热导率。应理解,第二多级热导率为该第四电极层的多级热导率意味着热导率从第四电极层的第二表面至该第四电极层的第一表面逐级递减。In another implementation, the second material layer 330 may include a fourth electrode layer, the first surface of the fourth electrode layer serves as the first surface 331 of the second material layer 330, and the second multi-level thermal conductivity is the fourth Multilevel thermal conductivity of electrode layers. It should be understood that the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity gradually decreases from the second surface of the fourth electrode layer to the first surface of the fourth electrode layer.
在本申请实施例中,第二材料层330可以包括第四电极层,该第二多级热导率为该第四电极层的多级热导率,意味着热导率从第四电极层的第二表面至第四电极层的第一表面逐级递减,从而可以阻碍外界至选通管材料层320的热传递,提高选通管的热稳定性。In this embodiment of the present application, the second material layer 330 may include a fourth electrode layer, and the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer, which means that the thermal conductivity is from the fourth electrode layer. The second surface to the first surface of the fourth electrode layer gradually decreases, thereby blocking the heat transfer from the outside to the gate material layer 320 and improving the thermal stability of the gate tube.
这种情况下,第二功函数之差可以是通过调节选通管材料层320或者第四电极层的化学计量比、掺杂、厚度等中的任意一种或多种实现的。可选地,也可以同时调节选通管材料层320和第四电极层的化学计量比、掺杂、厚度等中的任意一种或多种实现第二功函数之差。In this case, the difference in the second work function may be achieved by adjusting any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 or the fourth electrode layer. Optionally, any one or more of the stoichiometric ratio, doping, thickness, etc. of the gate material layer 320 and the fourth electrode layer can also be adjusted simultaneously to realize the difference in the second work function.
应理解,在进行化学计量比或掺杂的调控时,可以调控整个通管材料层320和/或整个第四电极层的化学计量比或掺杂,也可以仅调控通管材料层320和/或第四电极层的接触表层的化学计量比或掺杂,不做限定。It should be understood that when adjusting the stoichiometric ratio or doping, the stoichiometric ratio or doping of the entire via tube material layer 320 and/or the entire fourth electrode layer can be adjusted, or only the via tube material layer 320 and/or the via tube material layer 320 and/or the entire fourth electrode layer can be adjusted. Or the stoichiometric ratio or doping of the contact surface layer of the fourth electrode layer is not limited.
可选地,第四电极层的第一表面至第四电极层的第二表面的功函数可以呈梯度递减。应理解,第四电极层的第一表面和第四电极层的第二表面为第四电极层的两个相对的表面。应理解,第四电极层的功函数也可以呈现出其他分布,不做限定。Optionally, the work function from the first surface of the fourth electrode layer to the second surface of the fourth electrode layer may decrease in a gradient. It should be understood that the first surface of the fourth electrode layer and the second surface of the fourth electrode layer are two opposite surfaces of the fourth electrode layer. It should be understood that the work function of the fourth electrode layer may also exhibit other distributions without limitation.
可选地,第四电极层可以包括Pt、Ti、W、Au、Ru、Al、TiW、TiN、TaN、IrO2、ITO以及IZO等中的任意一种或多种。Optionally, the fourth electrode layer may include any one or more of Pt, Ti, W, Au, Ru, Al, TiW, TiN, TaN, IrO 2 , ITO, IZO, and the like.
可选地,第四电极层的厚度可以为35-100nm。Optionally, the thickness of the fourth electrode layer may be 35-100 nm.
应理解,本申请实施例不限定第一材料层和第二材料层的具体组合方式。示例性地,第一材料层310包括第一缓冲层和第一电极层,第二材料层330包括第二缓冲层和第二电极层,参见图4;或者,第一材料层310包括第三电极层,第二材料层330包括第四电极层参见图5;或者,第一材料层310包括第一缓冲层和第一电极层,第二材料层330包括第四电极层;或者,第一材料层310包括第三电极层,第二材料层330包括第二缓冲层和第二电极层。为便于描述,下面以前两个示例为例进行描述,但应理解,实际应用中可以不限于此。It should be understood that the embodiments of the present application do not limit the specific combination of the first material layer and the second material layer. Exemplarily, the first material layer 310 includes a first buffer layer and a first electrode layer, and the second material layer 330 includes a second buffer layer and a second electrode layer, see FIG. 4 ; or, the first material layer 310 includes a third Electrode layer, the second material layer 330 includes a fourth electrode layer, see FIG. 5; or, the first material layer 310 includes a first buffer layer and a first electrode layer, and the second material layer 330 includes a fourth electrode layer; or, the first The material layer 310 includes a third electrode layer, and the second material layer 330 includes a second buffer layer and a second electrode layer. For ease of description, the first two examples are used as examples for description below, but it should be understood that actual applications may not be limited to these.
对于选通管材料层320而言:可选地,选通管材料层320可以包括Te、Se或S基等的二元或者多元双向阈值开关(ovonic threshold switching,OTS)材料。Regarding the gate material layer 320: Optionally, the gate material layer 320 may include a Te, Se or S-based binary or multi-element bidirectional threshold switching (ovonic threshold switching, OTS) material.
可选地,选通管材料层320的厚度可以为10-30nm。Optionally, the thickness of the gate material layer 320 may be 10-30 nm.
可选地,OTS材料可以包括GeTe、CTe、BTe、SiTe、AlTe、ZnTe、CdTe、NTe、MgTe、CaTe、GaTe、GeS、GeSe等中的任意一种或多种。Alternatively, the OTS material may include any one or more of GeTe, CTe, BTe, SiTe, AlTe, ZnTe, CdTe, NTe, MgTe, CaTe, GaTe, GeS, GeSe, etc.
可选地,选通管材料层320还可以包括掺杂元素B、C、N、Ge、Si、Al、Zn、Ga、S、Se、As等等中的一种或多种。Optionally, the gate material layer 320 may also include one or more of doping elements B, C, N, Ge, Si, Al, Zn, Ga, S, Se, As, and the like.
下面以图4和图5为例对选通管300的结构进行示例性介绍。
The following takes FIG. 4 and FIG. 5 as examples to introduce the structure of the gate tube 300 .
图4是本申请实施例提供的另一种选通管的示例图。如图4所示,选通管400包括,底电极层410(即上述第一电极层)、第一缓冲层420(即上述第一缓冲层)、选通管材料层430(即上述选通管材料层320)、第二缓冲层440(即上述第二缓冲层)、顶电极层450(即上述第二电极层)。Figure 4 is an example diagram of another gate tube provided by the embodiment of the present application. As shown in Figure 4, the gate tube 400 includes a bottom electrode layer 410 (i.e., the above-mentioned first electrode layer), a first buffer layer 420 (i.e., the above-mentioned first buffer layer), and a gate tube material layer 430 (i.e., the above-mentioned gate tube material layer 320), a second buffer layer 440 (ie, the above-mentioned second buffer layer), and a top electrode layer 450 (ie, the above-mentioned second electrode layer).
其中,底电极层410的第一表面411与第一缓冲层420的第二表面422接触,第一缓冲层420的第一表面421与选通管材料层430的第一表面431接触,选通管材料层430的第二表面432与第二缓冲层440的第一表面441接触,顶电极层450的第一表面451与第二缓冲层440的第二表面442接触。The first surface 411 of the bottom electrode layer 410 is in contact with the second surface 422 of the first buffer layer 420, and the first surface 421 of the first buffer layer 420 is in contact with the first surface 431 of the gate material layer 430. The second surface 432 of the tube material layer 430 is in contact with the first surface 441 of the second buffer layer 440 , and the first surface 451 of the top electrode layer 450 is in contact with the second surface 442 of the second buffer layer 440 .
可选地,第一缓冲层420与选通管材料层430形成势垒;或者,第二缓冲层440与选通管材料层430形成势垒;或者,第一缓冲层420与选通管材料层430以及第二缓冲层440与选通管材料层430均形成势垒。Optionally, the first buffer layer 420 and the gate material layer 430 form a potential barrier; or the second buffer layer 440 and the gate material layer 430 form a potential barrier; or the first buffer layer 420 and the gate material layer The layer 430 and the second buffer layer 440 and the gate material layer 430 all form a potential barrier.
可选地,第一缓冲层420与选通管材料层430的功函数之差大于或等于0.3eV;或者,第二缓冲层440与选通管材料层430的功函数之差大于或等于0.3eV;或者,第一缓冲层420与选通管材料层430的功函数之差以及第二缓冲层440与选通管材料层430的功函数之差均大于或等于0.3eV。Optionally, the difference in work functions between the first buffer layer 420 and the gate material layer 430 is greater than or equal to 0.3 eV; or, the difference in work functions between the second buffer layer 440 and the gate material layer 430 is greater than or equal to 0.3 eV; alternatively, the difference between the work functions of the first buffer layer 420 and the gate material layer 430 and the difference between the work functions of the second buffer layer 440 and the gate material layer 430 are both greater than or equal to 0.3 eV.
可选地,第一缓冲层420的热导率小于底电极层410的热导率;或者,第二缓冲层440的热导率小于顶电极层450的热导率;或者,第一缓冲层420的热导率小于底电极层410的热导率以及第二缓冲层440的热导率小于顶电极层450的热导率。Optionally, the thermal conductivity of the first buffer layer 420 is less than the thermal conductivity of the bottom electrode layer 410; or, the thermal conductivity of the second buffer layer 440 is less than the thermal conductivity of the top electrode layer 450; or, the first buffer layer The thermal conductivity of 420 is less than that of the bottom electrode layer 410 and the thermal conductivity of the second buffer layer 440 is less than that of the top electrode layer 450 .
关于底电极层410、第一缓冲层420、选通管材料层430、第二缓冲层440、顶电极层450的材料以及厚度限定可参见上文选通管300中关于第一电极层、第一缓冲层、选通管材料层320、第二缓冲层、第二电极层的相关描述,不再赘述。Regarding the materials and thickness definitions of the bottom electrode layer 410, the first buffer layer 420, the gate material layer 430, the second buffer layer 440, and the top electrode layer 450, please refer to the above section about the first electrode layer and the first gate tube 300. The relevant descriptions of the buffer layer, the gate material layer 320, the second buffer layer, and the second electrode layer will not be described again.
图5是本申请实施例提供的又一种选通管的示例图。如图5所示,选通管500包括,底电极层510(即上述第三电极层)、选通管材料层520(即上述选通管材料层320)、顶电极层530(即上述第四电极层)。Figure 5 is an example diagram of yet another gate tube provided by the embodiment of the present application. As shown in Figure 5, the gate tube 500 includes a bottom electrode layer 510 (i.e., the above-mentioned third electrode layer), a gate tube material layer 520 (i.e., the above-mentioned gate tube material layer 320), and a top electrode layer 530 (i.e., the above-mentioned third electrode layer). four electrode layers).
其中,底电极层510的第一表面511与选通管材料层520的第一表面521接触,顶电极层530的第一表面531与选通管材料层520的第二表面522接触。The first surface 511 of the bottom electrode layer 510 is in contact with the first surface 521 of the gate material layer 520 , and the first surface 531 of the top electrode layer 530 is in contact with the second surface 522 of the gate material layer 520 .
可选地,底电极层510与选通管材料层520形成势垒;或者,顶电极层530与选通管材料层520形成势垒;或者,底电极层510与选通管材料层520以及顶电极层530与选通管材料层520均形成势垒。Optionally, the bottom electrode layer 510 and the gate material layer 520 form a potential barrier; or the top electrode layer 530 and the gate material layer 520 form a potential barrier; or the bottom electrode layer 510 and the gate material layer 520 and The top electrode layer 530 and the gate material layer 520 both form a potential barrier.
可选地,底电极层510与选通管材料层520的功函数之差大于或等于0.3eV;或者,顶电极层530与选通管材料层520的功函数之差大于或等于0.3eV;或者,底电极层510的与选通管材料层520的功函数之差以及顶电极层530与选通管材料层520的功函数之差均大于或等于0.3eV。Optionally, the difference in the work functions of the bottom electrode layer 510 and the gate material layer 520 is greater than or equal to 0.3eV; or, the difference in the work functions of the top electrode layer 530 and the gate material layer 520 is greater than or equal to 0.3eV; Alternatively, the difference between the work functions of the bottom electrode layer 510 and the gate material layer 520 and the difference between the work functions of the top electrode layer 530 and the gate material layer 520 are both greater than or equal to 0.3 eV.
可选地,底电极层510包括多级热导率,该多级热导率从底电极层510的第二表面512至底电极层510的第一表面511逐级递减;或者,顶电极层530包括多级热导率,该多级热导率从顶电极层530的第二表面532至顶电极层530的第一表面531逐级递减;或者,底电极层510包括多级热导率,该多级热导率从底电极层510的第二表面512至底电极层510的第一表面511逐级递减以及顶电极层530包括多级热导率,该多级热导率从顶电极层530的第二表面532至顶电极层530的第一表面531逐级递减。Optionally, the bottom electrode layer 510 includes a multi-level thermal conductivity that gradually decreases from the second surface 512 of the bottom electrode layer 510 to the first surface 511 of the bottom electrode layer 510; or, the top electrode layer 530 includes multiple levels of thermal conductivity that gradually decrease from the second surface 532 of the top electrode layer 530 to the first surface 531 of the top electrode layer 530; alternatively, the bottom electrode layer 510 includes multiple levels of thermal conductivity. , the multi-level thermal conductivity gradually decreases from the second surface 512 of the bottom electrode layer 510 to the first surface 511 of the bottom electrode layer 510 and the top electrode layer 530 includes multi-level thermal conductivity, the multi-level thermal conductivity starts from the top The second surface 532 of the electrode layer 530 to the first surface 531 of the top electrode layer 530 gradually decreases.
关于底电极层510、选通管材料层520、顶电极层530的材料以及厚度限定可参见上文选通管300中关于第三电极层、选通管材料层320、第四电极层的相关描述,不再赘述。
Regarding the materials and thickness limits of the bottom electrode layer 510 , the gate material layer 520 , and the top electrode layer 530 , please refer to the relevant descriptions of the third electrode layer, the gate material layer 320 , and the fourth electrode layer in the gate tube 300 above. ,No longer.
本发明实施例还提供了一种选通管的制备方法,图6是本申请实施例提供的一种选通管的制备方法的流程图。如图6所示,方法600包括步骤S610至S630,下面对这些步骤进行介绍。Embodiments of the present invention also provide a method for preparing a gate tube. FIG. 6 is a flow chart of a method for preparing a gate tube provided by embodiments of the present application. As shown in Figure 6, the method 600 includes steps S610 to S630, and these steps are introduced below.
S610,形成第一材料层。S610, form a first material layer.
可选地,第一材料层可以包括多级热导率(即上述第一多级热导率),该多级热导率从该第一材料层的第二表面至该第一材料层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。Optionally, the first material layer may include multi-level thermal conductivity (ie, the above-mentioned first multi-level thermal conductivity), the multi-level thermal conductivity from the second surface of the first material layer to the first material layer The first surface gradually decreases, thereby blocking heat transfer from the outside to the material layer of the gate tube and improving the thermal stability of the gate tube.
在一种实现方式中,形成第一材料层可以包括:形成第一电极层;在第一电极层的第一表面上形成第一缓冲层,其中,第一缓冲层的第一表面作为第一材料层的第一表面,第一电极层的第一表面与该第一缓冲层的第二表面接触,第一缓冲层的热导率小于第一电极层的热导率。In one implementation, forming the first material layer may include: forming a first electrode layer; forming a first buffer layer on the first surface of the first electrode layer, wherein the first surface of the first buffer layer serves as the first The first surface of the material layer and the first surface of the first electrode layer are in contact with the second surface of the first buffer layer, and the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer.
在本申请实施例中,形成第一材料层可以包括形成第一缓冲层和第一电极层,且第一缓冲层的热导率小于第一电极层的热导率,一方面,第一缓冲层的引入为选通管引入了更多的界面,使得第一缓冲层与选通管材料层之间可以产生界面效应(即声子散射),从而能够降低第一缓冲层与选通管材料层之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性;另一方面,第一缓冲层的热导率小于第一电极层的热导率,也可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In this embodiment of the present application, forming the first material layer may include forming a first buffer layer and a first electrode layer, and the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer. On the one hand, the first buffer layer The introduction of the layer introduces more interfaces to the gate tube, so that the interface effect (that is, phonon scattering) can be generated between the first buffer layer and the gate tube material layer, thereby reducing the The thermal conductivity between the layers can hinder the heat transfer from the outside to the gate material layer and improve the thermal stability of the gate tube; on the other hand, the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the first electrode layer. The conductivity can also hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.
应理解,关于第一缓冲层和第一电极层的材料和厚度可参见上文相关描述,不再赘述。It should be understood that regarding the materials and thicknesses of the first buffer layer and the first electrode layer, reference may be made to the relevant descriptions above and will not be described again.
在另一种实现方式中,形成第一材料层可以包括:形成第三电极层,其中,该第三电极层的第一表面作为该第一材料层的第一表面,第三电极层包括多级热导率,该多级热导率从第三电极层的第二表面至第三电极层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In another implementation, forming the first material layer may include: forming a third electrode layer, wherein the first surface of the third electrode layer serves as the first surface of the first material layer, and the third electrode layer includes a plurality of The multi-level thermal conductivity gradually decreases from the second surface of the third electrode layer to the first surface of the third electrode layer, which can hinder the heat transfer from the outside to the gate tube material layer and improve the gate. Thermal stability of the tube.
应理解,关于第三电极层的材料和厚度可参见上文相关描述,不再赘述。It should be understood that regarding the material and thickness of the third electrode layer, please refer to the relevant description above and will not be described again.
S620,在第一材料层的第一表面上形成选通管材料层,第一材料层的第一表面与选通管材料层的第一表面接触。S620: Form a gate material layer on the first surface of the first material layer, and the first surface of the first material layer is in contact with the first surface of the gate material layer.
应理解,关于选通管材料层的材料和厚度可参见上文相关描述,不再赘述。It should be understood that regarding the material and thickness of the gate material layer, please refer to the relevant description above and will not be described again.
S630,在选通管材料层的第二表面上形成第二材料层,第二材料层的第一表面与该选通管材料层的第二表面接触。S630: Form a second material layer on the second surface of the gate material layer, and the first surface of the second material layer is in contact with the second surface of the gate material layer.
可选地,第二材料层可以包括多级热导率(及上述第二多级热导率),该多级热导率从该第二材料层的第二表面至该第二材料层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。Optionally, the second material layer may include a multi-level thermal conductivity (and the above-mentioned second multi-level thermal conductivity), the multi-level thermal conductivity from the second surface of the second material layer to the second surface of the second material layer. The first surface gradually decreases, thereby blocking heat transfer from the outside to the material layer of the gate tube and improving the thermal stability of the gate tube.
在一种实现方式中,在选通管材料层的第二表面上形成第二材料层可以包括:在选通管材料层的第二表面上形成第二缓冲层,该第二缓冲层的第一表面作为该第二材料层的第一表面;在该第二缓冲层的第二表面上形成第二电极层,该第二电极层的第一表面与该第二缓冲层的第二表面接触,该第二缓冲层的热导率小于该第二电极层的热导率。In one implementation, forming the second material layer on the second surface of the gate material layer may include: forming a second buffer layer on the second surface of the gate material layer, the second buffer layer having a A surface serves as the first surface of the second material layer; a second electrode layer is formed on the second surface of the second buffer layer, and the first surface of the second electrode layer is in contact with the second surface of the second buffer layer , the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer.
在本申请实施例中,形成第二材料层可以包括形成第二缓冲层和第二电极层,且第二缓冲层的热导率小于第二电极层的热导率,一方面,第二缓冲层的引入为选通管引入了更多的界面,使得第二缓冲层与选通管材料层之间可以产生界面效应(即声子散射),从而能够降低第二缓冲层与选通管材料层之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性;另一方面,第二缓冲层的热导率小于第二电极层的热导率,也可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。
In this embodiment of the present application, forming the second material layer may include forming a second buffer layer and a second electrode layer, and the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the second electrode layer. On the one hand, the second buffer layer The introduction of the second buffer layer introduces more interfaces to the gate tube, so that the interface effect (i.e., phonon scattering) can occur between the second buffer layer and the gate tube material layer, thereby reducing the The thermal conductivity between the layers can hinder the heat transfer from the outside to the gate material layer and improve the thermal stability of the gate tube; on the other hand, the thermal conductivity of the second buffer layer is smaller than that of the second electrode layer. The conductivity can also hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.
应理解,关于第二缓冲层和第二电极层的材料和厚度可参见上文相关描述,不再赘述。It should be understood that regarding the materials and thicknesses of the second buffer layer and the second electrode layer, reference may be made to the relevant descriptions above and will not be described again.
在另一种实现方式中,该在该选通管材料层的第二表面上形成第二材料层可以包括:在该选通管材料层的第二表面上形成第四电极层,该第四电极层的第一表面作为该第二材料层的第一表面,第四电极层可以包括多级热导率,该多级热导率从该第四电极层的第二表面至该第四电极层的第一表面逐级递减,从而可以阻碍外界至选通管材料层的热传递,提高选通管的热稳定性。In another implementation, forming the second material layer on the second surface of the gate material layer may include: forming a fourth electrode layer on the second surface of the gate material layer, the fourth The first surface of the electrode layer serves as the first surface of the second material layer, and the fourth electrode layer may include multi-level thermal conductivity from the second surface of the fourth electrode layer to the fourth electrode. The first surface of the layer decreases step by step, which can hinder the heat transfer from the outside to the material layer of the gate tube and improve the thermal stability of the gate tube.
还需要说明的是,上述第一材料层与选通管材料层形成势垒;和/或,第二材料层与选通管材料层形成势垒,使得电子可以局域在势垒处,从而能够降低选通管的泄露电流。It should also be noted that the above-mentioned first material layer and the gate material layer form a potential barrier; and/or the second material layer and the gate material layer form a potential barrier, so that electrons can be localized at the potential barrier, thereby It can reduce the leakage current of the gate tube.
可选地,上述第一材料层与选通管材料层的第一功函数之差大于或等于0.3eV;和/或,第二材料层与选通管材料层的第二功函数之差大于或等于0.3eV。应理解,具体关于功函数的描述可参见上文,不再赘述。Optionally, the difference in the first work function of the above-mentioned first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the difference in the second work function of the second material layer and the gate material layer is greater than or equal to 0.3eV. It should be understood that the specific description of the work function can be found above and will not be described again.
可选地,形成第一材料层、选通管材料层或第二材料层的方法可以包括蒸镀法、溅射法、原子层沉积法、化学气相沉积法、脉冲激光沉积法、分子束外延法等中的任意一种或多种。Optionally, the method of forming the first material layer, the gate material layer or the second material layer may include evaporation, sputtering, atomic layer deposition, chemical vapor deposition, pulsed laser deposition, and molecular beam epitaxy. any one or more of the following.
应理解,形成第一材料层、选通管材料层和第二材料层可以采用相同的方法也可以采用不同的方法,本申请对此不做限定。It should be understood that the same method or different methods can be used to form the first material layer, the gate material layer and the second material layer, which is not limited in this application.
可选地,参见图7,在步骤S610形成第一材料层之前,可以先在衬底710上依次制备电极层720和绝缘层730,然后通过光刻和刻蚀工艺在绝缘层730上形成特征尺寸为80-500nm的小孔,再执行步骤S610。在一种实现方式中,参见图7中的(a),在小孔内形成第一电极层410,并通过化学抛光工艺平整化表面,然后在平整化表面的第一电极层上410形成第一缓冲层420,在第一缓冲层420上继续执行步骤S620和S630,例如可以在第一缓冲层420上继续依次形成选通管材料层430、第二缓冲层440和第二电极层450;在另一种实现方式中,参见图7中的(b),在小孔内形成第三电极层510,并通过化学抛光工艺平整化表面,接着在平整化表面的第三电极层510上继续执行步骤S620和S630,例如可以在第三电极层510上继续依次形成选通管材料层520和第四电极层530。可选地,在完成上述步骤之后,还可以利用光刻和刻蚀技术形成最后规定尺寸的选通管,例如,特征尺寸为50nm的选通管。Optionally, referring to FIG. 7 , before forming the first material layer in step S610 , the electrode layer 720 and the insulating layer 730 may be sequentially prepared on the substrate 710 , and then features may be formed on the insulating layer 730 through photolithography and etching processes. For small holes with a size of 80-500 nm, step S610 is performed again. In one implementation, referring to (a) in FIG. 7 , a first electrode layer 410 is formed in a small hole, the surface is planarized through a chemical polishing process, and then a first electrode layer 410 is formed on the first electrode layer 410 on the planarized surface. A buffer layer 420, continue to perform steps S620 and S630 on the first buffer layer 420, for example, the gate material layer 430, the second buffer layer 440 and the second electrode layer 450 can be sequentially formed on the first buffer layer 420; In another implementation, see (b) in FIG. 7 , the third electrode layer 510 is formed in the small hole, and the surface is planarized through a chemical polishing process, and then continues on the third electrode layer 510 with the planarized surface. Steps S620 and S630 are performed, for example, the gate material layer 520 and the fourth electrode layer 530 may be sequentially formed on the third electrode layer 510 . Optionally, after completing the above steps, photolithography and etching techniques can also be used to form a gate tube with a final specified size, for example, a gate tube with a characteristic size of 50 nm.
可选地,上述衬底可以为Si衬底或SiO2衬底。应理解,上述特征尺寸可以理解为选通管表面的长、宽或直径,不做限定。Alternatively, the above-mentioned substrate may be a Si substrate or SiO 2 substrate. It should be understood that the above characteristic dimensions can be understood as the length, width or diameter of the gate tube surface, and are not limited thereto.
下面以图8所示选通管为例,结合图9和图10对该选通管的测试性能(即泄露电流和热稳定性)进行介绍。The following takes the strobe shown in Figure 8 as an example, and introduces the test performance (ie, leakage current and thermal stability) of the strobe in conjunction with Figures 9 and 10.
图8是本申请实施例提供的一种选通管的微观结构示例图,应理解,图8所示的选通管为图4所示选通管的一种示例。如图8所示,在该选通管中,底电极层410的选用的材料为W,第一缓冲层420选用的材料为C-S化合物、选通管材料层430选用的材料为Ge-S化合物、第二缓冲层440选用的材料为C-S化合物、顶电极层450选用的材料为TiN。FIG. 8 is an example diagram of the microstructure of a gate tube provided by an embodiment of the present application. It should be understood that the gate tube shown in FIG. 8 is an example of the gate tube shown in FIG. 4 . As shown in FIG. 8 , in this gate tube, the material selected for the bottom electrode layer 410 is W, the material selected for the first buffer layer 420 is a C-S compound, and the material selected for the gate material layer 430 is a Ge-S compound. The material selected for the second buffer layer 440 is C-S compound, and the material selected for the top electrode layer 450 is TiN.
应理解,在该示例中,第一缓冲层420与选通管材料层430之间以及第二缓冲层440与选通管材料层430之间均形成界面势垒;第一缓冲层420与选通管材料层430的功函数之差以及第二缓冲层440与选通管材料层430的功函数之差均约大于0.3eV;第一缓冲层420的热导率小于底电极层410的热导率以及第二缓冲层440的热导率小于顶电极层450的热导率。It should be understood that in this example, an interface barrier is formed between the first buffer layer 420 and the gate material layer 430 and between the second buffer layer 440 and the gate material layer 430; the first buffer layer 420 and the gate material layer 430 form an interface barrier. The difference in work functions of the pass tube material layer 430 and the difference in work functions of the second buffer layer 440 and the gate tube material layer 430 are both approximately greater than 0.3 eV; the thermal conductivity of the first buffer layer 420 is smaller than that of the bottom electrode layer 410 The conductivity and thermal conductivity of the second buffer layer 440 are less than the thermal conductivity of the top electrode layer 450 .
还需说明的是,图8所示的微观结构为400℃退火后的选通管的微观结构,从图8可以看出,第一缓冲层C-S、选通管材料层Ge-S与第二缓冲层C-S形成的三明治异质结构在退火后仍保持非晶状态,没有发生结晶相变,意味着该选通管的热稳定性较高。这是由于,一方面,第一缓冲层和第二缓冲层的引入为选通管引入了更多的界面,使得缓冲层与选通管材料
层之间可以产生界面效应(即声子散射),从而能够降低缓冲层与选通管材料层之间的热导率,进而可以阻碍外界至选通管材料层的热传递,提高了选通管的热稳定性;另一方面,第一缓冲层的热导率小于底电极层的热导率以及第二缓冲层的热导率小于顶电极层的热导率,阻碍了外界至选通管材料层的热传递,进一步提高了选通管的热稳定性。It should also be noted that the microstructure shown in Figure 8 is the microstructure of the gate tube after annealing at 400°C. It can be seen from Figure 8 that the first buffer layer CS, the gate tube material layer Ge-S and the second The sandwich heterostructure formed by the buffer layer CS remains in an amorphous state after annealing and does not undergo crystalline phase change, which means that the gate tube has high thermal stability. This is because, on the one hand, the introduction of the first buffer layer and the second buffer layer introduces more interfaces to the gate tube, so that the buffer layer and the gate tube material The interface effect (i.e. phonon scattering) can be produced between the layers, which can reduce the thermal conductivity between the buffer layer and the gate material layer, thereby hindering the heat transfer from the outside to the gate material layer and improving the gate. Thermal stability of the tube; on the other hand, the thermal conductivity of the first buffer layer is smaller than the thermal conductivity of the bottom electrode layer and the thermal conductivity of the second buffer layer is smaller than the thermal conductivity of the top electrode layer, hindering the external access to the gate The heat transfer of the tube material layer further improves the thermal stability of the gate tube.
图9是本申请实施例提供的一种选通管的电压-电流曲线示例图。具体地,图9为图8所示选通管在400℃退火30min后所测试的电压-电流曲线示例图。如图9所示,可以看出,该选通管在400℃退火30min后仍可以保持稳定的开关特性。图10是本申请实施例提供的另一种选通管的电压-电流曲线示例图。具体地,图10为图9的局部放大图,可以看出该选通管的漏电流小于400pA。这是由于第一缓冲层与选通管材料层的接触面以及第二缓冲层与选通管材料层的接触面均具有功函数之差,从而形成了界面势垒,使得电子可以局域在势垒处,从而能够降低泄露电流。综上说明,本申请实施例所提供的选通管具有热稳定性高、泄露电流低的优势。且其中降低漏电流到了pA级别,因此可以满足存储单元高密度集成的需求。FIG. 9 is an example diagram of a voltage-current curve of a strobe provided by an embodiment of the present application. Specifically, FIG. 9 is an example diagram of the voltage-current curve tested after the gate tube shown in FIG. 8 was annealed at 400° C. for 30 minutes. As shown in Figure 9, it can be seen that the gate tube can still maintain stable switching characteristics after annealing at 400°C for 30 minutes. FIG. 10 is an example diagram of a voltage-current curve of another strobe provided by an embodiment of the present application. Specifically, FIG. 10 is a partial enlarged view of FIG. 9 , and it can be seen that the leakage current of the gate tube is less than 400 pA. This is because the contact surface between the first buffer layer and the gate material layer and the contact surface between the second buffer layer and the gate material layer both have differences in work functions, thus forming an interface barrier, allowing electrons to be localized in barrier, thereby reducing leakage current. In summary, the gate tube provided by the embodiment of the present application has the advantages of high thermal stability and low leakage current. And the leakage current is reduced to the pA level, so it can meet the needs of high-density integration of memory cells.
本申请实施例还提供了一种存储芯片,包括多个存储单元和多个本申请实施例中所提供的选通管,每个存储单元对应一个选通管。An embodiment of the present application also provides a memory chip, which includes a plurality of memory units and a plurality of strobe tubes provided in the embodiments of the present application, with each memory unit corresponding to a strobe tube.
可选地,该存储芯片可以包括交叉阵列存储结构,该交叉阵列存储结构可以为二维交叉阵列存储结构,也可以为三维交叉阵列存储结构,不做限定。Optionally, the memory chip may include a cross-array storage structure, and the cross-array storage structure may be a two-dimensional cross-array storage structure or a three-dimensional cross-array storage structure, without limitation.
本申请实施例还提供了一种存储器,包括:本申请实施例中所提供的存储芯片;外围电路,用于对存储芯片中的数据进行读写操作。An embodiment of the present application also provides a memory, which includes: the memory chip provided in the embodiment of the present application; and a peripheral circuit for reading and writing data in the memory chip.
本申请实施例还提供了一种电子设备,包括本申请实施例中所提供的存储器。可选地,该电子设备例如可以包括台式电脑、笔记本电脑、智能手机、平板电脑、个人数字助理(personal digital assistant,PDA)、可穿戴设备、智能音箱、电视、无人机、车辆、车载装置(例如车机、车载电脑、车载芯片等)或机器人等等。An embodiment of the present application also provides an electronic device, including the memory provided in the embodiment of the present application. Optionally, the electronic device may include, for example, a desktop computer, a notebook computer, a smartphone, a tablet, a personal digital assistant (PDA), a wearable device, a smart speaker, a television, a drone, a vehicle, or a vehicle-mounted device. (such as car machines, car computers, car chips, etc.) or robots, etc.
以上所述,仅为本申请的具体实施方式,但本申请的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本申请揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本申请的保护范围之内。因此,本申请的保护范围应以所述权利要求的保护范围为准。
The above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application. should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.
Claims (12)
- 一种选通管,其特征在于,包括:第一材料层、选通管材料层和第二材料层,A gate tube, characterized in that it includes: a first material layer, a gate tube material layer and a second material layer,其中,所述第一材料层的第一表面与所述选通管材料层的第一表面接触,所述第二材料层的第一表面与所述选通管材料层的第二表面接触,所述第一材料层与所述选通管材料层形成势垒;和/或,所述第二材料层与所述选通管材料层形成势垒。Wherein, the first surface of the first material layer is in contact with the first surface of the gate tube material layer, and the first surface of the second material layer is in contact with the second surface of the gate tube material layer, The first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.
- 根据权利要求1所述的选通管,其特征在于,所述第一材料层与所述选通管材料层的第一功函数之差大于或等于0.3eV;和/或,所述第二材料层与所述选通管材料层的第二功函数之差大于或等于0.3eV。The gate tube according to claim 1, wherein the difference between the first work functions of the first material layer and the gate tube material layer is greater than or equal to 0.3eV; and/or, the second The difference between the second work functions of the material layer and the gate material layer is greater than or equal to 0.3 eV.
- 根据权利要求2所述的选通管,其特征在于,所述第一功函数之差和/或所述第二功函数之差大于或等于0.5eV,且小于或等于0.65eV。The gate tube according to claim 2, wherein the difference between the first work function and/or the second work function is greater than or equal to 0.5eV and less than or equal to 0.65eV.
- 根据权利要求1至3中任一项所述的选通管,其特征在于,所述第一材料层包括第一多级热导率,所述第一多级热导率从所述第一材料层的第二表面至所述第一材料层的第一表面逐级递减;和/或,所述第二材料层包括第二多级热导率,所述第二多级热导率从所述第二材料层的第二表面至所述第二材料层的第一表面逐级递减。The gate tube according to any one of claims 1 to 3, characterized in that the first material layer includes a first multi-level thermal conductivity, the first multi-level thermal conductivity is from the first The second surface of the material layer decreases gradually from the first surface of the first material layer; and/or the second material layer includes a second multi-level thermal conductivity, and the second multi-level thermal conductivity decreases from The distance from the second surface of the second material layer to the first surface of the second material layer gradually decreases.
- 根据权利要求4所述的选通管,其特征在于,所述第一材料层包括第一缓冲层和第一电极层,所述第一缓冲层的第一表面作为所述第一材料层的第一表面,所述第一电极层的第一表面与所述第一缓冲层的第二表面接触,所述第一多级热导率包括所述第一缓冲层的热导率和所述第一电极层的热导率;和/或,所述第二材料层包括第二缓冲层和第二电极层,所述第二缓冲层的第一表面作为所述第二材料层的第一表面,所述第二电极层的第一表面与所述第二缓冲层的第二表面接触,所述第二多级热导率包括所述第二缓冲层的热导率和所述第二电极层的热导率。The gate tube according to claim 4, wherein the first material layer includes a first buffer layer and a first electrode layer, and the first surface of the first buffer layer serves as the first material layer. a first surface, the first surface of the first electrode layer is in contact with the second surface of the first buffer layer, and the first multi-level thermal conductivity includes the thermal conductivity of the first buffer layer and the The thermal conductivity of the first electrode layer; and/or the second material layer includes a second buffer layer and a second electrode layer, and the first surface of the second buffer layer serves as the first surface of the second material layer. surface, the first surface of the second electrode layer is in contact with the second surface of the second buffer layer, and the second multi-level thermal conductivity includes the thermal conductivity of the second buffer layer and the second Thermal conductivity of the electrode layer.
- 根据权利要求4所述的选通管,其特征在于,所述第一材料层包括第三电极层,所述第一多级热导率为所述第三电极层的多级热导率;和/或,所述第二材料层包括第四电极层,所述第二多级热导率为所述第四电极层的多级热导率。The gate tube according to claim 4, wherein the first material layer includes a third electrode layer, and the first multi-level thermal conductivity is the multi-level thermal conductivity of the third electrode layer; And/or, the second material layer includes a fourth electrode layer, and the second multi-level thermal conductivity is the multi-level thermal conductivity of the fourth electrode layer.
- 根据权利要求5所述的选通管,其特征在于,所述第一缓冲层和/或所述第二缓冲层包括非晶碳、SiC、CS、TeC、TeCS、MoTe2、MoS2、MnTe、HfO2/TaO、WTe2、WS2中的任意一种或多种。The gate tube according to claim 5, characterized in that the first buffer layer and/or the second buffer layer include amorphous carbon, SiC, CS, TeC, TeCS, MoTe 2 , MoS 2 , MnTe , any one or more of H f O 2 /TaO, WTe 2 and WS 2 .
- 一种选通管的制备方法,其特征在于,包括:A method for preparing a gate tube, characterized in that it includes:形成第一材料层;forming a first material layer;在所述第一材料层的第一表面上形成选通管材料层,所述第一材料层的第一表面与所述选通管材料层的第一表面接触;forming a gate tube material layer on the first surface of the first material layer, the first surface of the first material layer being in contact with the first surface of the gate tube material layer;在所述选通管材料层的第二表面上形成第二材料层,所述第二材料层的第一表面与所述选通管材料层的第二表面接触,A second material layer is formed on the second surface of the gate tube material layer, and the first surface of the second material layer is in contact with the second surface of the gate tube material layer,其中,所述第一材料层与所述选通管材料层形成势垒;和/或,所述第二材料层与所述选通管材料层形成势垒。Wherein, the first material layer and the gate tube material layer form a potential barrier; and/or the second material layer and the gate tube material layer form a potential barrier.
- 根据权利要求8所述的制备方法,其特征在于,所述第一材料层与所述选通管材料层的第一功函数之差大于或等于0.3eV;和/或,所述第二材料层与所述选通管材料层的第二功函数之差大于或等于0.3eV。The preparation method according to claim 8, characterized in that the difference between the first work functions of the first material layer and the gate material layer is greater than or equal to 0.3eV; and/or, the second material The difference between the second work function of the layer and the gate material layer is greater than or equal to 0.3 eV.
- 根据权利要求8或9所述的制备方法,其特征在于,所述第一材料层包括第一多级热导率,所述第一多级热导率从所述第一材料层的第二表面至所述第一材料层的第一表面逐级递减;和/或,所述第二材料层包括第二多级热导率,所述第二多级热导率从所述第二材料 层的第二表面至所述第二材料层的第一表面逐级递减。The preparation method according to claim 8 or 9, characterized in that the first material layer includes a first multi-level thermal conductivity, and the first multi-level thermal conductivity is obtained from a second layer of the first material layer. The surface to the first surface of the first material layer gradually decreases; and/or the second material layer includes a second multi-level thermal conductivity, the second multi-level thermal conductivity is from the second material layer to the first surface of the first material layer. The second surface of the layer gradually decreases to the first surface of the second material layer.
- 一种存储芯片,包括多个存储单元和多个如权利要求1至7中任一项所述的选通管,每个存储单元对应一个选通管。A memory chip includes a plurality of memory units and a plurality of strobe tubes according to any one of claims 1 to 7, each memory unit corresponding to a strobe tube.
- 一种存储器,其特征在于,包括:A memory, characterized in that it includes:如权利要求11所述的存储芯片;The memory chip according to claim 11;外围电路,用于对所述存储芯片中的数据进行读写操作。 Peripheral circuit, used for reading and writing data in the memory chip.
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US20110147696A1 (en) * | 2009-12-23 | 2011-06-23 | Samsung Electronics Co., Ltd. | Resistive random access memory devices and resistive random access memory arrays having the same |
CN112242487A (en) * | 2020-10-15 | 2021-01-19 | 华中科技大学 | Gate tube with quasi-superlattice structure and preparation method thereof |
CN112652713A (en) * | 2020-12-15 | 2021-04-13 | 华中科技大学 | Gate tube with quasi-superlattice structure and preparation method thereof |
CN113571635A (en) * | 2020-09-16 | 2021-10-29 | 中国科学院上海微系统与信息技术研究所 | Gating tube material, gating tube unit, preparation method and memory structure |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110147696A1 (en) * | 2009-12-23 | 2011-06-23 | Samsung Electronics Co., Ltd. | Resistive random access memory devices and resistive random access memory arrays having the same |
CN113571635A (en) * | 2020-09-16 | 2021-10-29 | 中国科学院上海微系统与信息技术研究所 | Gating tube material, gating tube unit, preparation method and memory structure |
CN112242487A (en) * | 2020-10-15 | 2021-01-19 | 华中科技大学 | Gate tube with quasi-superlattice structure and preparation method thereof |
CN112652713A (en) * | 2020-12-15 | 2021-04-13 | 华中科技大学 | Gate tube with quasi-superlattice structure and preparation method thereof |
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