KR20210153275A - Electronic device - Google Patents

Abstract

The present technology is to provide an electronic device comprising a semiconductor memory having an improved reliability. Provided is the electronic device comprising: a first conductive line; a second conductive line crossing the first conductive line; and a memory cell positioned between the first conductive line and the second conductive line in which a chalcogenide film and at least one threshold voltage adjustment film are stacked, wherein the chalcogenide film has a first threshold voltage in a thermal equilibrium state, is programmed to have a second threshold voltage greater than that of the first threshold voltage in response to a second polarity program voltage, and is programmed to have the first threshold voltage at the second threshold voltage in response to a program voltage of a first polarity different from the second polarity.

Description

Electronic device {ELECTRONIC DEVICE}

The present invention relates to memory circuits or semiconductor devices and their applications in electronic devices.

Recently, in accordance with miniaturization, low power consumption, high performance, and diversification of electronic devices, a semiconductor device capable of storing information in various electronic devices such as computers and portable communication devices is required, and research on this is being conducted. As such a semiconductor device, a semiconductor device capable of storing data using a characteristic of switching between different resistance states according to an applied voltage or current, for example, RRAM (Resistive Random Access Memory), PRAM (Phase-change Random Access Memory) , Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), E-fuse, and the like.

SUMMARY An object of the present invention is to provide an electronic device including a semiconductor memory having improved reliability.

An electronic device according to an embodiment of the present invention includes a first conductive line; a second conductive line crossing the first conductive line; and a memory cell positioned between the first conductive line and the second conductive line, in which a chalcogenide layer and at least one threshold voltage control layer are stacked, wherein the chalcogenide layer controls a first threshold voltage in a thermal equilibrium state. is programmed to have a second threshold voltage greater than the first threshold voltage in response to a program voltage of a second polarity, and is programmed to have a second threshold voltage greater than the first threshold voltage at the second threshold voltage in response to a program voltage having a first polarity different from the second polarity It can be programmed to have a threshold voltage of 1.

The chalcogenide layer includes a first number of electron traps in the youngest in a thermal equilibrium state, and the number of the electron traps in the youngest member decreases to a second number smaller than the first number in response to a program voltage of the second polarity; The number of the electron traps in the youngest member may increase from the second number to the first number in response to the first polarity program voltage.

The chalcogenide layer may include a material capable of ovonic threshold switching. The chalcogenide layer may include tellurium (Te) or selenium (Se), and the threshold voltage control layer may include a metal highly reactive with tellurium (Te) or selenium (Se) among transition metals. The threshold voltage control layer may include a plurality of protons movable in response to the program voltage of the first polarity and the program voltage of the second polarity, and the protons may include hydrogen. The threshold voltage control layer may include one formed in situ in the same chamber as the chalcogenide layer using a sputtering method at room temperature. The program voltage of the first polarity may be a negative voltage, and the program voltage of the second polarity may be a positive voltage.

When the program voltage of the first polarity and the program voltage of the second polarity are applied to the first conductive line, the threshold voltage adjusting layer is inserted between the chalcogenide layer and the first conductive line, and the first When the polarity program voltage and the second polarity program voltage are applied to the second conductive line, the threshold voltage control layer may be inserted between the chalcogenide layer and the second conductive line. The threshold voltage control layer may be respectively inserted between the first conductive line and the chalcogenide layer and between the second conductive line and the chalcogenide layer.

An electronic device according to an embodiment of the present invention includes a first conductive line; a second conductive line crossing the first conductive line; and a memory cell positioned between the first conductive line and the second conductive line, in which a chalcogenide layer including tellurium (Te) or selenium (Se) and at least one threshold voltage control layer are stacked, the A reaction layer may be formed or destroyed between the chalcogenide layer and the threshold voltage control layer in response to a program voltage applied to the memory cell.

The chalcogenide layer has a first threshold voltage in a thermal equilibrium state, the reaction layer is generated in response to a positive program voltage applied to the memory cell, and is programmed to have a second threshold voltage greater than the first threshold voltage; In response to a negative program voltage applied to the memory cell, the reactive layer may be dissipated to be programmed to have the first threshold voltage at the second threshold voltage.

The chalcogenide layer includes a first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member is smaller than the first number while the reaction layer is generated in response to a positive program voltage applied to the memory cell. The number of electron traps decreases from the second number, and as the reaction layer disappears in response to the negative program voltage applied to the memory cell, the number of the electron traps in the youngest member may increase from the second number to the first number.

The reaction layer may include telluride or selenide generated by a reaction between tellurium (Te) or selenium (Se) of the chalcogenide layer and the threshold voltage control layer. The threshold voltage control layer may include any one selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf).

When the program voltage is applied to the first conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the first conductive line, and when the program voltage is applied to the second conductive line, the A threshold voltage control layer may be inserted between the chalcogenide layer and the second conductive line.

An electronic device according to an embodiment of the present invention includes a first conductive line; a second conductive line crossing the first conductive line; and a memory cell in which a chalcogenide layer including a plurality of electron traps in a youngest member and at least one threshold voltage control layer including protons in the youngest layer are stacked between the first conductive line and the second conductive line, the memory cell comprising: The chalcogenide layer includes a first number of electron traps in the youngest member in a thermal equilibrium state, and the electron traps in the youngest member as protons of the threshold voltage control layer are injected into the chalcogenide layer in response to a positive program voltage applied to the memory cell. The number of the electrons decreases to a second number smaller than the first number, and the protons injected into the chalcogenide layer in response to a negative program voltage applied to the memory cell are injected into the threshold voltage control layer, and the electrons in the youngest The number of traps may increase from the second number to the first number.

The chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and the mobile protons of the proton storage layer are injected into the chalcogenide layer in response to a positive program voltage applied to the memory cell, which is greater than the first threshold voltage. The mobile protons programmed to have a second threshold voltage and injected into the chalcogenide layer in response to a negative program voltage applied to the memory cell are injected into the proton storage layer to increase the first threshold voltage from the second threshold voltage. can be programmed to have

The chalcogenide layer may include a material capable of ovonic threshold switching. The proton may include hydrogen, and the threshold voltage control layer may include a silicon oxide layer containing hydrogen.

When the positive program voltage and the negative program voltage are applied to the first conductive line, the threshold voltage adjusting layer is inserted between the chalcogenide layer and the first conductive line, and the positive program voltage and the negative program voltage are applied to the first conductive line. When applied to the second conductive line, the threshold voltage control layer may be inserted between the chalcogenide layer and the second conductive line.

This technology, based on the means for solving the above problems, has a memory cell having a simple structure in which a chalcogenide layer and a threshold voltage control layer are stacked, and a first threshold voltage and a second threshold voltage in response to a program voltage applied to the memory cell. Reversible transition between voltages has an effect of improving the reliability of the semiconductor memory.

In addition, since the chalcogenide layer operates as a selection device and a memory device, the memory cell has the effect of enabling high integration and low power operation.

In addition, since the memory cell is a two-terminal device that can be implemented through a sputtering process at room temperature, the process difficulty is very low, the yield can be improved, and the production cost can be lowered.

In addition, since the memory cell is a two-terminal device, it has excellent scalability, and the difference between the first threshold voltage and the second threshold voltage can be easily increased according to the size of the program voltage, so that it is easy to implement a multi-level cell. there is Through this, scalability can be further improved.

In addition, since the chalcogenide layer of the memory cell is made of a material capable of ovonic threshold switching, an operation speed of several ns can be realized, thereby enabling high-speed operation.

1 is a perspective view illustrating a semiconductor memory according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a memory cell of a semiconductor memory according to an embodiment of the present invention.
3 is a current-voltage graph illustrating a change in threshold voltage of a memory cell according to a program voltage in a semiconductor memory according to an embodiment of the present invention.
4 is an example of a configuration diagram of a microprocessor implementing a memory device according to an embodiment of the present invention.
5 is an example of a configuration diagram of a processor implementing a memory device according to an embodiment of the present invention.
6 is an example of a configuration diagram of a system for implementing a memory device according to an embodiment of the present invention.
7 is an example of a configuration diagram of a data storage system implementing a memory device according to an embodiment of the present invention.
8 is an example of a configuration diagram of a memory system implementing a memory device according to an embodiment of the present invention.

Advantages and features of the present invention and methods of achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the technical field to which the present invention belongs It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Sizes and relative sizes of layers and regions in the drawings may be exaggerated for clarity of description. Like reference numerals refer to like elements throughout.

An embodiment of the present invention, which will be described later, is to provide an electronic device including a semiconductor memory having improved reliability. Here, the semiconductor memory with improved reliability may refer to an ideal semiconductor memory having a simple structure, easy integration, high-speed and low-power operation, and robust stability and scalability. To this end, the electronic device according to an embodiment of the present invention may include a two-terminal semiconductor memory using a material capable of ovonic threshold switching (OTS).

1 is a perspective view illustrating a semiconductor memory according to an embodiment of the present invention. 2 is a cross-sectional view illustrating a memory cell of a semiconductor memory according to an embodiment of the present invention. 3 is a current-voltage graph illustrating a change in threshold voltage of a memory cell according to a program voltage in a semiconductor memory according to an embodiment of the present invention.

1 to 3 , the semiconductor memory according to the embodiment may include a memory cell array formed on a substrate (not shown). Here, the memory cell array includes a plurality of first conductive lines 110 extending in the first direction D1 , a first conductive line formed on the plurality of first conductive lines 110 , and intersecting the first direction D1 . A plurality of second conductive lines 120 extending in the two directions D2 and a plurality of memory cells respectively positioned between the plurality of first conductive lines 110 and the plurality of second conductive lines 120 (MC) may be included. That is, the memory cell array of the semiconductor memory according to the embodiment may have a cross point array architecture.

For reference, in FIG. 1 , three first conductive lines 110 arranged in parallel in the second direction D2, three second conductive lines 120 arranged in parallel in the first direction D1, and Although the nine memory cells MC disposed therebetween are illustrated, this is only for convenience of description, and the present invention is not limited thereto. Also, although FIG. 1 illustrates a case in which the memory cell array has a single-deck structure, the present invention is not limited thereto, and the memory cells MC may be vertically stacked. For example, the memory cell array may have a multi-deck structure in which first conductive lines 110 and second conductive lines 120 are alternately stacked in a vertical direction. In this case, the memory cells MC may be positioned between the alternately stacked first conductive lines 110 and second conductive lines 120 . In the memory cell array according to the embodiment, the degree of integration of the semiconductor memory may be improved by arranging the memory cells MC in a cross-point array structure. In addition, by stacking the memory cells MC in a multi-deck structure, the degree of integration of the semiconductor memory may be further improved.

Meanwhile, although not shown in the drawings, the substrate positioned under the memory cell array may include peripheral circuits for operating the memory cell array. The peripheral circuit may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the memory cell array. NMOS and PMOS transistors, registers, and capacitors may be used as elements constituting a row decoder, a column decoder, a page buffer, and a control circuit. As such, as the memory cell array is disposed on the substrate including the peripheral circuit, the area of the substrate occupied by the memory cell MC array and the peripheral circuit may be reduced.

Each of the plurality of first conductive lines 110 may be a word line or a row line, and each of the plurality of second conductive lines 120 may be a bit line or a column line. Here, the word line and the bit line are stateful concepts, and the first conductive line 110 may be a bit line and the second conductive line 120 may be a word line. The plurality of first conductive lines 110 may be disposed in parallel with a predetermined interval in the second direction D2, and each of the plurality of second conductive lines 120 may be disposed at a predetermined interval in the first direction D1. It may be spaced apart and arranged in parallel. In this case, the spacing between the plurality of first conductive lines 110 and the spacing between the plurality of second conductive lines 120 may be the same. Each of the plurality of first conductive lines 110 and the plurality of second conductive lines 120 may include a conductive material such as polysilicon or metal. For example, each of the plurality of first conductive lines 110 and the plurality of second conductive lines 120 may be tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), or titanium. nitride (WN _x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), etc. It may include a combination of

Each of the plurality of memory cells MC may be disposed at a point where the first conductive lines 110 and the second conductive lines 120 intersect, and may be arranged in a matrix form. Each of the plurality of memory cells MC may be a memory stack in which a lower electrode 130 , a chalcogenide layer 140 , a threshold voltage control layer 150 , and an upper electrode 160 are sequentially stacked. Here, each of the plurality of memory cells MC is programmed to have a first threshold voltage V _{th 1 in response to a program voltage -V program} having a first polarity, and a program voltage having a second polarity different from the first polarity. In response to (+V _program ), it may be programmed to have a second threshold voltage V _th 2 greater than the first threshold voltage V _{th 1 .} In this case, the first polarity program voltage (-V _program ) may be a negative voltage, and the second polarity program voltage (+V _program ) may be a positive voltage. _{In addition, the first threshold voltage V th} 1 in each of the plurality of memory cells MC may be an initial threshold voltage or a threshold voltage in a thermal equilibrium state.

In each of the plurality of memory cells MC, the lower electrode 130 and the upper electrode 160 may each include a conductive material such as polysilicon or metal. For example, the lower electrode 130 and the upper electrode 160 are tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), titanium (Ti), titanium nitride (WN _x ), titanium silicon nitride ( TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbon nitride ( SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), etc. may be included, and a combination thereof may be included. Meanwhile, the lower electrode 130 and the upper electrode 160 may be replaced with the first conductive line 110 and the second conductive line 120 , respectively.

The chalcogenide layer 140 may act as a selection device and a memory device. Specifically, the chalcogenide layer 140 may refer to a material layer capable of rapidly switching the state to the on state when a program voltage equal to or greater than a threshold voltage, which is a turn-on voltage, is applied while maintaining an off state, which is a basic low current state. In other words, the chalcogenide layer 140 may be programmed to have a first threshold voltage V _{th 1 in response to a first polarity program voltage -V program} , and may have a second polarity different from the first polarity. It may be programmed to have a second threshold voltage V _th 2 greater than the first threshold voltage V _th 1 in response to the program voltage +V _{program .} To this end, the chalcogenide layer 140 may include a material capable of ovonic threshold switching (OTS). Here, the material capable of ovonic threshold switching may refer to a binary or more multi-component compound including at least one chalcogen element.

Specifically, the chalcogenide layer 140 may be a compound capable of ovonic threshold switching and including at least one chalcogen element (ie, a group 16 element) and one or more electropositive elements. Here, the chalcogenide layer 140 may include a plurality of electronic traps in the youngest member, and a first threshold voltage (V _th 1 ) and a second threshold voltage ( V th 1 ) and a second threshold voltage ( V _th 2) can be reversibly transitioned. To this end, the chalcogenide layer 140 may include tellurium (Te) or selenium (Se). For reference, tellurium and selenium in the chalcogenide layer 140 may act as a major factor in determining the threshold voltage distribution and the number of electron traps.

The threshold voltage control layer 150 controls the number of electron traps in the chalcogenide layer 140 so that the chalcogenide layer 140 reversibly moves between the first threshold voltage Vth1 and the second threshold voltage Vth2. It can play a role in controlling the transition. To this end, the threshold voltage control layer 150 _{reacts with tellurium or selenium in the chalcogenide layer 140 in response to a program voltage (±V program} ), so that the interface between the chalcogenide and the threshold voltage control layer 150 is in contact. It may contain a material capable of generating or destroying the reaction film. Here, the reaction layer may include telluride or selenide generated by reacting with tellurium or selenium of the threshold voltage control layer 150 and the chalcogenide layer 140 .

Specifically, the threshold voltage control layer 150 may include transition metals, and among transition metals, a metal highly reactive with tellurium or selenium. More specifically, the threshold voltage control layer 150 may include any one metal layer selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf). For reference, the threshold voltage control layer 150 including the transition metal may be formed in situ in the same chamber as the chalcogenide layer 140 using sputtering at room temperature. This is a process in which a predetermined reactant, for example, telluride or selenide, is formed between the chalcogenide layer 140 and the threshold voltage control layer 150 in the process of forming the threshold voltage control layer 150 including the transition metal. in order to prevent

For example, the chalcogenide layer 140 includes tellurium, the threshold voltage control layer 150 is a titanium layer, and in a thermal equilibrium state, the chalcogenide layer 140 traps the first number of electron traps in the youngest member. and has a first threshold voltage Vth1. Here, when a program voltage (+V _program ) of the second polarity, that is, a positive voltage, is applied to the upper electrode 160, the tellurium in the chalcogenide layer 140 is caused by _{the program voltage (+V program) of the second polarity. A reaction layer including telluride (TiTe 2} ) may be formed at an interface between the chalcogenide layer 140 and the threshold voltage control layer 150 by reacting with the titanium. When a reaction film is formed at the interface between the chalcogenide film 140 and the threshold voltage control film 150 , the chalcogenide film 140 becomes deficient in tellurium compared to the thermal equilibrium state, so the number of electron traps in the youngest. is reduced to a second number smaller than the first number. As such, when the tellurium content in the chalcogenide film 140 decreases and the number of electron traps in the chalcogenide film 140 decreases compared to the thermal equilibrium state, the chalcogenide film 140 is the threshold in the thermal equilibrium state. The voltage may be programmed to have a second threshold voltage V _th 2 that is greater than the first threshold voltage V _{th 1 .}

On the other hand, _{when the first polarity program voltage (-V program} ), that is, a negative voltage is applied to the upper electrode 160 in a state in which the _{chalcogenide layer 140 is programmed to have the second threshold voltage V th 2 ,} The reaction film created at the interface between the chalcogenide film 140 and the threshold voltage control film 150 is annihilated, and the tellurium of the annihilated reaction film is injected into the chalcogenide film to tell the chalcogenide film 140 . The content of rurium may be restored to be the same as the content of tellurium in the thermal equilibrium state. Accordingly, since the number of electron traps in the chalcogenide layer 140 also increases from the second number to the first number at a level corresponding to the thermal equilibrium state, the chalcogenide layer 140 has a second threshold voltage (V _{th )} 2) It may be programmed to have a lower first threshold voltage (V _th 1 ), that is, a threshold voltage of a thermal equilibrium state.

Here, when the read voltage V _read is set to a voltage between the first threshold voltage V _th 1 and the second threshold voltage V _th 2 , it is possible to distinguish whether to program by the current level. At this time, since the magnitude of the second threshold voltage V _th 2 also gradually increases as the magnitude of the second polarity program voltage (+V _{program ) increases, the first threshold voltage V th} 1 and the second threshold voltage (V th 1 ) If the read voltage V _{read is subdivided between V th} 2 ), a plurality of pieces of information may be stored in one memory cell MC. That is, it is possible to implement a multi-level cell.

Meanwhile, the threshold voltage control layer 150 controls the number of electron traps in the chalcogenide layer 140 so that the chalcogenide layer 140 has a first threshold voltage (V _th 1 ) and a second threshold voltage (V _{th ).} 2) It is also possible to use protons to control the reversible transition between them. To this end, the threshold voltage control layer 150 may include a plurality of protons that are movable in response to a _{program voltage (±V program).} Specifically, the threshold voltage control layer 150 may include a plurality of hydrogens that are movable in response to a _{program voltage ±V program.} For example, the threshold voltage control layer 150 may include a silicon oxide layer containing hydrogen. For reference, the silicon oxide film containing hydrogen may be formed in situ in the same chamber as the chalcogenide film 140 by sputtering at room temperature using argon gas and hydrogen gas with silicon oxide as a target. In this case, an amorphous silicon oxide film containing hydrogen having many defects in the film and a thin thickness, that is, having a thickness ranging from several to several tens of nm, may be formed. Although the silicon oxide film is an insulating material, it has many defects in the film and if it is formed thinly to have a thickness of several tens of nm or less, conductivity like a conductive film can be imparted.

Specifically, the chalcogenide layer 140 includes the first number of electron traps in the youngest member in a thermal equilibrium state, and when the threshold voltage control layer 150 is a silicon oxide layer containing hydrogen, it is first applied to the upper electrode 160 . When a bipolar program voltage (+V _program ) is applied, protons, ie, hydrogen, of the threshold voltage control film 150 are injected into the chalcogenide film 140 by the program voltage (+V _{program) of the second polarity.} do. Hydrogen injected into the chalcogenide layer 140 is coupled to the electron traps in the youngest member, so that the number of electron traps in the chalcogenide layer 140 is reduced from the first number to the second number. At this time, as the number of electron traps in the chalcogenide layer 140 decreases to the second number, the chalcogenide layer 140 _{becomes larger than the first threshold voltage V th} 1 , which is the threshold voltage in the thermal equilibrium state. It may be programmed to have the second threshold voltage V _{th 2 .}

On the other hand, _{when the first polarity program voltage (-V program} ), that is, a negative voltage is applied to the upper electrode 160 in a state in which the _{chalcogenide layer 140 is programmed to have the second threshold voltage V th 2 ,} As hydrogen bound to the electron traps in the chalcogenide layer 140 is separated from the electron traps and moves into the threshold voltage control layer 150 , the number of electron traps in the chalcogenide layer 140 increases to a second number. may increase to the first number, which is the number of electron traps in the thermal equilibrium state. Accordingly, the chalcogenide layer 140 may be programmed to have a first threshold voltage V _{th 1 lower than the second threshold voltage V th} 2 , that is, a threshold voltage in a thermal equilibrium state.

The threshold voltage control layer 150 may be inserted between the chalcogenide layer 140 and the upper electrode 160 . Although the embodiment exemplifies the case in which the threshold voltage control layer 150 is inserted between the chalcogenide layer 140 and the upper electrode 160 , the present invention is not limited thereto. As a modification, the threshold voltage control layer 150 may be inserted between the chalcogenide layer 140 and the lower electrode 130 . Here, a position at which the threshold voltage control layer 150 is inserted may be determined according to an electrode to which a _{program voltage ±V program is applied.} For example, when a program voltage (±V _program ) is applied to the upper electrode 160 , the threshold voltage adjusting film 150 may be inserted between the chalcogenide film 140 and the upper electrode 160 , , when a program voltage (±V _program ) is applied to the lower electrode 130 , the threshold voltage adjusting film 150 may be inserted between the chalcogenide film 140 and the lower electrode 130 . Meanwhile, as another modification, the threshold voltage control layer 150 may be inserted both between the chalcogenide layer 140 and the lower electrode 130 and between the chalcogenide layer 140 and the upper electrode 160 . have. At this time, the threshold voltage control layer 150 is inserted between the chalcogenide layer 140 and the lower electrode 130, and the threshold voltage control layer 150 is inserted between the chalcogenide layer 140 and the upper electrode (160). ) may be identical to each other.

As described above, in the semiconductor memory according to the embodiment, the memory cell MC has a simple structure in which a chalcogenide layer 140 and a threshold voltage control layer 150 are stacked, and a program is applied to the memory cell MC. By reversibly transitioning between the first threshold voltage V _th 1 and the second threshold voltage V _th 2 in response to the voltage ±V _program , the reliability of the semiconductor memory may be improved.

In addition, since the chalcogenide layer 140 operates as a selection device and a memory device, the memory cell MC can be highly integrated and operated with low power.

In addition, since the memory cell MC is a two-terminal device that can be implemented through a sputtering process at room temperature, the process difficulty is very low, the yield can be improved, and the production cost can be lowered.

In addition, since the memory cell MC is a two-terminal device, it has excellent scalability, and is located between the first threshold voltage V _th 1 and the second threshold voltage V _th 2 _{according to the size of the program voltage ±V program .} Since the difference between , can be easily increased, it is easy to implement a multi-level cell, thereby further improving scalability.

In addition, since the chalcogenide layer 140 is made of a material capable of ovonic threshold switching, the memory cell MC can realize an operation speed of several ns, so that a high-speed operation is possible.

The semiconductor memory according to the above-described embodiment may be used in various electronic devices or systems. 4 to 8 illustrate some examples of electronic devices or systems that can be implemented using the semiconductor memory according to the above-described embodiment.

4 is an example of a configuration diagram of a microprocessor implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 4 , the microprocessor 1000 may control and adjust a series of processes of receiving and processing data from various external devices and sending the results to the external device, and a storage unit 1010, It may include an operation unit 1020 , a control unit 1030 , and the like. The microprocessor 1000 includes a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processing unit (DSP), an application processor (AP), etc. It may be a data processing device.

The storage unit 1010 is a processor register, a register, etc., and may be a part for storing data in the microprocessor 1000, and may include a data register, an address register, a floating-point register, and the like. In addition, it may include various registers. The storage unit 1010 may serve to temporarily store the data for which the operation unit 1020 performs the operation, the execution result data, and an address in which the data for the execution is stored.

The storage unit 1010 may include one or more of the above-described semiconductor memory embodiments. For example, the memory unit 1010 includes a first conductive line, a second conductive line intersecting the first conductive line, and between the first conductive line and the second conductive line, and includes a chalcogenide layer and at least one threshold voltage control layer. Including stacked memory cells, the chalcogenide layer has a first threshold voltage in a thermal equilibrium state, is programmed to have a second threshold voltage greater than the first threshold voltage in response to a program voltage of a second polarity, and has a second polarity It may be programmed to have a first threshold voltage from a second threshold voltage in response to a program voltage having a first polarity different from . In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, the reliability of the data storage characteristics of the storage unit 1010 may be improved. As a result, it is possible to improve the reliability of the microprocessor 1000 .

The operation unit 1020 may perform various four-ruling operations or logical operations according to the result of the control unit 1030 decoding the command. The operation unit 1020 may include one or more Arithmetic and Logic Units (ALUs).

The control unit 1030 receives a signal from the storage unit 1010 , the operation unit 1020 , an external device of the microprocessor 1000 , etc., and performs extraction or decoding of commands, control of signal input/output of the microprocessor 1000 , etc. and the processing indicated by the program can be executed.

In addition to the storage unit 1010 , the microprocessor 1000 according to the present embodiment may further include a cache memory unit 1040 capable of temporarily storing data input from or output to an external device. In this case, the cache memory unit 1040 may exchange data with the storage unit 1010 , the operation unit 1020 , and the control unit 1030 through the bus interface 1050 .

5 is an example of a configuration diagram of a processor implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 5 , the processor 1100 includes various functions in addition to the function of the microprocessor for receiving and processing data from various external devices, and then controlling and adjusting a series of processes of sending the results to the external device. Performance improvement and multi-function can be implemented. The processor 1100 may include a core unit 1110 serving as a microprocessor, a cache memory unit 1120 serving to temporarily store data, and a bus interface 1430 for data transfer between internal and external devices. can The processor 1100 may include various system on chip (SoC) such as a multi-core processor, a graphic processing unit (GPU), an application processor (AP), and the like. have.

The core unit 1110 of the present embodiment is a part that performs arithmetic and logic operations on data input from an external device, and may include a storage unit 1111 , an operation unit 1112 , and a control unit 1113 .

The storage unit 1111 is a processor register, a register, etc., and may be a part for storing data in the processor 1100, and may include a data register, an address register, a floating-point register, and the like. It can contain various registers. The storage unit 1111 may serve to temporarily store the data for which the operation unit 1112 performs the operation, the result data, and the address in which the data for the execution is stored. The operation unit 1112 is a part that performs operations inside the processor 1100 , and may perform various four-ruling operations, logical operations, etc. according to the result of the control unit 1113 decoding the command. The operation unit 1112 may include one or more Arithmetic and Logic Units (ALUs). The control unit 1113 receives a signal from the storage unit 1111, the operation unit 1112, an external device of the processor 1100, etc., and performs extraction or decoding of commands, control of signal input/output of the processor 1100, etc., The processing indicated by the program can be executed.

The cache memory unit 1120 temporarily stores data to compensate for a difference in data processing speed between the core unit 1110 operating at high speed and an external device operating at a low speed, and includes a primary storage unit 1121, It may include a secondary storage unit 1122 and a tertiary storage unit 1123 . In general, the cache memory unit 1120 includes primary and secondary storage units 1121 and 1122, and may include a tertiary storage unit 1123 when a high capacity is required, and may include more storage units if necessary. have. That is, the number of storage units included in the cache memory unit 1120 may vary according to design. Here, the processing speeds for storing and determining the data of the primary, secondary, and tertiary storage units 1121 , 1122 , and 1123 may be the same or different. When the processing speed of each storage unit is different, the speed of the primary storage unit may be the fastest. One or more storage units of the primary storage unit 1121 , the secondary storage unit 1122 , and the tertiary storage unit 1123 of the cache memory unit 1120 may include one or more of the above-described semiconductor memory embodiments. . For example, the cache memory unit 1120 includes a first conductive line, a second conductive line crossing the first conductive line, and between the first conductive line and the second conductive line, and has a chalcogenide layer and at least one threshold. a memory cell having a voltage control layer stacked thereon, wherein the chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and is programmed to have a second threshold voltage greater than the first threshold voltage in response to a second polarity program voltage; It may be programmed to have the first threshold voltage from the second threshold voltage in response to the program voltage having a first polarity different from the second polarity. In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, the reliability of the data storage characteristics of the cache memory unit 1120 may be improved. As a result, it is possible to improve the reliability of the processor 1100 .

5 illustrates a case in which the primary, secondary, and tertiary storage units 1121, 1122, and 1123 are all configured in the cache memory unit 1120, the primary, secondary, and The tertiary storage units 1121 , 1122 , and 1123 are all configured outside the core unit 1110 to compensate for a difference in processing speed between the core unit 1110 and an external device. Alternatively, the primary storage unit 1121 of the cache memory unit 1120 may be located inside the core unit 1110 , and the secondary storage unit 1122 and the tertiary storage unit 1123 may include the core unit 1110 . ), the complementary function of processing speed difference can be further strengthened. Alternatively, the primary and secondary storage units 1121 and 1122 may be located inside the core unit 1110 , and the tertiary storage unit 1123 may be located outside the core unit 1110 .

The bus interface 1430 is a part that connects the core unit 1110 , the cache memory unit 1120 , and an external device to efficiently transmit data.

The processor 1100 according to the present embodiment may include a plurality of core units 1110 , and the plurality of core units 1110 may share the cache memory unit 1120 . The plurality of core units 1110 and the cache memory unit 1120 may be directly connected or may be connected through a bus interface 1430 . All of the plurality of core units 1110 may have the same configuration as the above-described core unit. When the processor 1100 includes a plurality of core units 1110 , the primary storage unit 1121 of the cache memory unit 1120 corresponds to the number of the plurality of core units 1110 , respectively. ) and the secondary storage unit 1122 and the tertiary storage unit 1123 may be configured to be shared through the bus interface 1130 to the outside of the plurality of core units 1110 . Here, the processing speed of the primary storage unit 1121 may be faster than the processing speed of the secondary and tertiary storage units 1122 and 1123 . In another embodiment, the primary storage unit 1121 and the secondary storage unit 1122 are configured in each core unit 1110 corresponding to the number of the plurality of core units 1110 , and the tertiary storage unit 1123 . ) may be configured to be shared through the bus interface 1130 to the outside of the plurality of core units 1110 .

The processor 1100 according to this embodiment includes an embedded memory unit 1140 for storing data, a communication module unit 1150 capable of transmitting and receiving data with an external device by wire or wirelessly, and an external storage device to drive A memory control unit 1160 and a media processing unit 1170 for processing and outputting data processed by the processor 1100 or data input from an external input device to the external interface device may be additionally included. It may include modules and devices. In this case, the plurality of added modules may exchange data with the core unit 1110 and the cache memory unit 1120 through the bus interface 1130 .

Here, the embedded memory unit 1140 may include a non-volatile memory as well as a volatile memory. The volatile memory may include a dynamic random access memory (DRAM), a mobile DRAM, a static random access memory (SRAM), and a memory having a similar function, and the nonvolatile memory is a read only memory (ROM), a NOR flash memory , NAND Flash Memory, PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), STTRAM (Spin Transfer Torque Random Access Memory), MRAM (Magnetic Random Access Memory), and memory that performs similar functions. may include

The communication module unit 1150 may include a module connectable to a wired network, a module connectable to a wireless network, and all of them. Wired network module, like various devices for transmitting and receiving data through transmission line, wired LAN (Local Area Network; LAN), USB (Universal Serial Bus; USB), Ethernet (Ethernet), Power Line Communication (PLC) ) and the like. The wireless network module, like various devices that transmit and receive data without a transmission line, includes Infrared Data Association (IrDA), Code Division Multiple Access (CDMA), Time Division Multiple Access; TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth (Bluetooth), RFID (Radio Frequency IDentification) , Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High Speed Downlink Packet Access (HSDPA), Broadband Code Division It may include multiple access (Wideband CDMA; WCDMA), Ultra WideBand (UWB), and the like.

The memory control unit 1160 is for processing and managing data transmitted between the processor 1100 and an external storage device operating according to different communication standards, and various memory controllers, for example, IDE (Integrated Device Electronics), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Redundant Array of Independent Disks (RAID), Solid State Disk (SSD), External SATA (eSATA), Personal Computer Memory Card International Association (PCMCIA), USB ( Universal Serial Bus), Secure Digital Card (SD), Mini Secure Digital card (mSD), Micro Secure Digital Card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC), Embedded MMC (eMMC), Compact Flash Card (CF) ) may include a controller for controlling the

The media processing unit 1170 may process data processed by the processor 1100 or data input in the form of images, audio, and other forms from an external input device, and output the data to an external interface device. The media processing unit 1170 includes a graphics processing unit (GPU), a digital signal processing unit (DSP), a high definition audio (HD Audio), and a high definition multimedia interface (HDMI). ) may include a controller, etc.

6 is an example of a configuration diagram of a system for implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 6 , a system 1200 is a data processing device, and may perform input, processing, output, communication, storage, and the like, in order to perform a series of manipulations on data. The system 1200 may include a processor 1210 , a main memory device 1220 , an auxiliary memory device 1230 , an interface device 1240 , and the like. The system 1200 of this embodiment includes a computer, a server, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, and a mobile phone. Phone), Smart Phone, Digital Music Player, PMP (Portable Multimedia Player), Camera, Global Positioning System (GPS), Video Camera, Voice It may be various electronic systems operating using a process such as a voice recorder, telematics, an audio visual system (AV), and a smart television.

The processor 1210 may control processing such as interpretation of input commands and calculation and comparison of data stored in the system 1200, and may include a microprocessor (MPU), a central processing unit (CPU), and the like. ), a single/multi-core processor (Single/Multi Core Processor), a graphic processing unit (GPU), an application processor (AP), a digital signal processing unit (DSP), etc. can

The main memory 1220 is a storage location that can store and execute program codes or data by moving the program code or data from the auxiliary memory 1230 when the program is executed, and the stored contents can be preserved even if the power is cut off. The main memory device 1220 may include one or more of the above-described semiconductor memory embodiments. For example, the main memory device 1220 includes a first conductive line, a second conductive line intersecting the first conductive line, and between the first conductive line and the second conductive line, and has a chalcogenide layer and at least one or more threshold voltages. a memory cell having a control layer stacked thereon, wherein the chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and is programmed to have a second threshold voltage greater than the first threshold voltage in response to a program voltage of a second polarity; It may be programmed to have the first threshold voltage from the second threshold voltage in response to the program voltage having a first polarity different from the second polarity. In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, the reliability of the data storage characteristics of the main memory device 1220 may be improved. As a result, it is possible to improve the reliability of the system 1200 .

In addition, the main memory 1220 may further include a volatile memory type static random access memory (SRAM), a dynamic random access memory (DRAM), and the like in which all contents are erased when power is turned off. Unlike this, the main memory device 1220 does not include the semiconductor device of the above-described embodiment, and is a volatile memory type of static random access memory (SRAM) and dynamic random access memory (DRAM) in which all contents are erased when power is turned off. and the like.

The auxiliary storage device 1230 refers to a storage device for storing program codes or data. Although the speed is slower than the main memory 1220, it can store a lot of data. The auxiliary memory device 1230 may include one or more of the above-described semiconductor memory embodiments. For example, the auxiliary memory device 1230 includes a first conductive line, a second conductive line intersecting the first conductive line, and between the first conductive line and the second conductive line, the chalcogenide layer and at least one threshold. a memory cell having a voltage control layer stacked thereon, wherein the chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and is programmed to have a second threshold voltage greater than the first threshold voltage in response to a second polarity program voltage; It may be programmed to have the first threshold voltage from the second threshold voltage in response to the program voltage having a first polarity different from the second polarity. In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, the reliability of the data storage characteristics of the auxiliary memory device 1230 may be improved. As a result, it is possible to improve the reliability of the system 1200 .

In addition, the auxiliary storage device 1230 may include a magnetic tape using magnetism, a magnetic disk, a laser disk using light, a magneto-optical disk using these two, a solid state disk (SSD), a USB memory (Universal Serial Bus Memory; USB Memory), Secure Digital Card (SD), Mini Secure Digital card (mSD), Micro Secure Digital Card (micro SD), Secure Digital High Capacity (SDHC), Memory Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC), Embedded MMC (eMMC), Compact Flash Card (CF) It may further include a data storage system (refer to 1300 of FIG. 7 ), such as. On the contrary, the auxiliary memory 1230 does not include the semiconductor memory of the above-described embodiment, but includes a magnetic tape, a magnetic disk, a laser disk using light, a magneto-optical disk using these two, a solid state disk; SSD), USB memory (Universal Serial Bus Memory; USB Memory), secure digital card (SD), mini Secure Digital card (mSD), micro secure digital card (micro SD), high capacity secure digital Secure Digital High Capacity (SDHC), Memory Stick Card (Smart Media Card; SM), Multi Media Card (MMC), Embedded MMC (eMMC) ) and data storage systems (see 1300 of FIG. 7 ) such as a compact flash card (CF).

The interface device 1240 may be for exchanging commands and data between the system 1200 of this embodiment and an external device, and may include a keypad, a keyboard, a mouse, a speaker, and the like. It may be a microphone, a display device, various human interface devices (HID), and a communication device. The communication device may include a module capable of connecting to a wired network, a module capable of connecting to a wireless network, and all of them. Wired network module, like various devices for transmitting and receiving data through transmission line, wired LAN (Local Area Network; LAN), USB (Universal Serial Bus; USB), Ethernet (Ethernet), Power Line Communication (PLC) ) and the like, and the wireless network module, like various devices that transmit and receive data without a transmission line, are infrared communication (Infrared Data Association; IrDA), Code Division Multiple Access (CDMA), time division Time Division Multiple Access (TDMA), Frequency Division Multiple Access (FDMA), Wireless LAN, Zigbee, Ubiquitous Sensor Network (USN), Bluetooth ), RFID (Radio Frequency IDentification), Long Term Evolution (LTE), Near Field Communication (NFC), Wireless Broadband Internet (Wibro), High Speed Downlink Packet Access (HSDPA), Wideband CDMA (WCDMA), Ultra WideBand (UWB), and the like.

7 is an example of a configuration diagram of a data storage system implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 7 , the data storage system 1300 includes a storage device 1310 having a non-volatile characteristic as a configuration for data storage, a controller 1320 controlling it, an interface 1330 for connection with an external device, and a temporary storage device 1340 for temporarily storing data. The data storage system 1300 includes a disk type such as a hard disk drive (HDD), an optical drive (Compact Disc Read Only Memory; CDROM), a DVD (Digital Versatile Disc), and a solid state disk (SSD). USB Memory (Universal Serial Bus Memory; USB Memory), Secure Digital Card (SD), Mini Secure Digital card (mSD), Micro Secure Digital Card (micro SD), High Capacity Secure Digital Card (Secure) Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC), Embedded Multi Media Card (Embedded MMC; eMMC), Compact It may be in the form of a card such as a compact flash (CF).

The storage device 1310 may include a non-volatile memory for semi-permanently storing data. Here, the non-volatile memory may include read only memory (ROM), NOR flash memory, NAND flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), and the like. can

The controller 1320 may control data exchange between the storage device 1310 and the interface 1330 . To this end, the controller 1320 may include a processor 1321 that performs an operation for processing commands input through the interface 1330 from the outside of the data storage system 1300 .

The interface 1330 is for exchanging commands and data between the data storage system 1300 and an external device. When the data storage system 1300 is a card, the interface 1330 is a USB (Universal Serial Bus Memory), a secure digital card (SD), a mini secure digital card (mini Secure Digital card; mSD), and a micro secure Digital Card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card (Memory Stick Card), Smart Media Card (SM), Multi Media Card (MMC) , may be compatible with interfaces used in devices such as Embedded MMC (eMMC), Compact Flash (CF), etc., or may be compatible with interfaces used in devices similar to these devices. can When the data storage system 1300 is in the form of a disk, the interface 1330 is an IDE (Integrated Device Electronics), SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), eSATA (External SATA), PCMCIA (Personal Computer) Memory Card International Association), USB (Universal Serial Bus), etc. may be compatible, or may be compatible with an interface similar to these interfaces. Interface 1330 may be compatible with one or more interfaces of different types.

The temporary storage device 1340 may temporarily store data in order to efficiently transfer data between the interface 1330 and the storage device 1310 according to the diversification and high performance of interfaces with external devices, controllers, and systems. . The temporary storage device 1340 may include one or more of the above-described semiconductor memory embodiments. For example, the temporary storage device 1340 includes a first conductive line, a second conductive line intersecting the first conductive line, and between the first conductive line and the second conductive line, the chalcogenide layer and at least one threshold. a memory cell having a voltage control layer stacked thereon, wherein the chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and is programmed to have a second threshold voltage greater than the first threshold voltage in response to a second polarity program voltage; It may be programmed to have the first threshold voltage from the second threshold voltage in response to the program voltage having a first polarity different from the second polarity. In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, the reliability of the data storage characteristics of the temporary storage device 1340 may be improved. As a result, the reliability of the data storage system 1300 can be improved.

8 is an example of a configuration diagram of a memory system implementing a memory device according to an embodiment of the present invention.

Referring to FIG. 8 , the memory system 1400 includes a memory 1410 having non-volatile characteristics as a configuration for data storage, a memory controller 1420 for controlling it, an interface 1430 for connection with an external device, and the like. may include The memory system 1400 includes a solid state disk (SSD), a universal serial bus memory (USB Memory), a secure digital card (SD), and a mini secure digital card (mSD). , Micro Secure Digital Card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card (Memory Stick Card), Smart Media Card (SM), Multi Media Card (Multi Media Card) ; MMC), an embedded multimedia card (EMMC), a compact flash card (CF), or the like.

The memory 1410 for storing data may include one or more of the above-described semiconductor memory embodiments. For example, the memory 1410 includes a first conductive line, a second conductive line intersecting the first conductive line, and between the first conductive line and the second conductive line, and controls the chalcogenide layer and at least one or more threshold voltages. a memory cell in which the films are stacked, the chalcogenide film has a first threshold voltage in a thermal equilibrium state, and is programmed to have a second threshold voltage greater than the first threshold voltage in response to a program voltage of a second polarity; It may be programmed to have the first threshold voltage from the second threshold voltage in response to the program voltage having a first polarity different from the polarity. In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, the reliability of the data storage characteristics of the memory 1410 may be improved. As a result, the reliability of the memory system 1400 may be improved.

In addition, the memory of the present embodiment has non-volatile characteristics such as ROM (Read Only Memory), NOR Flash Memory, NAND Flash Memory, PRAM (Phase Change Random Access Memory), RRAM (Resistive Random Access Memory), MRAM (Magnetic Random Access) Memory) and the like.

The memory controller 1420 may control data exchange between the memory 1410 and the interface 1430 . To this end, the memory controller 1420 may include a processor 1421 for processing and operating commands input through the interface 1430 from the outside of the memory system 1400 .

The interface 1430 is for exchanging commands and data between the memory system 1400 and an external device, and includes a Universal Serial Bus (USB), a Secure Digital (SD) card, and a mini Secure Digital card. ; mSD), Micro Secure Digital Card (micro SD), Secure Digital High Capacity (SDHC), Memory Stick Card (Memory Stick Card), Smart Media Card (SM), Multi Media Card ( Compatible with the interface used in devices such as Multi Media Card (MMC), Embedded MMC (eMMC), Compact Flash Card (CF), etc., or in devices similar to these devices It can be compatible with the interface used. Interface 1430 may be compatible with one or more interfaces of different types.

The memory system 1400 of this embodiment is a buffer memory ( 1440) may be further included. The buffer memory 1440 for temporarily storing data may include one or more of the above-described semiconductor memory embodiments. For example, the buffer memory 1440 includes a first conductive line, a second conductive line crossing the first conductive line, and between the first conductive line and the second conductive line, the chalcogenide layer and at least one or more threshold voltages. a memory cell having a control layer stacked thereon, wherein the chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and is programmed to have a second threshold voltage greater than the first threshold voltage in response to a program voltage of a second polarity; It may be programmed to have the first threshold voltage from the second threshold voltage in response to the program voltage having a first polarity different from the second polarity. In addition, the chalcogenide layer includes the first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member decreases to a second number smaller than the first number in response to the program voltage of the second polarity, The number of the youngest electron traps may increase from the second number to the first number in response to the polarity program voltage. Through this, reliability of the data storage characteristics of the buffer memory 1440 may be improved. As a result, the reliability of the memory system 1400 may be improved.

In addition, the buffer memory 1440 of the present embodiment includes a volatile static random access memory (SRAM), a dynamic random access memory (DRAM), a nonvolatile read only memory (ROM), a NOR flash memory, and a NAND. Flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), spin transfer torque random access memory (STTRAM), magnetic random access memory (MRAM), and the like may be further included. Unlike this, the buffer memory 1440 does not include the semiconductor device of the above-described embodiment, but has a volatile SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a non-volatile ROM (Read Only). Memory), NOR Flash Memory, NAND Flash Memory, Phase Change Random Access Memory (PRAM), Resistive Random Access Memory (RRAM), Spin Transfer Torque Random Access Memory (STTRAM), Magnetic Random Access Memory (MRAM), etc. have.

Although the present invention has been described in detail with reference to a preferred embodiment, the present invention is not limited to the above embodiment, and various modifications can be made by those skilled in the art within the scope of the technical spirit of the present invention. do.

110: first conductive line 120: second conductive line
130: lower electrode 140: chalcogenide film
150: threshold voltage control film 160: upper electrode
MC: memory cell

Claims (20)

a first conductive line;
a second conductive line crossing the first conductive line; and
a memory cell positioned between the first conductive line and the second conductive line, in which a chalcogenide layer and at least one threshold voltage control layer are stacked;
The chalcogenide layer has a first threshold voltage in a thermal equilibrium state, is programmed to have a second threshold voltage greater than the first threshold voltage in response to a program voltage of a second polarity, and has a first polarity different from the second polarity An electronic device programmed to have the first threshold voltage from the second threshold voltage in response to a program voltage of According to claim 1,
The chalcogenide layer includes a first number of electron traps in the youngest in a thermal equilibrium state, and the number of the electron traps in the youngest member decreases to a second number smaller than the first number in response to a program voltage of the second polarity; The electronic device in which the number of the electron traps in the youngest member increases from the second number to the first number in response to the first polarity program voltage. According to claim 1,
The chalcogenide layer is an electronic device including a material capable of ovonic threshold switching. According to claim 1,
The chalcogenide layer includes tellurium (Te) or selenium (Se), and the threshold voltage control layer includes a metal highly reactive with tellurium (Te) or selenium (Se) among transition metals. According to claim 1,
The threshold voltage control layer includes a plurality of protons that are movable in response to the program voltage of the first polarity and the program voltage of the second polarity, and the protons include hydrogen. According to claim 1,
and wherein the threshold voltage control layer is formed in situ in the same chamber as the chalcogenide layer using a sputtering method at room temperature. According to claim 1,
The program voltage of the first polarity is a negative voltage, and the program voltage of the second polarity is a positive voltage. According to claim 1,
When the program voltage of the first polarity and the program voltage of the second polarity are applied to the first conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the first conductive line,
When the program voltage of the first polarity and the program voltage of the second polarity are applied to the second conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the second conductive line. According to claim 1,
The threshold voltage control layer is respectively inserted between the first conductive line and the chalcogenide layer and between the second conductive line and the chalcogenide layer. a first conductive line;
a second conductive line crossing the first conductive line; and
a memory cell positioned between the first conductive line and the second conductive line, in which a chalcogenide layer containing tellurium (Te) or selenium (Se) and at least one threshold voltage control layer are stacked;
An electronic device in which a reactive layer is generated or destroyed between the chalcogenide layer and the threshold voltage control layer in response to a program voltage applied to the memory cell. 11. The method of claim 10,
The chalcogenide layer has a first threshold voltage in a thermal equilibrium state, the reaction layer is generated in response to a positive program voltage applied to the memory cell, and is programmed to have a second threshold voltage greater than the first threshold voltage; The electronic device is programmed to have the first threshold voltage from the second threshold voltage by dissipating the reactive layer in response to a negative program voltage applied to the memory cell. 11. The method of claim 10,
The chalcogenide layer includes a first number of electron traps in the youngest member in a thermal equilibrium state, and the number of electron traps in the youngest member is smaller than the first number while the reaction layer is generated in response to a positive program voltage applied to the memory cell. The electronic device decreases to a second number, and increases from the second number to the first number as the reaction layer disappears in response to the negative program voltage applied to the memory cell. 11. The method of claim 10,
The reaction layer includes telluride or selenide generated by reacting tellurium (Te) or selenium (Se) of the chalcogenide layer and the threshold voltage control layer. 11. The method of claim 10,
The threshold voltage control layer includes any one selected from the group consisting of titanium (Ti), zirconium (Zr), and hafnium (Hf). 11. The method of claim 10,
When the program voltage is applied to the first conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the first conductive line,
When the program voltage is applied to the second conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the second conductive line. a first conductive line;
a second conductive line crossing the first conductive line; and
A memory cell positioned between the first conductive line and the second conductive line, in which a chalcogenide layer including a plurality of electron traps in a youngest member and at least one threshold voltage control layer including a proton in the youngest are stacked;
The chalcogenide layer includes a first number of electron traps in the youngest in a thermal equilibrium state, and in response to a positive program voltage applied to the memory cell, protons of the threshold voltage control layer are injected into the chalcogenide layer, and the electrons in the youngest The number of traps decreases to a second number smaller than the first number, and the protons injected into the chalcogenide layer in response to a negative program voltage applied to the memory cell are injected into the threshold voltage control layer, An electronic device in which the number of electronic traps increases from the second number to the first number. 17. The method of claim 16,
The chalcogenide layer has a first threshold voltage in a thermal equilibrium state, and the mobile protons of the proton storage layer are injected into the chalcogenide layer in response to a positive program voltage applied to the memory cell, which is greater than the first threshold voltage. The mobile protons programmed to have a second threshold voltage and injected into the chalcogenide layer in response to a negative program voltage applied to the memory cell are injected into the proton storage layer to increase the first threshold voltage from the second threshold voltage. An electronic device programmed to have. 17. The method of claim 16,
The chalcogenide layer is an electronic device including a material capable of ovonic threshold switching. 17. The method of claim 16,
The proton includes hydrogen, and the threshold voltage control layer includes a silicon oxide layer containing hydrogen. According to claim 1,
When the positive program voltage and the negative program voltage are applied to the first conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the first conductive line;
When the positive program voltage and the negative program voltage are applied to the second conductive line, the threshold voltage control layer is inserted between the chalcogenide layer and the second conductive line.

Images