CN112242302B - Transient suppression diode and method of manufacturing the same - Google Patents
Transient suppression diode and method of manufacturing the same Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66136—PN junction diodes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
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Abstract
A transient suppression diode and a manufacturing method thereof are provided, wherein the method comprises providing a substrate and defining a chip region; and forming a graphical barrier layer on the surface of the substrate in the chip area, wherein the graphical barrier layer is in a closed ring shape with axial symmetry, and the graphical barrier layer is used as a mask to diffuse the substrate to form a PN junction. The diffusion can be blocked at the position of the patterned barrier layer, so that two adjacent diffusion regions can only be communicated at the bottom of the patterned barrier layer region by diffusing through a diffusion window formed by the patterned barrier layer, the interface of the PN junction manufactured by the diffusion method is a continuous curved surface, namely the PN junction is a non-planar junction and has multiple radians, and the actual effective junction area of the PN junction is increased.
Description
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a transient suppression diode and a manufacturing method thereof.
Background
Transient interference of voltage and current is a main cause of damage to electronic circuits and devices, and often brings immeasurable loss to people. These disturbances usually come from start-stop operation of power equipment, instability of an alternating current power grid, lightning stroke disturbance, electrostatic discharge and the like, and transient disturbance is almost ubiquitous and untimely, so that people feel impossible to prevent. Therefore, a high performance TVS (transient Voltage suppressor), which is a PN junction semiconductor diode device formed by silicon through a diffusion process, is proposed to effectively suppress the transient interference. When two poles of the TVS are impacted by reverse transient high energy, the TVS can change the high impedance between the two poles into low impedance in the time of 10-12s magnitude, so as to absorb the surge power of thousands of watts, clamp the voltage between the two poles at a preset value, effectively protect precise components in an electronic circuit and prevent the precise components from being damaged by various surge pulses and static electricity. The TVS includes a Unidirectional (Unidirectional) TVS and a Bi-directional (Bi-directional) TVS. The bidirectional TVS is formed by reversely connecting two unidirectional TVSs in series, and the device can be well protected no matter surge pulse and static electricity impact from the positive direction or the reverse direction when in use.
In the application process, a TVS with higher power is often needed, but in the current manufacturing process of the PN junction semiconductor diode device, manufacturing the TVS with higher power means that a semiconductor chip with a larger size is needed, so that the volume of the transient voltage suppression diode device is increased, and the manufacturing cost is increased.
Disclosure of Invention
The invention provides a transient suppression diode and a manufacturing method thereof, which can achieve the same power, and meanwhile, the volume of the transient suppression diode is smaller, and the manufacturing cost is reduced.
According to a first aspect, an embodiment provides a method of manufacturing a transient suppression diode, comprising:
providing a substrate and defining a chip area, wherein the substrate is made of a first doping type material, and the first doping type is a P-type semiconductor or an N-type semiconductor;
forming a patterned blocking layer higher than the surface of the substrate on the surface of the substrate in the chip area, wherein the patterned blocking layer is a plurality of concentric circular rings or square rings;
performing a second doping type diffusion process on the substrate by taking the patterned barrier layer as a mask to form a second doping type diffusion region in the substrate, wherein a PN junction is formed between the diffusion region and the first doping type substrate and is a plurality of continuously fluctuating curved surfaces, the second doping type is correspondingly an N-type semiconductor or a P-type semiconductor, and the width of a single-layer ring in the patterned barrier layer is less than one half of the diffusion depth;
and covering the outer surface of the substrate of the first doping type and the outer surface of the diffusion region with metal layers respectively to form electrodes.
In some embodiments, the patterned barrier layer is an axisymmetric pattern.
In some embodiments, the distance between the patterned barrier layers on two adjacent chip regions is greater than or equal to the notch width of the defined isolation trench.
In some embodiments, the radial distance between two concentric rings in close proximity is greater than the diffusion depth within the same die region.
In some embodiments, the patterned barrier layer has a thickness greater than or equal to 13.5K a.
In some embodiments, the material of the patterned barrier layer is silicon dioxide.
In some embodiments, after the diffusing the substrate with the patterned blocking layer as a mask to form a PN junction, the method further includes: and removing the patterned barrier layer by using hydrofluoric acid.
In some embodiments, after or before removing the patterned barrier layer using hydrofluoric acid, further comprising:
defining an isolation region between two adjacent chip regions;
manufacturing an isolation groove in the isolation region by a chemical corrosion grooving mode, wherein a first diffusion region is arranged on the periphery of the isolation groove;
and passivating the isolation groove by using an insulating material on the surface of the isolation groove.
According to a second aspect, an embodiment provides a structure of a transient suppression diode, including: the substrate is made of a first doping type material, and the first doping type is a P-type semiconductor or an N-type semiconductor;
forming a diffusion region of a second doping type in the substrate, wherein the second doping type is an N-type semiconductor or a P-type semiconductor correspondingly;
a PN junction is formed between the diffusion region and the substrate of the first doping type, and the PN junction is a continuously fluctuant curved surface;
and electrode layers respectively on the outer surface of the first doping type substrate and the outer surface of the diffusion region.
In some embodiments, the diffusion region includes a first diffusion region and a second diffusion region, the first diffusion region is located in a part of the diffusion region at the bottom of the patterned barrier layer, the second diffusion region is located in a part of the diffusion region at the bottom of the patterned barrier layer, and the diffusion concentration of the first diffusion region is lower than that of the second diffusion region; an isolation groove is arranged between the adjacent chip areas, and the outer side of the isolation groove surrounds the first diffusion area.
According to the manufacturing method and the structure of the transient suppression diode of the embodiment, the patterned barrier layer is formed on the surface of the substrate in the chip area, then the substrate is diffused to form the PN junction, because the patterned barrier layer can block diffusion, the diffusion window formed by the patterned barrier layer is diffused to ensure that two adjacent diffusion areas can only be communicated at the bottom of the patterned barrier layer area, when the patterned barrier layer is a plurality of concentric circular rings or square rings, the contact surface of the manufactured PN junction is not a planar junction but a plurality of continuously fluctuating curved surfaces, namely, the PN junction is provided with a plurality of continuously fluctuating curved surfaces, and the contact surface of the PN junction is changed into a plurality of fluctuating curved surfaces from the original plane, so that the contact area is increased, and the effective contact area of the PN junction is increased in the chip with the same area, the transient suppression diode can achieve higher power, so that under the condition of manufacturing the transient suppression diode with the same power, the transient suppression diode is more excellent in electrical property, the size of the device is smaller, and the manufacturing cost is effectively reduced.
Drawings
Fig. 1 is a flowchart of a method for manufacturing a transient suppression diode according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a part of a transient suppression diode in a manufacturing process according to an embodiment of the invention;
fig. 3 is a schematic partial cross-sectional view of a transient suppression diode according to fig. 2 during fabrication;
fig. 4 is a schematic structural diagram of a portion of a transient suppression diode in a manufacturing process according to an embodiment of the invention;
fig. 5 is a schematic partial cross-sectional view of the transient suppression diode shown in fig. 4 during fabrication;
fig. 6 is a schematic diagram illustrating a passivation layer structure formed in a manufacturing process of a transient suppression diode according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
As can be seen from the background art, the current tvs device has a large size, which is not only disadvantageous for packaging but also increases the manufacturing cost.
The research shows that when the effective contact area of the PN junction in the chip is larger, the current which can pass through the chip is larger, that is, the power is larger, so that if the effective contact area of the PN junction in the chip can be increased, the power of the transient suppression diode can be increased, that is, the electrical performance of the transient suppression diode can be improved.
In the embodiment of the invention, a manufacturing method of a transient suppression diode and the transient suppression diode formed by the method are provided, a patterned barrier layer is formed on the surface of a substrate in a chip area, then the substrate is diffused to form a PN junction, the patterned barrier layer can block diffusion, impurity atoms can diffuse along the transverse direction and the longitudinal direction, therefore, diffusion is carried out through a diffusion window formed by the patterned barrier layer, so that two adjacent diffusion areas can be communicated at the bottom of the patterned barrier layer area, and the contact surface of the PN junction obtained by the diffusion method is a non-planar junction and has a plurality of radians, so that the actual area of the contact surface of the PN junction is increased, and the larger the junction area of the PN junction in a chip with the same area is, the larger the current can pass, therefore, the transient suppression diode has more excellent electrical performance and simultaneously reduces the cost.
Fig. 1 is a schematic flow chart of a method for manufacturing a transient suppression diode according to an embodiment of the present invention, please refer to fig. 1, which includes:
The substrate is made of a first doping type material, and the first doping type is a P-type semiconductor or an N-type semiconductor. For example, the substrate 100 may be a P-type substrate or an N-type substrate.
For example, an N-type substrate, the substrate doping impurity may be arsenic or phosphorus, and the concentration may be 3ohm cm, and the doping impurity of the second doping type implanted thereto is a P-type material, and may be boron, and the concentration may be 0.2ohm cm.
It should be noted that after the substrate 100 is provided, the surface thereof needs to be subjected to a cleaning process, and in this embodiment, the cleaning process includes: washing with 5 + -1% HF, 5 + -1% HCl and the rest reverse osmosis water at room temperature for 5-6 min. After cleaning, low-temperature drying is needed, specifically, drying with hot air at 60 ± 5 ℃ for about 20 minutes.
Fig. 2 is a schematic structural diagram of a part of a manufacturing process of a transient suppression diode according to an embodiment of the present invention. Fig. 3 is a schematic partial cross-sectional view of the transient suppression diode shown in fig. 2 during fabrication. Referring to fig. 2 and 3, a chip region 101 is defined on a substrate 100, the substrate 100 has a plurality of chip regions 101, and an isolation trench needs to be formed between adjacent chip regions 101, so that during the fabrication of the transient suppression diode, the chip region 101 is defined and an isolation region 102 is also defined at the same time, so as to form an isolation trench at the location of the isolation region 102. Increasing the effective contact area of the PN junction in the chip region 101 may improve the electrical performance of the transient suppression diode.
And 2, forming a patterned barrier layer 200 higher than the surface of the substrate on the surface of the substrate 100 in the chip region 101, wherein the patterned barrier layer 200 is in a closed ring shape with axial symmetry.
With continued reference to fig. 2 and fig. 3, in the present embodiment, the material of the patterned blocking layer 200 is silicon dioxide.
In this embodiment, the patterned blocking layer 200 may be formed by oxidizing the surface of the substrate 100 by an oxidation process (generally, the depth of oxidizing the substrate once is about 13.5K a), oxidizing a predetermined thickness of the surface of the substrate to silicon dioxide, that is, obtaining a silicon dioxide layer with the predetermined thickness, and then etching the silicon dioxide layer through a first patterned mask having a pattern of the patterned blocking layer 200 to expose the original substrate material, that is, the etching depth is equal to the predetermined thickness, so as to transfer the pattern of the first patterned mask to the silicon dioxide layer, that is, to form the patterned blocking layer 200 with the predetermined thickness. The patterned barrier layer 200 prepared by the method is high in speed and uniform in stress, and the stability of the device can be guaranteed.
It should be noted that the thicker the patterned barrier layer 200 is, that is, the deeper the oxidation depth when forming silicon dioxide by oxidation, the better the effect of blocking diffusion is achieved, and in this embodiment, the thickness of the patterned barrier layer 200 is greater than or equal to 13.5K a. Then, it is known that when the surface of the substrate 100 is subjected to the oxidation process as described above, the thickness to be oxidized needs to be greater than or equal to 13.5K a, then when the pattern of the first patterned mask is transferred onto the silicon dioxide layer, the etch depth to the silicon dioxide layer also needs to exceed 13.5K a.
In other embodiments, the method for forming the image blocking layer 200 may also be: a protective layer (silicon dioxide) covering the surface of the substrate 100 is deposited on the surface of the substrate 100, and then the protective layer is etched through a first patterned mask having a patterned barrier layer 200, so that the pattern of the first patterned mask is transferred to the protective layer (silicon dioxide layer).
In the above, the pattern of the patterned blocking layer 200 is an axisymmetric closed ring, which is intended to ensure the balance around the surface of the substrate 100, and also to ensure the uniformity of PN junction contact stress and current after subsequent diffusion, so as to ensure the performance of the formed transient suppression diode.
The patterned blocking layer 200 is a plurality of concentric circular rings or square rings, and the larger the number of concentric rings, the larger the effective contact area of the formed PN junction after subsequent diffusion.
As in the embodiment provided in fig. 2, the patterned barrier layer 200 is a two-layer concentric square ring.
In other embodiments, the number of rings in the patterned barrier layer 200 may be selected according to requirements, for example, in some embodiments, the number of rings in the patterned barrier layer 200 may also be 1 layer, 3 layers, 4 layers, or other layers.
And 3, diffusing the substrate 100 by taking the patterned barrier layer 200 as a mask to form a PN junction.
Referring to fig. 5, with the patterned blocking layer 200 as a mask, a second doping type diffusion process is performed on the substrate 100, so that a second doping type diffusion region 300 is formed in the substrate 100, and PN junctions are formed between the diffusion region 300 and the first doping type substrate, and the PN junctions are a plurality of continuously undulating curved surfaces.
In this embodiment, the diffusion process may specifically include: the heating temperature is 1100-1270 deg.C, the heating time is 15-60 hours above, and the depth of the P-type impurity atoms and the N-type impurity atoms from the surface of the semiconductor substrate 100 reaches 30 microns above.
In other embodiments, the substrate 100 may be doped by ion implantation, so that the diffusion region 300 of the second doping type is formed in the substrate 100 to form a PN junction.
It should be noted that the second doping type is an N-type semiconductor or a P-type semiconductor, for example, when a P-type substrate is provided, the impurity source of the diffusion process should be N-type when the diffusion region 300 is formed; if an N-type substrate is provided, the impurity source of the diffusion process should be selected to be P-type when forming the diffusion region 300.
In this embodiment, an N-type substrate is selected, and thus, the impurity source of the diffusion process when forming the diffusion region 300 is correspondingly P-type.
After the patterned barrier layer 200 is formed on the N-type substrate, it can be understood that the diffusion window 201 is formed, i.e., the position not blocked by the patterned barrier layer 200 is regarded as a diffusion window that can be directly diffused from the substrate surface.
Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view of the substrate in fig. 4 after the diffusion process, due to the patterned barrier layer 200, the patterned barrier layer 200 is located at a position where the diffusion impurity source is prevented from directly diffusing from the surface of the substrate to the inside, that is, the diffusion impurity source can only diffuse to the inside of the substrate through the diffusion window 201, that is, to the periphery (directly below the barrier layer 200) directly below and under the diffusion window 201, so that the diffusion depth directly under the diffusion window 201 is deep, the diffusion depth directly under the barrier layer 200 is shallow, and the further away from the diffusion window 201, the shallower the diffusion depth is, so as to form a curved surface. When the thickness and/or height of the patterned barrier layer 200 is appropriate, or the diffusion time is long enough, the diffusion layer formed by two adjacent diffusion windows can penetrate through the bottom of the patterned barrier layer 200 region, so as to form a continuous PN junction inside the chip substrate, the contact surface of the PN junction manufactured by the diffusion method, that is, the interface of the PN junction is curved, and completely different from the shape of a conventional planar junction, the formed PN junction is a non-planar junction and has a plurality of radians (similar to waves), as can be seen from the cross-sectional view of fig. 5, the portion of the diffusion region 300 corresponding to the bottom of the patterned barrier layer 200 is a first diffusion region, the cross-sectional length of the first diffusion region is changed from the conventional single side b to two sides 2a, and the effective contact surface of the formed PN junction is obviously increased. Because the larger the effective contact area of the PN junction is, the larger the current can pass, the scheme of the application increases the effective area of the PN junction on the basis of not increasing the area of a single chip, thereby solving the contradiction that the area of the single chip is required to be reduced and the area of the PN junction is required to be increased in practical application, and compared with the chip with the same area, the transient suppression diode formed by the manufacturing method provided by the application has better electrical performance.
It should be noted that the width of each barrier ring (e.g., the cross-sectional width of the square barrier ring shown in the figure) in the patterned barrier layer 200 needs to be designed according to the subsequent diffusion depth to ensure that the PN junctions in the chip region 101 can communicate with each other inside the substrate.
The width of the ring of the patterned blocking layer 200 needs to be less than 2 times of diffusion depth (junction depth), that is, the width of each blocking ring in the patterned blocking layer 200 is less than two junction depths, so as to ensure that the substrate at the bottom of the patterned blocking layer 200 can be laterally extended, that is, the diffusion layers are communicated inside the substrate, so as to ensure the current stability of the formed PN junction.
In this embodiment, the distance between the patterned barrier layers 200 on two adjacent chip regions 101 should also be greater than or equal to the width of the notch of the defined isolation region 102 (isolation trench).
It should be noted that, in the same chip region 101, if the patterned blocking layer 200 is a multi-layer concentric ring structure, for example, a structure having two concentric ring layers, i.e., a first blocking ring on the inner layer and a second blocking ring on the outer layer, respectively, the length difference between the radius of the first blocking ring and the radius of the second blocking ring should also be greater than the diffusion depth, so as to ensure the effectiveness of the process of the fabricated transient suppression diode.
After the step 3, the method further comprises the following steps: the patterned barrier layer 200 is removed.
In this embodiment, the patterned barrier layer 200 is removed by using hydrofluoric acid, that is, the silicon dioxide barrier layer is removed by using hydrofluoric acid.
In some embodiments, an isolation trench may need to be etched after or before the patterned barrier layer 200 is removed using hydrofluoric acid.
Specifically, after the patterned barrier layer 200 is removed, the isolation trench may be etched.
In the present embodiment, at the defined isolation region 102, an isolation trench is formed in the isolation region by using a chemical etching trenching method.
It should be noted that a defined isolation region 102 is generally defined between two adjacent chip regions 101, a recessed isolation trench is formed at this position by wet etching, and the etched depth is necessarily greater than the diffusion depth to ensure insulation between two chips.
Referring to fig. 6, after the isolation trench is formed, the isolation trench is passivated with an insulating material 400 on the surface of the isolation trench.
The insulating material 400 used in this embodiment is glass frit.
Corresponding to fig. 5, it can be seen that, in the process of manufacturing the isolation trench, the patterned barrier layer 200 is respectively disposed on two sides of the isolation trench, the diffusion ions at the bottom of the patterned barrier layer 200 are the first diffusion regions C, and the first diffusion regions C are regions where two directions meet when the diffusion process laterally diffuses along diffusion windows on two sides of the first diffusion regions C, so that the diffusion concentration at the position of the first diffusion region C is lower than that of the peripheral region, and the first diffusion regions C surround the isolation trench for one circle, that is, the first diffusion regions C with lower concentration are all formed for one circle of the isolation trench, so that the breakdown voltage at this position is higher than that of the peripheral region, and thus the first diffusion regions can function as guard rings, that is, can function to prevent the isolation trench region from being broken down. Therefore, the electrical performance of the formed transient suppression diode is further improved.
And 4, covering metal layers on the outer surface of the substrate of the first doping type and the outer surface of the diffusion region respectively to form electrodes.
When the unidirectional TVS is to be formed, the outer surface of the substrate of the first doping type and the outer surface of the diffusion region can be respectively arranged on two sides of the device, or can be arranged on the same side of the device; when the bidirectional TVS is to be formed, the bidirectional TVS is formed by reversely connecting two unidirectional TVSs in series, namely, electrodes are respectively formed on two sides of the TVS, and the electrodes are respectively formed on diffusion regions on two sides of the TVS.
The present embodiment further provides a transient suppression diode manufactured by the above manufacturing method, please refer to fig. 6, wherein the transient suppression diode includes a substrate 100, a diffusion region 300 in the substrate, a PN junction formed between the diffusion region 300 and the substrate 100, and an electrode layer (not shown), the substrate 100 is made of a first doping type material, and the first doping type is a P-type semiconductor or an N-type semiconductor; the diffusion region 300 is formed in the substrate and is of a second doping type, wherein the second doping type is an N-type semiconductor or a P-type semiconductor, respectively; the PN junction is formed between the diffusion region and the substrate of the first doping type, the interface of the PN junction is a continuous curved surface, and the electrode layers can be respectively formed on the outer surface of the substrate of the first doping type or the outer surface of the diffusion region.
In this embodiment, the diffusion region 300 includes a first diffusion region C and a second diffusion region, the first diffusion region C is located in the partial diffusion region 300 at the bottom of the patterned barrier layer, the second diffusion region is located in the partial diffusion region 300 at the bottom of the patterned barrier layer, and the diffusion concentration of the first diffusion region is lower than that of the second diffusion region; an isolation groove (isolation region 102) is arranged between adjacent chip regions, and the outer side of the isolation groove (isolation region 102) surrounds the first diffusion region C.
The section of the PN junction contact surface of the fabricated transient suppression diode is a non-planar junction, and the inside of the PN junction contact surface is provided with a plurality of radians (similar to waves), for example, in the cross-sectional view shown in fig. 5, when a ring (silicon dioxide blocking ring) is added in the graph of the patterned blocking layer 200, the section length of the PN junction corresponding to the bottom of the patterned blocking layer is changed from a traditional single edge (length b) to two edges (length 2 a), and the effective contact surface of the formed PN junction is obviously increased. Therefore, a device through which a current with larger current flows can be manufactured on a chip with a fixed area, and the power of the transient suppression diode is effectively improved; furthermore, the patterned barrier layer 200 may further form a first diffusion region C around the isolation trench, where the first diffusion region C corresponds to a guard ring, and the first diffusion region C is a region where two directions meet when the diffusion process laterally diffuses along diffusion windows on two sides of the first diffusion region C, so that the diffusion concentration at the position of the first diffusion region C is lower than that of the peripheral region, and the first diffusion region C surrounds the isolation trench for one circle, that is, the isolation trench for one circle is the first diffusion region C with lower concentration, so that the breakdown voltage at this position is higher than that of the peripheral region, and thus, the first diffusion region may function as a guard ring to prevent the isolation trench region from being broken down. Thus, the electrical properties of the formed device are further improved.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (9)
1. A method of manufacturing a transient suppression diode, comprising:
providing a substrate and defining a chip area, wherein the substrate is made of a first doping type material, and the first doping type is a P-type semiconductor or an N-type semiconductor;
forming a patterned blocking layer higher than the surface of the substrate on the surface of the substrate in the chip area, wherein the patterned blocking layer is a plurality of concentric circular rings or square rings;
performing a second doping type diffusion process on the substrate by taking the patterned barrier layer as a mask, wherein in the patterned barrier layer, the width of the single-layer ring is less than one half of the diffusion depth; forming a diffusion region of a second doping type in the substrate, forming PN junctions between the diffusion region and the substrate of the first doping type, wherein the PN junctions are a plurality of continuously fluctuating curved surfaces, and the second doping type is correspondingly an N-type semiconductor or a P-type semiconductor;
and covering the outer surface of the substrate of the first doping type and the outer surface of the diffusion region with metal layers respectively to form electrodes.
2. The method of manufacturing of claim 1, wherein the patterned barrier layer is an axisymmetric pattern.
3. The method of manufacturing of claim 1, wherein a distance between the patterned barrier layers on two adjacent chip regions is greater than or equal to a notch diameter of the defined isolation trench.
4. The method of claim 1, wherein a radial distance between two adjacent concentric rings is greater than a diffusion depth within the same chip region.
5. The method of manufacturing of claim 1, wherein the patterned barrier layer has a thickness greater than or equal to 13.5K a.
6. The method of claim 1, wherein the patterned barrier layer is formed of silicon dioxide.
7. The method of manufacturing according to claim 1, wherein after the diffusing the substrate with the patterned barrier layer as a mask to form a PN junction, further comprising: and removing the patterned barrier layer by using hydrofluoric acid.
8. The method of manufacturing of claim 7, further comprising, after or before removing the patterned barrier layer using hydrofluoric acid:
defining an isolation region between two adjacent chip regions;
manufacturing an isolation groove in the isolation region by a chemical corrosion grooving mode, wherein a first diffusion region is arranged on the periphery of the isolation groove;
and passivating the isolation groove by using an insulating material on the surface of the isolation groove.
9. A transient suppression diode, comprising:
the substrate is made of a first doping type material, and the first doping type is a P-type semiconductor or an N-type semiconductor;
forming a diffusion region of a second doping type in the substrate, wherein the diffusion region is formed by performing a diffusion process of the second doping type on the substrate by taking a patterned barrier layer as a mask, the patterned barrier layer is a plurality of concentric circular rings or square rings, and the width of a single-layer ring in the patterned barrier is less than one half of the diffusion depth; the second doping type is correspondingly an N-type semiconductor or a P-type semiconductor;
the PN junction is formed between the diffusion region and the substrate of the first doping type, the PN junction is a plurality of continuously fluctuating curved surfaces, the diffusion region comprises a first diffusion region and a second diffusion region, the first diffusion region is located in a partial diffusion region at the bottom of the patterned blocking layer, the second diffusion region is located in a partial diffusion region at the bottom of the patterned blocking layer, and the diffusion concentration of the first diffusion region is lower than that of the second diffusion region; an isolation groove is arranged between adjacent chip areas, and the outer side of the isolation groove surrounds the first diffusion area;
and electrode layers respectively on the outer surface of the first doping type substrate and the outer surface of the diffusion region.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870078A (en) * | 2016-06-12 | 2016-08-17 | 浙江明德微电子股份有限公司 | Chip structure for effectively increasing PN junction area and manufacturing method thereof |
| CN107425047A (en) * | 2017-03-02 | 2017-12-01 | 深圳傲威半导体有限公司 | A kind of TVS diode PN junction structure |
| CN210956686U (en) * | 2019-12-20 | 2020-07-07 | 力特半导体（无锡）有限公司 | Transient voltage suppression diode |
| CN112071753A (en) * | 2020-09-10 | 2020-12-11 | 深圳市槟城电子有限公司 | Electronic component and preparation method thereof |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870078A (en) * | 2016-06-12 | 2016-08-17 | 浙江明德微电子股份有限公司 | Chip structure for effectively increasing PN junction area and manufacturing method thereof |
| CN107425047A (en) * | 2017-03-02 | 2017-12-01 | 深圳傲威半导体有限公司 | A kind of TVS diode PN junction structure |
| CN210956686U (en) * | 2019-12-20 | 2020-07-07 | 力特半导体（无锡）有限公司 | Transient voltage suppression diode |
| CN112071753A (en) * | 2020-09-10 | 2020-12-11 | 深圳市槟城电子有限公司 | Electronic component and preparation method thereof |
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