CN102263105B - Trench semiconductor component and manufacturing method - Google Patents
Trench semiconductor component and manufacturing method Download PDFInfo
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- CN102263105B CN102263105B CN 201010186803 CN201010186803A CN102263105B CN 102263105 B CN102263105 B CN 102263105B CN 201010186803 CN201010186803 CN 201010186803 CN 201010186803 A CN201010186803 A CN 201010186803A CN 102263105 B CN102263105 B CN 102263105B
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Abstract
The invention discloses a trench semiconductor component and a manufacturing method. The trench semiconductor component comprises a trench metal oxide semiconductor transistor component and a trench electrostatic protection component, wherein the trench electrostatic protection component is electrically connected between the gate and source of the trench metal oxide semiconductor transistor component to provide high electrostatic protection capability. The manufacturing of the trench electrostatic protection component is integrated in the trench metal oxide semiconductor transistor component, so the position of the doped region of the trench electrostatic protection component is not required to be defined by utilizing an additional photomask, and the advantages of process simplicity and low cost are further achieved.
Description
Technical field
The present invention is about a kind of trench semiconductor component and preparation method thereof, espespecially a kind of trench semiconductor component with ditching type metal oxide semi conductor transistor assembly and ditching type electrostatic defending assembly and preparation method thereof.
Background technology
Therefore power MOS transistor (Power MOS transistor) assembly especially easily is subject to the injury of electrostatic discharge pulses (ESD pulse) owing to having the on state characteristic of high voltage and high current.Particularly since integrated circuit technology now in order to obtain to hang down starting voltage, the in addition thinning of the thickness of the grid oxic horizon of power MOS transistor assembly, under this required, it is impaired that the power MOS transistor assembly very easily is subject to the injury of the electrostatic discharge pulses that produces because of friction or other uncontrollable factor.Therefore, in the application of power MOS transistor assembly, the use of the electrostatic discharge protection circuit of must arranging in pairs or groups is to avoid the power MOS transistor assembly impaired.In existing power MOS transistor component technology, normally after the power MOS transistor establishment of component is finished, carry out again the making of electrostatic discharge protection circuit, yet this practice can increase extra technique and cost.
In addition, United States Patent (USP) the 7th, 205, No. 196 patents, disclosed a kind of method of making power MOS transistor assembly and electrostatic defending assembly, according to its instruction, the making of electrostatic defending assembly is to be integrated in the technique of power MOS transistor assembly, yet therefore the pattern that it must utilize together extra light shield definition polysilicon layer can cause the increase of process complexity and cost.
Summary of the invention
One of purpose of the present invention is to provide a kind of trench semiconductor component and preparation method thereof, with the complex process of solution known technology and expensive shortcoming.
For reaching above-mentioned purpose, the invention provides a kind of trench semiconductor component.Above-mentioned trench semiconductor component comprises:
The semiconductor substrate, it is characterized in that, comprise a upper surface and a lower surface, definition has one first assembly district and one second assembly district on the described semiconductor base, and the described upper surface of described semiconductor base comprises that at least one the first irrigation canals and ditches are positioned within described the first assembly district, and at least one the second irrigation canals and ditches are positioned within described the second assembly district;
At least one ditching type metal oxide semi conductor transistor assembly is arranged in described the first assembly district, and wherein said ditching type metal oxide semi conductor transistor assembly comprises:
One dielectric layer is positioned at the sidewall of described the first irrigation canals and ditches;
One grid is positioned within described the first irrigation canals and ditches;
One matrix doped region is positioned at the described semiconductor base of a side of described the first irrigation canals and ditches;
One source pole is positioned at the described upper surface of described semiconductor base and is electrically connected with described matrix doped region; And
One drains, and is positioned at the described lower surface of described semiconductor base;
One ditching type electrostatic defending assembly, be arranged within described second irrigation canals and ditches in described the second assembly district, described ditching type electrostatic defending assembly comprises one first doped region and one second doped region, wherein said the first doped region has one first doping type, described the second doped region has one second doping type, and described the first doped region has different doping types from described the second doped region:
And
One grid lead is arranged at the described upper surface of described semiconductor base, wherein said grid lead respectively with the described grid of described ditching type metal oxide semi conductor transistor assembly, and
Described second doped region of described ditching type electrostatic defending assembly is electrically connected.
For reaching above-mentioned purpose, the present invention provides a kind of method of making trench semiconductor component in addition.Said method comprises the following steps:
The semiconductor substrate is provided, definition has one first assembly district and one second assembly district on the described semiconductor base, and a upper surface of described semiconductor base has at least one the first irrigation canals and ditches and is positioned within described the first assembly district, and at least one the second irrigation canals and ditches are positioned within described the second assembly district;
In described first irrigation canals and ditches in described the first assembly district, form a ditching type metal oxide semi conductor transistor assembly, and in described second irrigation canals and ditches in described the second assembly district, form a ditching type electrostatic defending assembly, wherein said ditching type metal oxide semi conductor transistor assembly comprises a grid, be positioned within described the first irrigation canals and ditches, an and matrix doped region, be positioned at the described semiconductor base of a side of described the first irrigation canals and ditches, and described ditching type electrostatic defending assembly comprises one first doped region and one second doped region, and described the first doped region has different doping types from described the second doped region; And
Described upper surface in described semiconductor base forms a grid lead and one source pole, wherein said grid lead is electrically connected with described second doped region of described ditching type electrostatic defending assembly and the described grid of described ditching type metal oxide semi conductor transistor assembly respectively, and described source electrode and the electric connection of described matrix doped region.
For reaching above-mentioned purpose, the present invention more provides a kind of method of making trench semiconductor component.Said method comprises the following steps:
The semiconductor substrate is provided, definition has one first assembly district and one second assembly district on the described semiconductor base, and a upper surface of described semiconductor base has at least one the first irrigation canals and ditches and is positioned within described the first assembly district, and at least one the second irrigation canals and ditches are positioned within described the second assembly district;
Inwall in described the first irrigation canals and ditches and described the second irrigation canals and ditches forms a dielectric layer;
Form a doping semiconductor layer within described the first irrigation canals and ditches and described the second irrigation canals and ditches, wherein said doping semiconductor layer has one first doping type;
Form a matrix doped region in the described semiconductor base in described the first assembly district, wherein said matrix doped region has described the first doping type;
Form a mask pattern in the surface of described semiconductor base and described doping semiconductor layer, the described doping semiconductor layer in described the second irrigation canals and ditches of wherein said mask pattern partial coverage;
Carry out an Implantation, change not the doping type of the described doping semiconductor layer in described the second irrigation canals and ditches that covered by described mask pattern, so that the described doping semiconductor layer that is covered by described mask pattern forms one first doped region, and make and be positioned at the described doping semiconductor layer that described the first doped region two sides do not cover by described mask pattern and form respectively one second doped region and one the 3rd doped region, wherein said the second doped region and described the 3rd doped region have one second doping type;
Form an insulating barrier in the surface of described semiconductor base, wherein said insulating barrier exposes described the second doped region and described the 3rd doped region in described the second irrigation canals and ditches; And
On described semiconductor base, form a grid lead and one source pole, wherein said grid lead respectively with described the second irrigation canals and ditches in described the second doped region, and be electrically connected with described doping semiconductor layer in described the first irrigation canals and ditches, and described source electrode and the electric connection of described matrix doped region.
Therefore the making of ditching type electrostatic defending assembly of the present invention is integrated within the ditching type metal oxide semi conductor transistor assembly, need not utilize extra light shield, therefore have work simplification and advantage with low cost.
Description of drawings
Fig. 1 to Figure 10 has illustrated the method schematic diagram of one embodiment of the present invention making trench semiconductor component.
Figure 11 and Figure 12 have illustrated the schematic diagram of the ditching type electrostatic defending assembly of the present embodiment.
Figure 13 has illustrated the top view of the ditching type electrostatic defending assembly of another embodiment of the present invention.
Figure 14 has illustrated the circuit diagram of semiconductor subassembly of the present invention.
Wherein, description of reference numerals is as follows:
10 semiconductor bases, 101 upper surfaces
102 lower surfaces, 103 silicon substrates
104 silicon epitaxial layers 10A the first assembly district
10B the second assembly district 12 dielectric layers
14 photoresistance patterns, 16 photoresistance patterns
181 first irrigation canals and ditches, 182 second irrigation canals and ditches
20 dielectric layers, 22 doping semiconductor layers
23 grids, 24 doped regions
26 matrix doped regions, 28 photoresistance patterns
301 first doped regions, 302 second doped regions
303 the 3rd doped regions, 34 doped regions
36 insulating barriers, 38 contact zones
40 grid leads, 42 source electrodes
44 connecting electrodes, 46 protective layers
48 drain electrodes, 50 ditching type metal oxide semiconductor crystal
The pipe assembly
60 ditching type electrostatic defending assemblies
Embodiment
Please refer to Fig. 1 to Figure 10.Fig. 1 to Figure 10 has illustrated the method schematic diagram of one embodiment of the present invention making trench semiconductor component, and wherein Fig. 1 is a top view, and Fig. 2 to Figure 10 is generalized section.Such as Fig. 1 and shown in Figure 2, provide semiconductor substrate 10.Semiconductor base 10 comprises a upper surface 101 and a lower surface 102, and definition has one first assembly district 10A and one second assembly district 10B on the semiconductor base 10, wherein the first assembly district 10A is in order to make ditching type metal oxide semi conductor transistor assembly, and the second assembly district 10B is then in order to make ditching type electrostatic defending assembly.In the present embodiment, semiconductor base 10 comprises a silicon substrate 103, and one silicon epitaxial layers 104 be positioned on the silicon substrate 103, but the material of semiconductor base 10 is as limit, and can be individual layer or composite semiconductor substrate that other semiconductor material that is fit to consists of.
As shown in Figure 3, then on the upper surface 101 of semiconductor base 10, form a dielectric layer 12, and utilize the first light shield to cooperate lithography process on dielectric layer 12, to form a photoresistance pattern 14, again by etch process pattern dielectric layer 12.The grid lead that acts on isolated semiconductor base 10 and follow-up making of dielectric layer 12.Dielectric layer 12 can be one silica layer, and is formed by techniques such as deposition or thermal oxidations, but also can be made of other dielectric material as limit.
As shown in Figure 4, remove photoresistance pattern 14.Then utilize the second light shield to cooperate lithography process to form another photoresistance pattern 16 in the upper surface 101 of semiconductor base 10, and by etch process for example anisotropic etching process remove the semiconductor base 10 that is not covered by photoresistance pattern 16, upper surface 101 by semiconductor base 10 forms at least one the first irrigation canals and ditches 181 in the first assembly district 10A whereby, and forms at least one the second irrigation canals and ditches 182 in the second assembly district 10B.Then, before photoresistance pattern 16 is not removed, inwall in the first irrigation canals and ditches 181 and the second irrigation canals and ditches 182 forms a dielectric layer 20, for example utilize thermal oxidation technology to form an oxide layer, wherein be positioned at the dielectric layer 20 of inwall of the first irrigation canals and ditches 181 as the usefulness of the gate insulator of the ditching type metal oxide semi conductor transistor assembly of follow-up formation, the dielectric layer 20 that is positioned at the inwall of the second irrigation canals and ditches 182 then is used for ditching type electrostatic defending assembly and the semiconductor base 10 of isolated follow-up formation.In the present embodiment, to make a plurality of each other ditching type electrostatic defending assemblies of serial connection in order to promote electrostatic protection effect, therefore in the second assembly district 10B, formed a plurality of the second irrigation canals and ditches 182, and the demand of the number of the second irrigation canals and ditches 182 and unrestricted and visual electrostatic protection effect is changed.
As shown in Figure 5, remove photoresistance pattern 16.Subsequently, in the upper surface 101 formation semi-conductor layer of semiconductor base 10, and make semiconductor layer insert the first irrigation canals and ditches 181 and the second irrigation canals and ditches 182.Then carrying out ion implantation technology makes semiconductor layer form doping semiconductor layer 22 again, and utilize thermal process to drive in admixture, wherein the doping semiconductor layer 22 in the first irrigation canals and ditches 181 is as the usefulness of the grid of the ditching type metal oxide semi conductor transistor assembly of follow-up formation, and the doping semiconductor layer 22 in the second irrigation canals and ditches 182 is then as the material of the ditching type electrostatic defending assembly of follow-up formation.In the present embodiment, the material selection polysilicon of doping semiconductor layer 22, but not can be the semiconductor material that other is fit to as limit.In addition, doping semiconductor layer 22 mixes for severe and has the first doping type.
As shown in Figure 6, carry out the doping semiconductor layer 22 of the upper surface 101 of comprehensive ground of an etch-back (etch-back) technique ablation semiconductor base 10, and keep the doping semiconductor layer 22 that is positioned within the first irrigation canals and ditches 181 and the second irrigation canals and ditches 182, wherein the doping semiconductor layer 22 in the first irrigation canals and ditches 181 forms the grid 23 of ditching type metal oxide semi conductor transistor assembly.In addition, semiconductor base 10 and doping semiconductor layer 22 are carried out for example comprehensive (blanket) Implantation of ion implantation technology, wherein in this Implantation, implant the admixture of the first doping type of low dosage, therefore the semiconductor base 10 that is not covered by dielectric layer 12 can form the slight doped region 24 that mixes, and be positioned at the first irrigation canals and ditches 181 and can form a matrix doped region 26 with respect to the semiconductor base 10 of the second irrigation canals and ditches 182 opposite sides, and the grid 23 that is positioned at the first irrigation canals and ditches 181 with the doping semiconductor layer 22 that is positioned at the second irrigation canals and ditches 182 owing to having the severe doping so can't be affected.
As shown in Figure 7, utilize the 3rd road light shield to cooperate lithography process to form another photoresistance pattern 28 in the upper surface 101 of semiconductor base 10, make the doping semiconductor layer 22 in photoresistance pattern 28 covering doped regions 24, each second irrigation canals and ditches 182 of partial coverage, and partial coverage matrix doped region 26.Then carry out ion implantation technology, the high dose admixture that will have the second doping type is implanted the doping semiconductor layer 22 and matrix doped region 26 that is not covered by photoresistance pattern 28, forms whereby one second doped region 302 and one the 3rd doped region 303 within each second irrigation canals and ditches 182.On the other hand, 22 of doping semiconductor layers that covered by photoresistance pattern 28 are mixed and formed the first doped region 301 between the second doped region 302 and the 3rd doped regions 303.Because the first doped region 301 has different doping types from the second doped region 302, therefore can form a diode assembly with PN junction, and the first doped region 301 and the 3rd doped region 303 also can form the diode assembly that another has the PN junction, the first doped region 301, the second doped region 302 and the 3rd doped region 303 can form a diode assembly with bi-directional electrostatic protective capacities, for example bi-directional zener diode assembly whereby.In addition, then do not formed two doped regions 34 in the matrix doped region 26 of photoresistance pattern 28 coverings.
As shown in Figure 8, remove photoresistance pattern 28.Subsequently, utilize the 4th road light shield to cooperate little shadow and etch process to form an insulating barrier 36 in the upper surface 101 of semiconductor base 10.Insulating barrier 36 can be for example boron-phosphorosilicate glass (BPSG) or the formed dielectric layer of other material, and insulating barrier 36 exposes the second doped region 302 and the 3rd doped region 303 in the second irrigation canals and ditches 182, and matrix doped region 26.Then, carry out ion implantation technology, the high dose admixture that will have the second doping type is implanted matrix doped region 26, the second doped region 302 and the 3rd doped region 303 that insulating barrier 36 exposes, and forms the contact zone 38 that severe is mixed and had the second doping type on the surface of matrix doped region 26, the second doped region 302 and the 3rd doped region 303 whereby.
As shown in Figure 9, utilize the 5th road light shield to cooperate little shadow and etch process to form a grid lead 40, one source pole 42 and connecting electrode 44 in the upper surface 101 of semiconductor base 10.Grid lead 40 respectively with the second irrigation canals and ditches 182 in the bonding pad 38 of the second doped region 302, and be electrically connected with grid 23 in the first irrigation canals and ditches 181; Source electrode 42 is electrically connected with the bonding pad 38 of matrix doped region 26; In addition, 44 of connecting electrodes are electrically connected the bonding pad 38 of the second doped region 302 in the bonding pad 38 of the 3rd doped region 303 in one second irrigation canals and ditches 182 and adjacent another second irrigation canals and ditches 182, and ditching type electrostatic defending assembly is electrically connected with series system.
As shown in figure 10, then the 6th road light shield cooperates little shadow and etch process to form a protective layer 46 on semiconductor base 10, and wherein protective layer 46 exposes part of grid pole wire 40 and source electrode 42, with further for the electric connection of follow-up formation interconnect layer do.In addition, the lower surface 102 in semiconductor base 10 forms a drain electrode 48.What deserves to be explained is the lower surface 102 that drain electrode 48 is formed at semiconductor base 10, so the time point that its step is carried out is not limited thereto, and can carries out in other reasonable time point, for example before or after the positive technique of semiconductor substrate 10 is carried out, carry out.
Please refer to Figure 11 and Figure 12.Figure 11 and Figure 12 have illustrated the schematic diagram of the ditching type electrostatic defending assembly of the present embodiment, and wherein Figure 12 is the local enlarged diagram of Figure 11.Such as Figure 11 and shown in Figure 12, a plurality of ditching type electrostatic defending assemblies are formed at respectively within each second irrigation canals and ditches 182, and the bonding pad 38 of the second doped region 302 of grid lead 40 and a ditching type electrostatic defending assembly is electrically connected, connecting electrode 44 then is connected with the bonding pad 38 of the second doped region 302 of the bonding pad 38 of the 3rd doped region 303 of a ditching type electrostatic defending assembly and another neighbouring trenches formula electrostatic defending assembly respectively, whereby ditching type electrostatic defending assembly is connected with series system.On the other hand, 42 of source electrodes are electrically connected with bonding pad 38 with respect to the 3rd doped region 303 of the ditching type electrostatic defending assembly of grid lead 40 opposite sides.In the present embodiment, the second irrigation canals and ditches 182 are by the open square ring that is of upper apparent direction sight, and its size increases progressively to the outer ring by inner ring, and cooperate the connecting electrode 44 with analogous shape, yet the shape of the second irrigation canals and ditches 182 not can be other shape as limit.
Please refer to Figure 13.Figure 13 has illustrated the top view of the ditching type electrostatic defending assembly of another embodiment of the present invention.As shown in figure 13, the size that is second irrigation canals and ditches 182 of the present embodiment with above-described embodiment difference is little than previous embodiment, and the present embodiment utilizes a plurality of undersized the second irrigation canals and ditches 182 to form the concentric turns pattern of similar previous embodiment, but between the 3rd doped region 303 of the second irrigation canals and ditches 182 inside of same circle, be not connected to each other, but be electrically connected with the second doped region 302 that is positioned at adjacent turn and corresponding the second irrigation canals and ditches 182 inside.In other words, between grid lead 40 and the source electrode 42 and many passages in parallel are arranged, and each passage is made of the ditching type electrostatic defending assembly that connects with series system respectively.
In declarative description of the present invention, the first doping type and the second doping type mean two kinds of different doping types, for example P type and N-type, and the kind of the ditching type metal oxide semi conductor transistor assembly that its visual institute wish is made is selected.If for example ditching type metal oxide semi conductor transistor assembly is N-type metal oxide semiconductor transistor (NMOS) assembly, then the first doping type is that P type and the second doping type are N-type, if but ditching type metal oxide semi conductor transistor assembly is P-type mos transistor (PMOS) assembly, then the first doping type is that N-type and the second doping type are the P type.In addition, ditching type metal oxide semi conductor transistor assembly is power ditching type metal oxide semi conductor transistor assembly, but not as limit; Ditching type electrostatic defending assembly is then in order to providing electrostatic defending, and can connect to increase electrostatic protection effect by series system.
Please refer to Figure 14, and please cooperate with reference to Figure 10.Figure 14 has illustrated the circuit diagram of semiconductor subassembly of the present invention.Such as Figure 10 and shown in Figure 14, ditching type electrostatic defending assembly 60 is connected to each other with series system, and ditching type electrostatic defending assembly 60 is electrically connected between the grid 23 and source electrode 42 of ditching type metal oxide semi conductor transistor assembly 50, whereby when electrostatic discharge pulses that grid lead 40 produces because of friction or other uncontrollable factor, this has high-tension electrostatic discharge pulses can flow to ditching type electrostatic defending assembly 60 again via source electrode 42 outflows, and can directly not be passed to the grid 23 of ditching type metal oxide semi conductor transistor assembly 50, therefore can avoid ditching type metal oxide semi conductor transistor assembly 50 impaired.In addition, because the ditching type electrostatic defending assembly 60 of the present embodiment has the bi-directional electrostatic protective capacities, no matter therefore electrostatic discharge pulses is positive voltage or negative voltage, but equal effective supply electrostatic defending function.
In sum, trench semiconductor component of the present invention comprises ditching type metal oxide semi conductor transistor assembly and ditching type electrostatic defending assembly, and ditching type electrostatic defending assembly is electrically connected between the grid and source electrode of ditching type metal oxide semi conductor transistor assembly, and good antistatic capacity is provided whereby.Because the making of ditching type electrostatic defending assembly is integrated within the ditching type metal oxide semi conductor transistor assembly, therefore need not utilize the position of the doped region of extra light shield definition ditching type electrostatic defending assembly, therefore have work simplification and advantage with low cost.Moreover the number of ditching type electrostatic defending assembly is visual antistatic capacity demand and being adjusted also, and can be applicable on the various semiconductor subassembly.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (14)
1. a trench semiconductor component is characterized in that, comprising:
The semiconductor substrate, comprise a upper surface and a lower surface, definition has one first assembly district and one second assembly district on the described semiconductor base, and the described upper surface of described semiconductor base comprises that at least one the first irrigation canals and ditches are positioned within described the first assembly district, and at least one the second irrigation canals and ditches are positioned within described the second assembly district;
At least one ditching type metal oxide semi conductor transistor assembly is arranged in described the first assembly district, and wherein said ditching type metal oxide semi conductor transistor assembly comprises:
One dielectric layer is positioned at the sidewall of described the first irrigation canals and ditches;
One grid is positioned within described the first irrigation canals and ditches;
One matrix doped region is positioned at the described semiconductor base of a side of described the first irrigation canals and ditches;
One source pole is positioned at the described upper surface of described semiconductor base and is electrically connected with described matrix doped region; And
One drains, and is positioned at the described lower surface of described semiconductor base;
One ditching type electrostatic defending assembly, be arranged within described second irrigation canals and ditches in described the second assembly district, described ditching type electrostatic defending assembly comprises one first doped region and one second doped region, wherein said the first doped region has one first doping type, described the second doped region has one second doping type, and described the first doped region has different doping types from described the second doped region: and
One grid lead, be arranged at the described upper surface of described semiconductor base, wherein said grid lead respectively with the described grid of described ditching type metal oxide semi conductor transistor assembly, and described second doped region of described ditching type electrostatic defending assembly is electrically connected.
2. trench semiconductor component as claimed in claim 1 is characterized in that, the described grid of described ditching type metal oxide semi conductor transistor assembly is a doping semiconductor layer.
3. trench semiconductor component as claimed in claim 2 is characterized in that, described doping semiconductor layer is a doped polysilicon layer.
4. trench semiconductor component as claimed in claim 2 is characterized in that, described doping semiconductor layer has described the second doping type.
5. trench semiconductor component as claimed in claim 1 is characterized in that, the described matrix doped region of described ditching type metal oxide semi conductor transistor assembly has described the first doping type.
6. trench semiconductor component as claimed in claim 1, it is characterized in that, described ditching type electrostatic defending assembly comprises that in addition the 3rd doped region with described second doping type is positioned at described the second irrigation canals and ditches, and the described source electrode of described the 3rd doped region and described ditching type metal oxide semi conductor transistor assembly is electrically connected.
7. trench semiconductor component as claimed in claim 1, it is characterized in that, other comprises that another ditching type electrostatic defending assembly is arranged within another second irrigation canals and ditches, and one connecting electrode be arranged at the described upper surface of described semiconductor base, wherein said ditching type electrostatic defending assembly is electrically connected with series system by described connecting electrode.
8. trench semiconductor component as claimed in claim 1 is characterized in that, described semiconductor base comprises a silicon substrate, and a silicon epitaxial layers is positioned on the described silicon substrate, and described the first irrigation canals and ditches and described the second irrigation canals and ditches are positioned within the described silicon epitaxial layers.
9. trench semiconductor component as claimed in claim 1 is characterized in that, described ditching type metal oxide semi conductor transistor assembly comprises an aqueduct type power metal oxide semiconductor transistor assembly.
10. trench semiconductor component as claimed in claim 1 is characterized in that, described ditching type electrostatic defending assembly comprises a diode assembly.
11. a method of making trench semiconductor component is characterized in that, comprising:
The semiconductor substrate is provided, definition has one first assembly district and one second assembly district on the described semiconductor base, and a upper surface of described semiconductor base has at least one the first irrigation canals and ditches and is positioned within described the first assembly district, and at least one the second irrigation canals and ditches are positioned within described the second assembly district;
Inwall in described the first irrigation canals and ditches and described the second irrigation canals and ditches forms a dielectric layer;
Form a doping semiconductor layer within described the first irrigation canals and ditches and described the second irrigation canals and ditches, wherein said doping semiconductor layer has one first doping type;
Form a matrix doped region in the described semiconductor base in described the first assembly district, wherein said matrix doped region has described the first doping type;
Form a mask pattern in the surface of described semiconductor base and described doping semiconductor layer, the described doping semiconductor layer in described the second irrigation canals and ditches of wherein said mask pattern partial coverage;
Carry out an Implantation, change not the doping type of the described doping semiconductor layer in described the second irrigation canals and ditches that covered by described mask pattern, so that the described doping semiconductor layer that is covered by described mask pattern forms one first doped region, and make and be positioned at the described doping semiconductor layer that described the first doped region two sides do not cover by described mask pattern and form respectively one second doped region and one the 3rd doped region, wherein said the second doped region and described the 3rd doped region have one second doping type;
Form an insulating barrier in the surface of described semiconductor base, wherein said insulating barrier exposes described the second doped region and described the 3rd doped region in described the second irrigation canals and ditches; And
On described semiconductor base, form a grid lead and one source pole, wherein said grid lead respectively with described the second irrigation canals and ditches in described the second doped region, and be electrically connected with described doping semiconductor layer in described the first irrigation canals and ditches, and described source electrode and the electric connection of described matrix doped region.
12. the method for making trench semiconductor component as claimed in claim 11 is characterized in that, other is included in and forms on the described semiconductor base before the described source electrode, has the contact zone of described the second doping type prior to formation one in the described matrix doped region.
13. the method for making trench semiconductor component as claimed in claim 11 is characterized in that, a lower surface that other is included in described semiconductor base forms a drain electrode.
14. the method for making trench semiconductor component as claimed in claim 11, it is characterized in that, described the second assembly district comprises a plurality of the second irrigation canals and ditches, and the described method described upper surface that is included in addition described semiconductor base forms a connecting electrode and is electrically connected described the second doped region in described the 3rd doped region second irrigation canals and ditches adjacent with another in one second irrigation canals and ditches with series system.
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| CN 201010186803 CN102263105B (en) | 2010-05-26 | 2010-05-26 | Trench semiconductor component and manufacturing method |
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| CN102593125A (en) * | 2012-03-09 | 2012-07-18 | 上海宏力半导体制造有限公司 | Groove type MOS (metal oxide semiconductor) electrostatic discharge structure and integrated circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524298A (en) * | 2001-05-22 | 2004-08-25 | ͨ�ð뵼�幫˾ | DMOS with zener diode for ESD protection |
| CN101351893A (en) * | 2005-12-28 | 2009-01-21 | 维西埃-硅化物公司 | Trench polysilicon diode |
| JP2009016725A (en) * | 2007-07-09 | 2009-01-22 | Panasonic Corp | Semiconductor device |
| CN101447453A (en) * | 2007-11-29 | 2009-06-03 | 万国半导体股份有限公司 | Method for preventing gate oxide damage of a trench MOSFET during wafer processing |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI290730B (en) * | 2004-08-30 | 2007-12-01 | Mosel Vitelic Inc | Manufacturing process for integrated circuit |
| US20070176239A1 (en) * | 2006-01-31 | 2007-08-02 | M-Mos Semiconductor Sdn. Bhd. | Trenched MOSFETS with improved ESD protection capability |
| US7897997B2 (en) * | 2008-02-23 | 2011-03-01 | Force Mos Technology Co., Ltd. | Trench IGBT with trench gates underneath contact areas of protection diodes |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1524298A (en) * | 2001-05-22 | 2004-08-25 | ͨ�ð뵼�幫˾ | DMOS with zener diode for ESD protection |
| CN101351893A (en) * | 2005-12-28 | 2009-01-21 | 维西埃-硅化物公司 | Trench polysilicon diode |
| JP2009016725A (en) * | 2007-07-09 | 2009-01-22 | Panasonic Corp | Semiconductor device |
| CN101447453A (en) * | 2007-11-29 | 2009-06-03 | 万国半导体股份有限公司 | Method for preventing gate oxide damage of a trench MOSFET during wafer processing |
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