CN112234123A

CN112234123A - Integrated device for two-way communication and preparation method thereof

Info

Publication number: CN112234123A
Application number: CN202011065496.2A
Authority: CN
Inventors: 田朋飞; 朱世杰; 闫春辉; 崔旭高; 方志来; 张国旗
Original assignee: Shenzhen Third Generation Semiconductor Research Institute
Current assignee: Shenzhen Third Generation Semiconductor Research Institute
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2021-01-15

Abstract

The application relates to the technical field of semiconductors, and particularly discloses an integrated device for bidirectional communication and a preparation method thereof. The method comprises the following steps: providing a first substrate, a second substrate and a third substrate; forming a first micro-LED chip on a first substrate, forming a first reserved area for placing a second micro-LED chip and a second reserved area for placing a GaN-based HEMT on the first substrate, forming a second micro-LED chip on a second substrate, and forming a GaN-based HEMT on a third substrate; removing the second substrate and transferring the second micro-LED chip to the first reserved region, removing the third substrate and transferring the GaN-based HEMT to the second reserved region; and establishing the electric connection between the first micro-LED chip and the GaN-based HEMT. Through the mode, the micro-LED and GaN-based HEMT integrated device can be combined with the advantages of the micro-LED and the GaN-based HEMT, and a semiconductor integrated device with high integration level, high efficiency and reliability can be developed.

Description

Integrated device for two-way communication and preparation method thereof

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to an integrated device for bidirectional communication and a method for manufacturing the same.

Background

In recent years, the visible light communication technology has become a great research hotspot in the communication field due to the advantages of unlimited spectrum resources, good confidentiality, integration with infrastructure lighting facilities and the like.

Because the micro light-emitting diode (micro-LED) has the characteristics of small size, high response speed, high current density, long service life and low power consumption, the micro light-emitting diode has good achievement in the display field. The optical fiber is used for light emission and light detection in the field of visible light communication, also has great application potential, is very suitable for a photonic integrated chip, and needs an additional high-frequency switching device for driving. Because GaN has the advantages of large forbidden band width, high electron mobility, high breakdown field strength and the like, GaN-based HEMTs become hot spots for research of new-generation power devices.

In the long-term research and development process, the inventor of the application finds that the prior art is difficult to produce an integrated device which integrates the functions of a GaN-based HEMT, a light emitter and a light detector on the same substrate.

Disclosure of Invention

Based on the integrated device for the bidirectional communication and the preparation method thereof, the integrated device for the bidirectional communication can be combined with the advantages of the micro-LED and the GaN-based HEMT to develop a semiconductor integrated device with high integration level, high efficiency and reliability.

In order to solve the technical problem, the application adopts a technical scheme that: there is provided a method of manufacturing an integrated device for bidirectional communication, the method comprising: providing a first substrate, a second substrate and a third substrate; forming a first micro-LED chip on a first substrate, forming a first reserved area for placing a second micro-LED chip and a second reserved area for placing a GaN-based HEMT on the first substrate, forming a second micro-LED chip on a second substrate, and forming a GaN-based HEMT on a third substrate; removing the second substrate and transferring the second micro-LED chip to the first reserved region, removing the third substrate and transferring the GaN-based HEMT to the second reserved region; establishing electric connection between the first micro-LED chip and the GaN-based HEMT; the central light-emitting wavelength of any light-emitting point in the light-emitting area of the first micro-LED chip is smaller than that of any light-emitting point in the light-emitting area of the second micro-LED chip.

In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided an integrated device for bidirectional communication, the integrated device comprising: a first substrate; a first micro-LED chip disposed on the first substrate; the second micro-LED chip is arranged on the first reserved area of the first substrate; the GaN-based HEMT is arranged on the second reserved area of the first substrate, and the first micro-LED chip is electrically connected with the GaN-based HEMT; the central light-emitting wavelength of any light-emitting point in the light-emitting area of the first micro-LED chip is smaller than that of any light-emitting point in the light-emitting area of the second micro-LED chip.

The beneficial effect of this application is: different from the situation of the prior art, the inventor of the application finds that the micro-LED chip has the functions of light emission and light detection, and then integrates two different micro-LED chips and one GaN-based HEMT on the same substrate to prepare the integrated device for bidirectional communication, can combine the advantages of the micro-LED and the GaN-based HEMT to develop the semiconductor integrated device with high integration level, high efficiency and reliability, and has wider application scenes. In addition, the first micro-LED chip, the second micro-LED chip and the GaN-based HEMT are respectively grown on different substrates instead of simultaneously growing two different micro-LED chips and one GaN-based HEMT on the same substrate, so that the growth process of the whole device is effectively prevented from being too complicated, and the failure of the whole device caused by the damage of the micro-LED chips or the GaN-based HEMT in the growth process can be prevented. Furthermore, the integrated device can greatly simplify the packaging complexity and reduce parasitic elements; by reducing the connecting wires, the parasitic resistance and capacitance can be greatly reduced, and the efficiency and the response time of the capacitor can be further improved. In addition, the central luminous wavelength of any luminous point of the active luminous layers of the light emitter and the light detector is controlled, so that the Stokes shift effect of micro-LEDs can be effectively reduced, the light detector obtains higher responsivity, and the communication performance is better.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:

FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a method for fabricating an integrated device for bi-directional communication according to the present application;

FIG. 2 is a flowchart illustrating an embodiment of step S2 in FIG. 1;

FIG. 3 is a schematic flow chart diagram illustrating another embodiment of step S2 in FIG. 1;

FIG. 4 is a schematic flow chart diagram illustrating a further embodiment of step S2 in FIG. 1;

FIG. 5 is a flowchart illustrating an embodiment of step S3 in FIG. 1;

FIG. 6 is a schematic flow chart of a further embodiment of step S2 in FIG. 1;

FIG. 7 is a schematic flow chart diagram illustrating another embodiment of step S3 in FIG. 1;

FIG. 8 is a flowchart illustrating an embodiment of step S4 in FIG. 1;

FIG. 9 is a schematic diagram of a top view configuration of an integrated device for bi-directional communication;

FIG. 10 is a schematic structural diagram corresponding to step S218 in FIG. 3;

FIG. 11 is a schematic diagram of a structure corresponding to the method illustrated in FIGS. 2 and 3;

FIG. 12 is a schematic diagram of a structure corresponding to the method illustrated in FIGS. 4 and 5;

FIG. 13 is a schematic diagram of a structure corresponding to the method of FIG. 6;

FIG. 14 is a schematic diagram of a structure corresponding to the method illustrated in FIGS. 7 and 6;

FIG. 15 is a schematic diagram of a partial structure of an integrated device for bi-directional communication;

fig. 16 is another partial structural diagram of an integrated device for bidirectional communication.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The present application proposes a method for manufacturing an integrated device for bidirectional communication, referring to fig. 1 and fig. 11 to 14, the method comprising:

s1: a first substrate 100, a second substrate 200 and a third substrate 300 are provided.

The material of the first substrate 100 may be sapphire, Si, GaN, SiC, or other suitable materials, and preferably, the material of the first substrate 100 may be sapphire. The material of the second substrate 200 may be Si. The material of the third substrate 300 may be Si.

S2: the first micro-LED chip 110 is formed on the first substrate 100, and the first reserved region 101 for placing the second micro-LED chip 120 and the second reserved region 102 for placing the GaN-based HEMT130 are formed on the first substrate 100, the second micro-LED chip 120 is formed on the second substrate 200, and the GaN-based HEMT130 is formed on the third substrate 300.

Specifically, the first micro-LED chip 110, the second micro-LED chip 120, and the GaN-based High Electron Mobility Transistor 130 (HEMT) are respectively prepared on the selected first substrate 100, the second substrate 200, and the third substrate 300 using a semiconductor standard process.

Two sets of light emitters and light detectors are generally required for bidirectional communication, wherein the first micro-LED chip 110 serves as the light emitter in the integrated device 10, the second micro-LED chip 120 serves as the light detector in the integrated device 10, and the GaN-based HEMT130 serves as a high-frequency switch in the integrated device 10 for controlling the on/off of the light emitter (i.e., the first micro-LED chip 110).

The first substrate 100 serves as a shared substrate, and the first reserved area 101 and the second reserved area 102 on the first substrate 100 are arranged at intervals.

S3: the second substrate 200 is removed and the second micro-LED chip 120 is transferred to the first reserved region 101, and the third substrate 300 is removed and the GaN-based HEMT130 is transferred to the second reserved region 102.

The specific process of removing the second substrate 200 and the third substrate 300 may be determined according to the materials of the second substrate 200 and the third substrate 300, for example, when the second substrate 200 and the third substrate 300 are both Si substrates, the Si substrates may be etched by wet etching, where an etchant used in the wet etching may be KOH solution.

Further, the peeled second micro-LED chip 120 may be transferred to the first reserved region 101 and the peeled GaN-based HEMT130 may be transferred to the second reserved region 102 using a transfer printing technique.

Among them, the transfer printing technique is to transfer a single thin-film device removed from an original substrate onto another substrate using an accurate pick-and-place manner.

Specifically, the executing part of the transfer printing technology may be an elastic stamp (not shown), specifically, a Polydimethylsiloxane (PDMS) elastic stamp, which is an elastomer with a relatively stable structure and high strength and is an ideal material for making the elastic stamp. The conventional transfer printing technology needs to transfer the prepared second micro-LED chip 120 or GaN-based HEMT130 from the original substrate to an elastic stamp and then to another substrate using an elastic stamp. For example, in the present embodiment, the second micro-LED chip 120, the GaN-based HEMT130 are transferred onto the first substrate 100.

S4: electrical connection of the first micro-LED chip 110 and the GaN-based HEMT130 is established.

After the transfer is finished, a new semiconductor integrated device is produced by establishing electrical connection between the first micro-LED chip 110 and the GaN-based HEMT 130.

It should be noted that, during long-term research and development, the inventors of the present application found that, if the light emitter (i.e., the first micro-LED chip 110) and the light detector (i.e., the second micro-LED chip 120) in the integrated device 10 both use the same active light emitting layer, the light spectrum detected by the light detector is not at the optimal absorption wavelength thereof according to the stokes shift effect of the micro-LEDs, thereby affecting the responsivity of the light detector. In order to improve the responsivity of the light detector, the central light-emitting wavelength of any light-emitting point in the light-emitting area of the first micro-LED chip 110 is smaller than the central light-emitting wavelength of any light-emitting point in the light-emitting area of the second micro-LED chip 120. The central luminous wavelength of any luminous point of the active luminous layers of the light emitter and the light detector is controlled, so that the Stokes displacement effect of micro-LEDs can be effectively reduced, the light detector obtains higher responsivity, and the communication performance is better.

Different from the situation of the prior art, the inventor of the application finds that the micro-LED chip has the functions of light emission and light detection, and then integrates two different

micro-LED chips

110 and 120 and one GaN-based HEMT130 on the same substrate to prepare the integrated device 10 for bidirectional communication, and can combine the advantages of the

micro-LED chips

110 and 120 and the GaN-based HEMT130 to develop a semiconductor integrated device with high integration, high efficiency and reliability, and the application scene is wider. In addition, according to the preparation method, the first micro-LED chip 110, the second micro-LED chip 120 and the GaN-based HEMT130 grow on different substrates respectively, instead of simultaneously growing two different

micro-LED chips

110 and 120 and one GaN-based HEMT130 on the same substrate, the growth process of the whole device is effectively avoided to be too complicated, and the failure of the whole device caused by the damage of the micro-LED chips or the GaN-based HEMT130 in the growth process can be prevented. Further, the integrated device 10 can greatly simplify the packaging complexity and reduce parasitic elements; by reducing the connecting wires, the parasitic resistance and capacitance can be greatly reduced, and the efficiency and the response time of the capacitor can be further improved. In addition, the central luminous wavelength of any luminous point of the active luminous layers of the light emitter and the light detector is controlled, so that the Stokes shift effect of micro-LEDs can be effectively reduced, the light detector obtains higher responsivity, and the communication performance is better.

Referring to fig. 2 and 11, in an embodiment, step S2 includes:

s211: a first buffer layer 111 is formed on one side of the first substrate 100.

The material of the first buffer layer 111 may be GaN. In this step, the first buffer layer 111 may be grown on one side of the first substrate 100 by a conventional Metal-organic Chemical Vapor Deposition (MOCVD) process or by means of a process such as physical Vapor Deposition, sputtering, hydrogen Vapor Deposition, or atomic layer Deposition.

S212: a first light emitting epitaxial layer 112 is formed on a side of the first buffer layer 111 away from the first substrate 100.

The first light emitting epitaxial layer 112 includes a first conductive type semiconductor layer 1121, a first active light emitting layer 1122, and a second conductive type semiconductor layer 1123, which are sequentially stacked on one side of the first buffer layer 111.

Specifically, the first conductivity type semiconductor layer 1121, the first active light-emitting layer 1122, and the second conductivity type semiconductor layer 1123 are sequentially grown by MOCVD (metal organic chemical vapor deposition), Molecular Beam Epitaxy (MBE), or the like.

The first conductive type semiconductor layer 1121 is an n-type GaN layer, and may be a GaN layer doped with at least one of Si, Ge, and Sn. The first active light emitting layer 1122 may be a single-layer quantum well (SQW) or a multi-layer quantum well (MQW). The second conductive type semiconductor layer 1123 is a p-type GaN layer, and may Be specifically a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.

S213: the first current diffusion layer 113 is formed on a side of the second conductive type semiconductor layer 1123 away from the first active light emitting layer 1122.

Specifically, the first current diffusion layer 113 is grown on the side of the second conductivity-type semiconductor layer 1123 away from the first active light-emitting layer 1122 using a magnetron sputtering method. The first current diffusion layer 113 may employ a transparent conductive material, such as Indium Tin Oxide (ITO). In other embodiments, the first current spreading layer 113 may be a metal transparent thin layer including nickel (Ni), gold (Au), or other suitable metal.

S214: the first current diffusion layer 113, the second conductive type semiconductor layer 1123, and the first active light emitting layer 1122 are patterned to form a first mesa structure 114 partially exposing the first conductive type semiconductor layer 1121.

Specifically, an etching process is applied to remove a portion of the first current diffusion layer 113, the second conductive type semiconductor layer 1123 and the first active light emitting layer 1122 to form the first mesa structure 114 partially exposing the first conductive type semiconductor layer 1121.

The etching process may include dry etching, wet etching, or a combination thereof. The etching process may include various etching steps, each of which is designed to use a specific etchant to effectively remove the corresponding first current diffusion layer 113, second conductive type semiconductor layer 1123, and first active light emitting layer 1122.

For example, a layer of photoresist may be coated on the surface of the first micro-LED chip 110, and the first mesa structure 114 is defined by an exposure and development technique. The first current diffusion layer 113 without the photoresist region is etched to the surface of the second conductivity-type semiconductor layer 1123 by using a wet etching process, where an etchant used in the wet etching may be a concentrated hydrochloric acid/concentrated nitric acid mixed solution (where a volume ratio of concentrated hydrochloric acid to concentrated nitric acid is 4: 1). Etching the photoresist-free region to the surface of the first conductive type semiconductor layer 1121 by using an Inductively Coupled Plasma (ICP) dry etching method, wherein the etching gas may be BCl₃、Ar。

S215: a first conductivity type electrode 115 is formed on a portion of the first conductivity type semiconductor layer 1121 exposed by the first mesa structure 114, wherein the first conductivity type electrode 115 is electrically connected to the first conductivity type semiconductor layer 1121.

Here, the first conductive type electrode 115 is an n-type electrode corresponding to the n-type GaN layer. Specifically, one or more metals of Cr/Al/Ti/Au may be fabricated on the exposed surface of the first conductivity-type semiconductor layer 1121 to form the first conductivity-type electrode 115, so that the first conductivity-type electrode 115 is an n-type electrode, and the first conductivity-type electrode 115 is electrically connected to the first conductivity-type semiconductor layer 1121, for example, in this embodiment, the first conductivity-type electrode 115 is electrically connected to the first conductivity-type semiconductor layer 1121 in a direct contact manner.

S216: a second conductivity-type electrode 116 is formed on a side of the first current diffusion layer 113 away from the second conductivity-type semiconductor layer 1123, wherein the second conductivity-type electrode 116 is electrically connected to the first current diffusion layer 113.

Wherein, the second conductive type electrode 116 is a p-type electrode corresponding to the p-type GaN layer. Specifically, the second conductivity-type electrode 116 may be formed by forming Ti/Au metal on the side of the first current diffusion layer 113 away from the second conductivity-type semiconductor layer 1123, so that the second conductivity-type electrode 116 is a p-type electrode, and the second conductivity-type electrode 116 is electrically connected to the first current diffusion layer 113.

Specifically, a photoresist may be coated on a portion of the first conductive type semiconductor layer 1121 exposed by the first mesa structure 114 and a side of the first current diffusion layer 113 away from the second conductive type semiconductor layer 1123, and areas of the first conductive type electrode 115 and the second conductive type electrode 116 are defined by exposure and development, respectively, and a corresponding metal layer is evaporated or sputtered to remove the residual photoresist to form the first conductive type electrode 115 and the second conductive type electrode 116.

Referring to fig. 3 and fig. 10-11, in an embodiment, the step S2 further includes:

s217: the first conductive type semiconductor layer 1121 and the first buffer layer 111 are patterned to form the second mesa structure 117 partially exposing the first substrate 100.

S218: a first reserved region 101 and a second reserved region 102 are formed on a portion of the first substrate 100 exposed by the second mesa structure 117.

Specifically, after removing the residual photoresist, the photoresist is recoated and exposed to light and developed, and a second mesa structure 117 is defined on the existing first mesa structure 114 again. And etching the photoresist-free area to the surface of the first substrate 100 by adopting an ICP dry etching method.

Further, step S2 further includes: the residual photoresist is removed and ohmic contact is formed between the first current diffusion layer 113 and the second conductive type semiconductor layer 1123 using a thermal annealing method.

It should be noted that the sequence of steps S215, S216, and S217 is not limited.

Referring to fig. 4 and 12, in an embodiment, step S2 includes:

s221: a second buffer layer 121 is formed on one side of the second substrate 200.

The material of the second buffer layer 121 may be any one or a combination of AlN, AlGaN, and GaN. In this step, the second buffer layer 121 may be grown on one side of the second substrate 200 by a conventional MOCVD process or by means of, for example, a physical vapor deposition, sputtering, a hydrogen vapor deposition method, or an atomic layer deposition process.

S222: a second light emitting epitaxial layer 122 is formed on a side of the second buffer layer 121 remote from the second substrate 200.

The second light emitting epitaxial layer 122 includes a third conductive type semiconductor layer 1221, a second active light emitting layer 1222, and a fourth conductive type semiconductor layer 1223 sequentially stacked on one side of the second buffer layer 121.

Specifically, the third conductive type semiconductor layer 1221, the second active light emitting layer 1222, and the fourth conductive type semiconductor layer 1223 are sequentially grown by a method such as MOCVD or MBE.

The thickness of the second substrate 200 is 800 micrometers, the thickness of the second buffer layer 121 is 0.5 to 5 micrometers, the thickness of the third conductive type semiconductor layer 1221 is 0.1 to 5 micrometers, the thickness of the second active light emitting layer 1222 is 0.01 to 0.5 micrometers, and the thickness of the fourth conductive type semiconductor layer 1223 is 0.05 to 0.5 micrometers. Preferably, the thickness of the second substrate 200 is 600 micrometers, the thickness of the second buffer layer 121 is 1.2 micrometers, the thickness of the third conductive type semiconductor layer 1221 is 1 micrometer, the thickness of the second active light emitting layer 1222 is 0.1 micrometer, and the thickness of the fourth conductive type semiconductor layer 1223 is 0.15 micrometer.

The third conductive type semiconductor layer 1221 is an n-type GaN layer, and may be a GaN layer doped with at least one of Si, Ge, and Sn. The second active light emitting layer 1222 may be a single quantum well or a multi-layer quantum well. The fourth conductive type semiconductor layer 1223 is a p-type GaN layer, and may Be specifically a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.

S223: a second current diffusion layer 123 is formed on a side of the fourth conductive type semiconductor layer 1223 remote from the second active light emitting layer 1222.

Specifically, the second current diffusion layer 123 is grown on the side of the fourth conductivity-type semiconductor layer 1223 remote from the second active light emitting layer 1222 using a magnetron sputtering method. The second current spreading layer 123 may employ a transparent conductive material, such as indium tin oxide. In other embodiments, the second current spreading layer 123 may be a thin metal transparent layer comprising nickel, gold, or other suitable metal.

S224: the second current diffusion layer 123, the fourth conductive type semiconductor layer 1223, and the second active light emitting layer 1222 are patterned to form a third mesa structure 124 partially exposing the third conductive type semiconductor layer 1221.

Specifically, an etching process is applied to remove portions of the second current diffusion layer 123, the fourth conductive type semiconductor layer 1223, and the second active light emitting layer 1222 to form the third mesa structure 124 partially exposing the third conductive type semiconductor layer 1221.

The etching process may include dry etching, wet etching, or a combination thereof. The etching process may include various etching steps, each of which is designed to use a specific etchant to effectively remove the corresponding second current diffusion layer 123, fourth conductive type semiconductor layer 1223, and second active light emitting layer 1222.

For example, a photoresist layer may be coated on the surface of the second micro-LED chip 120, and the third mesa structure 124 may be defined by an exposure and development technique. And etching the second current diffusion layer 123 in the photoresist-free region to the surface of the third conductivity-type semiconductor layer 1221 by using a wet etching process, wherein an etchant used in the wet etching process is a concentrated hydrochloric acid/concentrated nitric acid mixed solution (wherein the volume ratio of the concentrated hydrochloric acid to the concentrated nitric acid is 4: 1). The photoresist-free region is etched to the surface of the fourth conductive type semiconductor layer 1223 by using an ICP dry etching method.

S225: a third conductive-type electrode 125 is formed on a portion of the third conductive-type semiconductor layer 1221 exposed by the third mesa structure 124, wherein the third conductive-type electrode 125 is electrically connected to the third conductive-type semiconductor layer 1221.

Wherein the third conductive type electrode 125 is an n-type electrode corresponding to the n-type GaN layer. Specifically, one or more metals of Cr/Al/Ti/Au may be fabricated on the exposed surface of the third conductive type semiconductor layer 1221 to form the third conductive type electrode 125, so that the third conductive type electrode 125 is an n-type electrode, and the third conductive type electrode 125 is electrically connected to the third conductive type semiconductor layer 1221, for example, in this embodiment, the third conductive type electrode 125 is electrically connected to the third conductive type semiconductor layer 1221 by directly contacting.

S226: a fourth conductive-type electrode 126 is formed on a side of the second current diffusion layer 123 away from the fourth conductive-type semiconductor layer 1223, wherein the fourth conductive-type electrode 126 is electrically connected to the second current diffusion layer 123.

Wherein, the fourth conductive type electrode 126 is a p-type electrode corresponding to the p-type GaN layer. Specifically, the fourth conductivity-type electrode 126 may be formed by forming Ti/Au metal on the side of the second current diffusion layer 123 away from the fourth conductivity-type semiconductor layer 1223, so that the fourth conductivity-type electrode 126 is a p-type electrode, the fourth conductivity-type electrode 126 is electrically connected to the second current diffusion layer 123, and the second current diffusion layer 123 is electrically connected to the fourth conductivity-type semiconductor layer 1223.

Specifically, a photoresist may be coated on a portion of the third conductive type semiconductor layer 1221 exposed by the third mesa structure 124 and a side of the second current diffusion layer 123 away from the fourth conductive type semiconductor layer 1223, areas of the third conductive type electrode 125 and the fourth conductive type electrode 126 are defined by exposure and development, and corresponding metal layers are evaporated or sputtered to form the third conductive type electrode 125 and the fourth conductive type electrode 126.

Referring to fig. 5, 12 and 16, in an embodiment, step S3:

s321: forming SiO on a portion of the surface of the second micro-LED chip 120₂A passivation layer 140.

Specifically, SiO is deposited on a portion of the surface of the second micro-LED chip 120 using Plasma Enhanced Chemical Vapor Deposition (PECVD)₂And a passivation layer 140 to define a fourth mesa structure and a transfer link anchor.

S322: to the non-covered SiO₂The second buffer layer 121 of the passivation layer 140 and the second light emitting epitaxial layer 122 are patterned to form a fourth mesa structure (not shown) and a transfer link anchor (not shown) partially exposing the second substrate 200.

Specifically, an etching process is applied to remove a portion of the second buffer layer 121 and the second light emitting epitaxial layer 122 to form a fourth mesa structure and a transfer connection anchor partially exposing the second substrate 200.

The etching process may include dry etching, wet etching, or a combination thereof. The etching process may include various etching steps, each of which is designed to use a specific etchant to effectively remove the corresponding second buffer layer 121 and third conductive type semiconductor layer 1221.

For example, the non-coated SiO layer is formed by ICP dry etching₂A region of the passivation layer 140 is etched to the surface of the second substrate 200.

S323: removing the second substrate 200 and SiO₂ A passivation layer 140.

The second substrate 200 is etched by wet etching to separate the second micro-LED chip 120 from the second substrate 200, for example, by usingThe Si substrate was corroded with a 60% by mass KOH aqueous solution. Then using CHF by an inductive coupling type plasma etching machine₃Gas to residual SiO₂Etching the passivation layer 140, and performing wet etching by using a BOE solution to completely remove the residual SiO₂And passivating layer 140, i.e. the second micro-LED chip 120 to be transferred.

S324: the second buffer layer 121 of the second micro-LED chip 120 and the first substrate 100 are bonded by an adhesive material.

In step S324, the adhesive material is an ultraviolet curing adhesive. The first substrate 100 and the second buffer layer 121 of the second micro-LED chip 120 are bonded by using an ultraviolet curing adhesive, and the ultraviolet curing adhesive is cured by using ultraviolet irradiation to form a first cured layer 150. Preferably, the wavelength of the ultraviolet light is 365 nm.

Referring to fig. 6 and 13, in an embodiment, step S2 includes:

s231: a high-resistance GaN buffer layer 131 is formed on one side of the third substrate 300.

S232: the GaN channel layer 132 is formed on a side of the high-resistance GaN buffer layer 131 away from the third substrate 300.

S233: an AlGaN barrier layer 133 is formed on the GaN channel layer 132 on the side away from the high-resistance GaN buffer layer 131.

Specifically, MOCVD may be adopted to sequentially grow the high-resistance GaN buffer layer 131, the GaN channel layer 132, and the AlGaN barrier layer 133 on one side of the third substrate 300. The thickness of the third substrate 300 is 800-1200 microns, the thickness of the GaN high-resistance buffer layer is 1-10 microns, the thickness of the GaN channel layer 132 is 50-150 nanometers, and the thickness of the AlGaN barrier layer 133 is 10-50 nanometers. Preferably, the thickness of the third substrate 300 is 1000 micrometers, the thickness of the GaN high resistance buffer layer is 4 micrometers, the thickness of the GaN channel layer 132 is 100 nanometers, and the thickness of the AlGaN barrier layer 133 is 30 nanometers.

Referring to fig. 7 and 14, in an embodiment, step S3 includes:

s331: the third substrate 300 is removed.

The third substrate 300 is etched by means of wet etching to realize the peeling of the GaN-based HEMT130 from the third substrate 300, for example, a Si substrate is etched by using a KOH aqueous solution with a mass fraction of 60%.

S332: the high-resistance GaN buffer layer 131 of the GaN-based HEMT130 and the first substrate 100 are bonded through an adhesive material.

In step S332, the adhesive material is an ultraviolet curing adhesive. The first substrate 100 and the high-resistance GaN buffer layer 131 of the GaN-based HEMT130 are bonded by ultraviolet curing glue, and the ultraviolet curing glue is cured by ultraviolet irradiation to form a second cured layer 160. Preferably, the wavelength of the ultraviolet light is 365 nm.

Referring to fig. 8 and 14, in an embodiment, step S4 includes:

s41: SiO is formed on the AlGaN barrier layer 133 on the side away from the GaN channel layer 132₂A passivation layer 140.

In this example, SiO₂The passivation layer 140 serves as an electrical insulation layer, and a PECVD process is used to deposit SiO on the AlGaN barrier layer 133 at a side away from the GaN channel layer 132₂A passivation layer 140.

S42: in SiO according to the positions and shapes of source electrode 134, drain electrode 135 and gate electrode 136₂The passivation layer 140 is formed with a through hole.

In particular, in SiO₂The passivation layer 140 is coated with a photoresist on its surface, exposed to light by an ultraviolet lithography machine, and developed with 0.5% NaOH solution according to the positions and shapes of the source electrode 134, the drain electrode 135, and the gate electrode 136, thereby defining the source electrode 134, the drain electrode 135, and the gate electrode 136 regions.

The SiO is realized by combining the ICP dry etching and the solution wet etching₂The passivation layer 140 is formed with a through hole. For example, CHF is used₃Carrying out ICP dry etching on the gas, and then carrying out wet etching on the gas by using BOE solution to form SiO film₂The passivation layer 140 is formed with a through hole.

S43: in SiO₂The through-hole regions of the passivation layer 140 deposit a source electrode 134, a drain electrode 135, and a gate electrode 136, respectively, wherein the first conductive type electrode 115 and the drain electrode 135 are electrically connected.

Specifically, the source electrode 134, the drain electrode 135, and the gate electrode 136 are deposited on the through hole region by using a magnetron sputtering or the like, wherein the first conductive type electrode 115 and the drain electrode 135 are electrically connected to achieve electrical connection between the first micro-LED chip 110 and the GaN-based HEMT130 in the integrated device 10.

Wherein, the source electrode 134, the drain electrode 135 and the gate electrode 136 are made of Ti, Al, Ni, Au, Ag, Pt, TiN_XAt least one of (1).

In the above embodiment, the photoresist may be S1818 photoresist, and the S1818 photoresist may be used as an etching mask. In addition, the residual photoresist may be removed using an acetone solution.

Referring to fig. 9-10 and fig. 15-16, the present application also proposes an integrated device 10 for bidirectional communication, where the integrated device 10 for bidirectional communication can be prepared by the preparation method of the above embodiment.

The integrated device 10 for bidirectional communication includes: a first substrate 100, a first micro-LED chip 110, a second micro-LED chip 120, and a GaN-based HEMT 130. The first micro-LED chip 110 is disposed on the first substrate 100, the second micro-LED chip 120 is disposed on the first reserved region 101 of the first substrate 100, the GaN-based HEMT130 is disposed on the second reserved region 102 of the first substrate 100, and the first micro-LED chip 110 is electrically connected to the GaN-based HEMT 130.

The first micro-LED chip 110 serves as a light emitter in the integrated device 10, the second micro-LED chip 120 serves as a light detector in the integrated device 10, and the GaN-based HEMT130 serves as a high-frequency switch in the integrated device 10 for controlling the on/off of the light emitter (i.e., the first micro-LED chip 110).

The central emission wavelength of any emission point in the emission region of the first micro-LED chip 110 is smaller than the central emission wavelength of any emission point in the emission region of the second micro-LED chip 120. The central luminous wavelength of any luminous point of the active luminous layers of the light emitter and the light detector is controlled, so that the Stokes displacement effect of micro-LEDs can be effectively reduced, the light detector obtains higher responsivity, and the communication performance is better.

Different from the situation of the prior art, the integrated device 10 for bidirectional communication integrates two different

micro-LED chips

110 and 120 and one GaN-based HEMT130 on the same substrate to prepare the integrated device 10 for bidirectional communication, and can be used for developing a semiconductor integrated device with high integration, high efficiency and reliability by combining the advantages of the micro-LEDs 110 and 120 and the GaN-based HEMT130, so that the application scene is wider. Further, the integrated device 10 can greatly simplify the packaging complexity and reduce parasitic elements; by reducing the connecting wires, the parasitic resistance and capacitance can be greatly reduced, and the efficiency and the response time of the capacitor can be further improved.

Further, a first cured layer 150 is disposed between the second micro-LED chip 120 and the first substrate 100, and a second cured layer 160 is disposed between the GaN-based HEMT130 and the first substrate 100.

In one embodiment, the first micro-LED chip 110 includes: a first buffer layer 111, a first light emitting epitaxial layer 112, a first current diffusion layer 113, a first conductive type electrode 115, and a second conductive type electrode 116.

The first buffer layer 111 is disposed on the first substrate 100, the first light emitting epitaxial layer 112 is disposed on a side of the first buffer layer 111 away from the first substrate 100, and the first light emitting epitaxial layer 112 includes a first conductive type semiconductor layer 1121, a first active light emitting layer 1122, and a second conductive type semiconductor layer 1123 which are sequentially stacked and disposed on a side of the first buffer layer 111. The first current diffusion layer 113 is disposed on a side of the second conductive type semiconductor layer 1123 away from the first active light emitting layer 1122, wherein at least a part of a light emitting region of the first light emitting epitaxial layer 112 includes at least: the first mesa structure 114 of the first conductive type semiconductor layer 1121 is partially exposed. The first conductivity type electrode 115 is disposed on a portion of the first conductivity type semiconductor layer 1121 exposed by the first mesa structure 114, wherein the first conductivity type electrode 115 is electrically connected to the first conductivity type semiconductor layer 1121. The second conductivity-type electrode 116 is disposed on a side of the first current diffusion layer 113 away from the second conductivity-type semiconductor layer 1123, wherein the second conductivity-type electrode 116 is electrically connected to the first current diffusion layer 113.

Specifically, the material of the first buffer layer 111 may be GaN. The first conductive type semiconductor layer 1121 is an n-type GaN layer, and may be a GaN layer doped with at least one of Si, Ge, and Sn. The first active light emitting layer 1122 may be a single-layer quantum well (SQW) or a multi-layer quantum well (MQW). The second conductive type semiconductor layer 1123 is a p-type GaN layer, and may Be specifically a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.

The thickness of the first buffer layer 111 is 1 to 5 micrometers, the thickness of the first conductive type semiconductor layer 1121 is 1 to 4 micrometers, the thickness of the first active light emitting layer 1122 is 0.05 to 0.5 micrometers, and the thickness of the second conductive type semiconductor layer 1123 is 0.1 to 1 micrometer. Preferably, the thickness of the first buffer layer 111 is 3 micrometers, the thickness of the first conductive type semiconductor layer 1121 is 2 micrometers, the thickness of the first active light emitting layer 1122 is 0.17 micrometers, and the thickness of the second conductive type semiconductor layer 1123 is 0.5 micrometers.

Further, the first conductive type electrode 115 is an n-type electrode corresponding to the n-type GaN layer. Specifically, one or more metals of Cr/Al/Ti/Au may be fabricated on the exposed surface of the first conductivity-type semiconductor layer 1121 to form the first conductivity-type electrode 115, so that the first conductivity-type electrode 115 is an n-type electrode, and the first conductivity-type electrode 115 is electrically connected to the first conductivity-type semiconductor layer 1121, for example, in this embodiment, the first conductivity-type electrode 115 is electrically connected to the first conductivity-type semiconductor layer 1121 in a direct contact manner.

The second conductive type electrode 116 is a p-type electrode corresponding to the p-type GaN layer. Specifically, the second conductivity-type electrode 116 may be formed by forming Ti/Au metal on the side of the first current diffusion layer 113 away from the second conductivity-type semiconductor layer 1123, so that the second conductivity-type electrode 116 is a p-type electrode, and the second conductivity-type electrode 116 is electrically connected to the first current diffusion layer 113.

The first current diffusion layer 113 may employ a transparent conductive material, such as indium tin oxide. In other embodiments, the first current spreading layer 113 may be a metal transparent thin layer including nickel, gold, or other suitable metal.

In one embodiment, at least a portion of the light emitting area of the first light emitting epitaxial layer 112 further comprises: the second mesa structure 117 of the first substrate 100 is partially exposed. The first reserved area 101 and the second reserved area 102 are located on the second mesa 117.

In one embodiment, the second micro-LED chip 120 includes: a second buffer layer 121, a second light emitting epitaxial layer 122, a second current diffusion layer 123, a third conductive type electrode 125, and a fourth conductive type electrode 126.

The second buffer layer 121 is disposed on the first substrate 100, the second light emitting epitaxial layer 122 is disposed on a side of the second buffer layer 121 remote from the second substrate 200, and the second light emitting epitaxial layer 122 includes a third conductive type semiconductor layer 1221, a second active light emitting layer 1222, and a fourth conductive type semiconductor layer 1223, which are sequentially stacked and disposed on a side of the second buffer layer 121. The second current diffusion layer 123 is disposed on a side of the fourth conductive type semiconductor layer 1223 away from the second active light emitting layer 1222, wherein at least a portion of a light emitting region of the second light emitting epitaxial layer 122 at least includes: the third mesa structure 124 of the third conductive type semiconductor layer 1221 is partially exposed. The third conductive-type electrode 125 is disposed on a portion of the third conductive-type semiconductor layer 1221 exposed by the third mesa structure 124, wherein the third conductive-type electrode 125 is electrically connected to the third conductive-type semiconductor layer 1221. The fourth conductive type electrode 126 is disposed on a side of the second current diffusion layer 123 away from the fourth conductive type semiconductor layer 1223, wherein the fourth conductive type electrode 126 is electrically connected to the second current diffusion layer 123, and the second current diffusion layer 123 is electrically connected to the fourth conductive type semiconductor layer 1223.

Specifically, the material of the second buffer layer 121 may be any one or a combination of AlN, AlGaN, and GaN. The third conductive type semiconductor layer 1221 is an n-type GaN layer, and may be a GaN layer doped with at least one of Si, Ge, and Sn. The second active light emitting layer 1222 may be a Single Quantum Well (SQW) or a multi-layer quantum well (MQW). The fourth conductive type semiconductor layer 1223 is a p-type GaN layer, and may Be specifically a GaN layer doped with at least one of Mg, Zn, Be, Ca, Sr, and Ba.

The second current diffusion layer 123 may employ a transparent conductive material, such as Indium Tin Oxide (ITO). In other embodiments, the second current spreading layer 123 may be a thin metal transparent layer comprising nickel, gold, or other suitable metal.

The thickness of the second substrate 200 is 800 micrometers, the thickness of the second buffer layer 121 is 0.5-5 micrometers, the thickness of the third conductive type semiconductor layer 1221 is 0.1-5 micrometers, the thickness of the second active light emitting layer 1222 is 0.01-0.5 micrometers, and the thickness of the fourth conductive type semiconductor layer 1223 is 0.05-0.5 micrometers. Preferably, the thickness of the second substrate 200 is 600 micrometers, the thickness of the second buffer layer 121 is 1.2 micrometers, the thickness of the third conductive type semiconductor layer 1221 is 1 micrometer, the thickness of the second active light emitting layer 1222 is 0.1 micrometer, and the thickness of the fourth conductive type semiconductor layer 1223 is 0.15 micrometer.

Further, the third conductive type electrode 125 is an n-type electrode corresponding to the n-type GaN layer. Specifically, the third conductivity-type electrode 125 may be formed by forming one or more metals of Cr/Al/Ti/Au on the exposed surface of the third conductivity-type semiconductor layer 1221, so that the third conductivity-type electrode 125 is an n-type electrode, and the third conductivity-type electrode 125 is electrically connected to the third conductivity-type semiconductor layer 1221, for example, in this embodiment, the third conductivity-type electrode 125 is electrically connected to the third conductivity-type semiconductor layer 1221 by directly contacting.

The fourth conductive type electrode 126 is a p-type electrode corresponding to the p-type GaN layer. Specifically, the fourth conductivity-type electrode 126 may be formed by forming Ti/Au metal on the side of the second current diffusion layer 123 away from the fourth conductivity-type semiconductor layer 1223, so that the fourth conductivity-type electrode 126 is a p-type electrode, the fourth conductivity-type electrode 126 is electrically connected to the second current diffusion layer 123, and the second current diffusion layer 123 is electrically connected to the fourth conductivity-type semiconductor layer 1223.

It should be noted that, during long-term research and development, the inventors of the present application found that, if the light emitter (i.e., the first micro-LED chip 110) and the light detector (i.e., the second micro-LED chip 120) in the integrated device 10 both use the same active light emitting layer, the light spectrum detected by the light detector is not at the optimal absorption wavelength thereof according to the stokes shift effect of the micro-LEDs, thereby affecting the responsivity of the light detector. In order to improve the responsivity of the optical detector, the central light-emitting wavelength of any light-emitting point in the light-emitting area of the first micro-LED chip 110 is smaller than the central light-emitting wavelength of any light-emitting point in the light-emitting area of the second micro-LED chip 120.

In one embodiment, the GaN-based HEMT130 includes: a high-resistance GaN buffer layer 131, a GaN channel layer 132, and an AlGaN barrier layer 133. The high-resistance GaN buffer layer 131 is disposed on the side of the third substrate 300, the GaN channel layer 132 is disposed on the side of the high-resistance GaN buffer layer 131 away from the third substrate 300, and the AlGaN barrier layer 133 is disposed on the side of the GaN channel layer 132 away from the high-resistance GaN buffer layer 131.

In one embodiment, the GaN-based HEMT130 further comprises: a source electrode 134, a drain electrode 135 and a gate electrode 136, wherein the source electrode 134, the drain electrode 135 and the gate electrode 136 are distributed at intervals on a side of the AlGaN barrier layer 133 away from the GaN channel layer 132, and the first conductivity type electrode 115 and the drain electrode 135 are electrically connected.

Wherein the source electrode 134, the drain electrode 135 and the gate electrode 136 are made of Ti, Al, Ni, Au, Ag, Pt, TiN_XAt least one of (1).

The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.

Claims

1. A method of making an integrated device for two-way communication, the method comprising:

providing a first substrate, a second substrate and a third substrate;

forming a first micro-LED chip on the first substrate, forming a first reserved region for placing the second micro-LED chip and a second reserved region for placing the GaN-based HEMT on the first substrate, forming a second micro-LED chip on the second substrate, and forming the GaN-based HEMT on the third substrate;

removing the second substrate and transferring the second micro-LED chip to the first reserved region, removing the third substrate and transferring the GaN-based HEMT to the second reserved region;

establishing electric connection between the first micro-LED chip and the GaN-based HEMT;

the central light-emitting wavelength of any light-emitting point in the light-emitting area of the first micro-LED chip is smaller than that of any light-emitting point in the light-emitting area of the second micro-LED chip.

2. The method of claim 1, wherein the forming of the first micro-LED chip on the first substrate comprises:

forming a first buffer layer on one side of the first substrate;

forming a first light-emitting epitaxial layer on one side of the first buffer layer, which is far away from the first substrate, wherein the first light-emitting epitaxial layer comprises a first conductivity type semiconductor layer, a first active light-emitting layer and a second conductivity type semiconductor layer which are sequentially stacked and arranged on one side of the first buffer layer;

forming a first current diffusion layer on one side of the second conductivity type semiconductor layer far away from the first active light-emitting layer;

patterning the first current diffusion layer, the second conductive type semiconductor layer and the first active light emitting layer to form a first mesa structure partially exposing the first conductive type semiconductor layer;

forming a first conductive type electrode on a portion of the first conductive type semiconductor layer exposed by the first mesa structure, wherein the first conductive type electrode is electrically connected to the first conductive type semiconductor layer;

and forming a second conductive type electrode on the side of the first current diffusion layer far away from the second conductive type semiconductor layer, wherein the second conductive type electrode is electrically connected with the first current diffusion layer.

3. The method of claim 2, wherein the forming of the first reserved region for placing the second micro-LED chip and the second reserved region for placing the GaN-based HEMT on the first substrate comprises:

patterning the first conductive type semiconductor layer and the first buffer layer to form a second mesa structure partially exposing the first substrate;

forming the first and second reserved regions on a portion of the first substrate exposed by the second mesa structure.

4. The method according to claim 2, wherein the first conductivity type semiconductor layer is an n-type GaN layer, and the second conductivity type semiconductor layer is a p-type GaN layer.

5. The method of claim 1, wherein forming a second micro-LED chip on the second substrate comprises:

forming a second buffer layer on one side of the second substrate;

forming a second light-emitting epitaxial layer on one side of the second buffer layer, which is far away from the second substrate, wherein the second light-emitting epitaxial layer comprises a third conductive type semiconductor layer, a second active light-emitting layer and a fourth conductive type semiconductor layer which are sequentially stacked and arranged on one side of the second buffer layer;

forming a second current diffusion layer on one side of the fourth conductivity type semiconductor layer far away from the second active light-emitting layer;

patterning the second current diffusion layer, the fourth conductive type semiconductor layer and the second active light emitting layer to form a third mesa structure partially exposing the third conductive type semiconductor layer;

forming a third conductive type electrode on a portion of the third conductive type semiconductor layer exposed by the third mesa structure, wherein the third conductive type electrode is electrically connected to the third conductive type semiconductor layer;

forming a fourth conductivity type electrode on a side of the second current diffusion layer away from the fourth conductivity type semiconductor layer, wherein the fourth conductivity type electrode is electrically connected to the second current diffusion layer.

6. The method of claim 5, wherein the removing the second substrate and transferring the second micro-LED chip to the first reserved area comprises:

forming SiO on partial surface of the second micro-LED chip₂A passivation layer;

to the SiO not covered₂Patterning the second buffer layer of the passivation layer and the second light-emitting epitaxial layer to form a fourth mesa structure and a transfer connection anchor, wherein the fourth mesa structure and the transfer connection anchor partially expose the second substrate;

removing the second substrate and the SiO₂A passivation layer;

bonding the second buffer layer of the second micro-LED chip and the first substrate through an adhesive material.

7. The method according to claim 5, wherein the third conductivity type semiconductor layer is an n-type GaN layer, and the fourth conductivity type semiconductor layer is a p-type GaN layer.

8. The method according to claim 1, wherein the forming the GaN-based HEMT on the third substrate comprises:

forming a high-resistance GaN buffer layer on one side of the third substrate;

forming a GaN channel layer on one side of the high-resistance GaN buffer layer, which is far away from the third substrate;

and forming an AlGaN barrier layer on one side of the GaN channel layer, which is far away from the high-resistance GaN buffer layer.

9. The method of claim 8, wherein the removing the third substrate and transferring the GaN-based HEMT to the second reserved region comprises:

removing the third substrate;

bonding the high-resistance GaN buffer layer of the GaN-based HEMT and the first substrate by an adhesive material.

10. The method according to any one of claims 6 or 9,

the adhesive material is ultraviolet curing glue.

11. The method of claim 8, wherein the establishing the electrical connection of the first micro-LED chip to the GaN-based HEMT comprises:

forming SiO on one side of the AlGaN barrier layer away from the GaN channel layer₂A passivation layer;

in the SiO layer, the source electrode, the drain electrode and the gate electrode are arranged in the same shape₂The passivation layer is provided with a through hole;

in the SiO₂And respectively depositing the source electrode, the drain electrode and the gate electrode in the through hole region of the passivation layer, wherein the first conductive type electrode and the drain electrode are electrically connected.

12. The method of claim 1,

the material of the first substrate is at least one of sapphire, Si, GaN or SiC;

the material of the second substrate is Si;

the material of the third substrate is Si.

13. An integrated device for bidirectional communication, the integrated device comprising:

a first substrate;

a first micro-LED chip disposed on the first substrate;

the second micro-LED chip is arranged on the first reserved area of the first substrate;

the GaN-based HEMT is arranged on the second reserved region of the first substrate, and the first micro-LED chip is electrically connected with the GaN-based HEMT;

14. The integrated device of claim 13, wherein the first micro-LED chip comprises:

a first buffer layer disposed on the first substrate;

the first light-emitting epitaxial layer is arranged on one side, far away from the first substrate, of the first buffer layer and comprises a first conductivity type semiconductor layer, a first active light-emitting layer and a second conductivity type semiconductor layer which are sequentially stacked and arranged on one side of the first buffer layer;

a first current diffusion layer disposed on a side of the second conductivity type semiconductor layer away from the first active light emitting layer, wherein at least a part of a light emitting region of the first light emitting epitaxial layer includes at least: a first mesa structure partially exposing the first conductive type semiconductor layer;

a first conductive type electrode disposed on a portion of the first conductive type semiconductor layer exposed by the first mesa structure, wherein the first conductive type electrode is electrically connected to the first conductive type semiconductor layer;

and a second conductivity type electrode disposed on a side of the first current diffusion layer away from the second conductivity type semiconductor layer, wherein the second conductivity type electrode is electrically connected to the first current diffusion layer.

15. The integrated device of claim 14, wherein at least a portion of the light emitting region of the first light emitting epitaxial layer further comprises: a second mesa structure partially exposing the first substrate;

the first reserved area and the second reserved area are located on a second mesa structure.

16. The integrated device of claim 13, wherein the second micro-LED chip comprises:

a second buffer layer disposed on the first substrate;

the second light-emitting epitaxial layer is arranged on one side, far away from the second substrate, of the second buffer layer and comprises a third conductivity type semiconductor layer, a second active light-emitting layer and a fourth conductivity type semiconductor layer which are sequentially stacked and arranged on one side of the second buffer layer;

a second current diffusion layer disposed on a side of the fourth conductivity type semiconductor layer away from the second active light emitting layer, wherein at least a part of a light emitting region of the second light emitting epitaxial layer at least includes: a third mesa structure partially exposing the third conductive type semiconductor layer;

a third conductive type electrode disposed on a portion of the third conductive type semiconductor layer exposed by the third mesa structure, wherein the third conductive type electrode is electrically connected to the third conductive type semiconductor layer;

and a fourth conductive type electrode disposed on a side of the second current diffusion layer away from the fourth conductive type semiconductor layer, wherein the fourth conductive type electrode is electrically connected to the second current diffusion layer.

17. The integrated device of claim 13, wherein the GaN-based HEMT comprises:

the high-resistance GaN buffer layer is arranged on one side of the third substrate;

the GaN channel layer is arranged on one side, far away from the third substrate, of the high-resistance GaN buffer layer;

and the AlGaN barrier layer is arranged on one side of the GaN channel layer, which is far away from the high-resistance GaN buffer layer.

18. The integrated device of claim 17,

the GaN-based HEMT further includes: the source electrode, the drain electrode and the gate electrode are distributed on one side, away from the GaN channel layer, of the AlGaN barrier layer at intervals, wherein the first conduction type electrode is electrically connected with the drain electrode.

19. The integrated device of claim 13,

a first curing layer is arranged between the second micro-LED chip and the first substrate, and a second curing layer is arranged between the GaN-based HEMT and the first substrate.