CN112234050A - Multi-chip integrated circuit packaging structure - Google Patents
Multi-chip integrated circuit packaging structure Download PDFInfo
- Publication number
- CN112234050A CN112234050A CN202010999387.1A CN202010999387A CN112234050A CN 112234050 A CN112234050 A CN 112234050A CN 202010999387 A CN202010999387 A CN 202010999387A CN 112234050 A CN112234050 A CN 112234050A
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- China
- Prior art keywords
- chip
- integrated circuit
- front surface
- clamping groove
- groove
- Prior art date
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Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 17
- 238000002844 melting Methods 0.000 claims abstract description 14
- 230000008018 melting Effects 0.000 claims abstract description 14
- 230000017525 heat dissipation Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 4
- 238000003466 welding Methods 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 2
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 230000009471 action Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005485 electric heating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/62—Protection against overvoltage, e.g. fuses, shunts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
- H01L23/467—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing gases, e.g. air
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
Abstract
The invention discloses a multi-chip integrated circuit packaging structure which comprises an organic carrier plate, wherein spherical bumps are fixedly arranged on the front surface of the organic carrier plate, an insulating plate is fixedly arranged at the central position of the front surface of the organic carrier plate, a clamping groove is formed in the periphery of the inner side of the front surface of the insulating plate, notches are formed in the corners of the periphery of the front surface of the clamping groove, a left chip and a right chip are fixedly arranged on the inner side of the front surface of the clamping groove, chip pins are fixedly connected to the inner sides of the left chip and the right chip, a melting point is formed in the central position of the. This multi-chip integrated circuit packaging structure openly fixes the ball-type bump of establishing through organic support plate, has improved the equipment and has assembled the product rate, has improved the electric heat performance, and very big dwindle packaging structure's thickness and width, make parasitic parameter reduce, signal transmission delay diminishes, and the rate of utilization improves greatly, and the reliability is more perfect, accords with future development trend.
Description
Technical Field
The invention relates to the technical field of packaging structures of integrated circuits, in particular to a multi-chip integrated circuit packaging structure.
Background
In the fabrication of integrated circuits, chips are obtained by the steps of wafer fabrication, forming integrated circuits, and dicing wafers. After the integrated circuit of the wafer is manufactured, the chips formed by cutting the wafer can be electrically connected to the loader outwards; the carrier can be a lead frame or a substrate, and the chip can be electrically connected to the carrier by wire bonding or flip chip bonding. The chip packaging technology is a process technology for wrapping a chip to avoid the chip from contacting with the outside and preventing the chip from being damaged by the outside.
Impurities and undesirable gases in the air, and even water vapor, can corrode the precision circuitry on the chip, thereby causing degradation of electrical performance. When a plurality of chips are placed together for work, heat imbalance easily occurs, local temperature is too high, and a single chip has problems. Different packaging technologies are widely different in manufacturing processes and technologies, and play a crucial role in performance of the memory chip after packaging.
Disclosure of Invention
The present invention is directed to a multi-chip integrated circuit package structure, which solves the above-mentioned problems of the prior art.
In order to solve the technical problems, the invention provides the following technical scheme: the multi-chip integrated circuit packaging structure comprises an organic carrier plate, spherical bumps, an insulating plate, a clamping groove, a notch, a left chip, a right chip, chip pins, a melting point, a plastic package body, a clamping groove column, a top pin hole and a heat dissipation opening, wherein the insulating plate is fixedly arranged at the center of the front surface of the organic carrier plate, the thickness and the width of the packaging structure are greatly reduced, parasitic parameters are reduced, signal transmission delay is reduced, the utilization rate is greatly improved, the reliability is more perfect, and the multi-chip integrated circuit packaging structure accords with the future development trend.
Further, the draw-in groove has been seted up all around to the positive inboard of the insulating board of institute of pollution, the notch has been seted up to the positive corner all around of draw-in groove, makes things convenient for the joint of plastic-sealed body on the draw-in groove, and the notch that the positive corner was seted up all around of draw-in groove is equipped with everywhere altogether, and symmetric distribution is around the draw-in groove is positive, and the diameter size is unanimous, avoids external environment to the influence of chip, prevents.
Furthermore, a left chip and a right chip are fixedly mounted on the inner side of the front face of the clamping groove, and two ends of the left chip and the right chip are connected to the inner side of the front face of the clamping groove through metal wires in a pressure welding mode and are connected with the organic carrier plate, so that the working benefit of the integrated circuit is improved, and the performance of the chip is enhanced.
Furthermore, the inner sides of the left chip and the right chip are fixedly connected with chip pins, the central positions of the chip pins are provided with melting points, the left chip and the right chip are fixedly connected with the chip pins, and the melting points arranged at the central positions of the chip pins are provided with a plurality of parts, so that the phenomenon that one chip is unexpected when working can be effectively prevented, and the other chip is not influenced by the chip pins and works normally.
Further, the positive swing joint of draw-in groove has the plastic-sealed body, corner fixed mounting all around of plastic-sealed body bottom has the draw-in groove post, can be effectively convenient with the draw-in groove chucking, avoid receiving external force factor and lead to droing, make inside chip receive the condition of damage.
Further, thimble hole and thermovent have been seted up to the positive inboard of plastic-sealed body, and the thermovent shape that the positive inboard of plastic-sealed body was seted up is the cuboid shape, is connected with the thimble hole, is located the plastic-sealed body surface, and sets up the serial number in the thimble hole, can effectively give off the heat that inside chip during operation produced, avoids causing the damage to the chip because of inside heat is too big, makes its electrical property descend.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, the spherical salient points fixedly arranged on the front surface of the organic carrier plate are arranged in an array mode, so that the assembly yield can be effectively improved, the electric heating performance is improved, the thickness and the width of the packaging structure are greatly reduced, parasitic parameters are reduced, the signal transmission delay is reduced, the utilization rate is greatly improved, the reliability is more perfect, and the future development trend is met; the plurality of chips are connected together through the chip pins fixedly connected with the inner sides of the left chip and the right chip, so that the working efficiency is improved, and the melting point arranged in the center of the chip pin can prevent one chip from being automatically disconnected from the other chip after the other chip has a problem, so that the loss is reduced; the plastic package body movably connected with the front side of the clamping groove can effectively prevent the chip from being influenced by the external environment, so that the electrical performance is reduced, and the heat generated during the working of the chip can be timely dissipated by the heat dissipation port arranged on the surface, so that the problem of damage is prevented.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic view of the overall structure of the front face of the present invention;
FIG. 2 is an enlarged schematic view of the structure at A in FIG. 1;
FIG. 3 is a schematic diagram of a lateral organic carrier structure according to the present invention;
FIG. 4 is a schematic view of the plastic package structure viewed from above;
FIG. 5 is a schematic structural diagram of a side view of the plastic package body of the present invention;
in the figure: the chip packaging structure comprises an organic carrier plate 1, spherical salient points 2, an insulating plate 3, a clamping groove 4, a notch 5, a chip 6 left, a chip 7 right, chip pins 8, a melting point 9, a plastic package body 10, a clamping groove column 11, a pinhole 12 and a heat dissipation opening 13.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1-5, the present invention provides the following technical solutions: the multi-chip integrated circuit packaging structure comprises an organic carrier plate 1, spherical salient points 2, an insulating plate 3, a clamping groove 4, a notch 5, a left chip 6, a right chip 7, chip pins 8, a melting point 9, a plastic package body 10, clamping groove columns 11, a top pin hole 12 and a heat dissipation port 13, wherein the insulating plate 3 is fixedly arranged at the center of the front surface of the organic carrier plate 1;
the periphery of the inner side of the front surface of the insulating plate 3 is provided with clamping grooves 4, notches 5 are formed in the peripheral corners of the front surface of the clamping grooves 4, so that the plastic package body 10 can be conveniently clamped on the clamping grooves 4, the notches 5 formed in the peripheral corners of the front surface of the clamping grooves 4 are arranged in four places, are symmetrically distributed around the front surface of the clamping grooves 4, and have consistent diameter and size, so that the influence of external environment on a chip is avoided, and the phenomenon of damage is prevented;
a left chip 6 and a right chip 7 are fixedly arranged on the inner side of the front surface of the clamping groove 4, and two ends of the left chip 6 and the right chip 7 are connected to the inner side of the front surface of the clamping groove 4 through metal wires in a pressure welding manner and connected with the organic carrier plate 1, so that the working benefit of the integrated circuit is improved, and the performance of the chips is enhanced;
the front surface of the clamping groove 4 is movably connected with a plastic package body 10, and clamping groove columns 11 are fixedly arranged at the corners around the bottom end of the plastic package body 10, so that the plastic package body can be effectively and conveniently clamped with the clamping groove 4, and the phenomenon that an internal chip is damaged due to falling off caused by external force factors is avoided;
the inner side of the front face of the plastic package body 10 is provided with a top pinhole 12 and a heat dissipation port 13, the heat dissipation port 13 arranged on the inner side of the front face of the plastic package body 10 is in a cuboid shape, is connected with the top pinhole 12 and is positioned on the surface of the plastic package body 10, and a serial number is arranged in the top pinhole 12, so that one chip can be effectively prevented from generating an accident situation when in work, and the other chip is not influenced by the accident situation and can normally work;
according to the multi-chip integrated circuit packaging structure, two ends of a left chip 6 and a right chip 7 are connected to the inner side of the front face of a clamping groove 4 through metal wire pressure welding and are connected with an organic carrier plate 1, clamping groove columns 11 fixedly installed at the peripheral corners of the bottom end of a plastic package body 10 are matched with notches 5 formed at the peripheral corners of the front face of the clamping groove 4, so that the chips are effectively prevented from being influenced by the external environment, the electrical performance is reduced, heat generated during the working of the chips can be timely dissipated through heat dissipation ports 13 formed in the surfaces of the chips, and the problem of damage is prevented; the spherical salient points 2 fixedly arranged on the front surface of the organic carrier plate 1 are arranged in an array mode, so that the assembly yield can be effectively improved, the electric heating performance is improved, the thickness and the width of a packaging structure are greatly reduced, parasitic parameters are reduced, the signal transmission delay is reduced, the utilization rate is greatly improved, the reliability is more perfect, and the future development trend is met; chip pin 8 through the inboard fixed connection of left chip 6 and right chip 7 links together a plurality of chips, has increased work efficiency, and the melting point 9 that chip pin 8 central point put and seted up can avoid one of them chip to go wrong after, and melting point 9 automatic disconnection is connected with another chip, reduces the loss.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. Multi-chip integrated circuit packaging structure, including organic support plate (1), ball-type bump (2), insulation board (3), draw-in groove (4), notch (5), left chip (6), right chip (7), chip pin (8), melting point (9), plastic-sealed body (10), draw-in groove post (11), thimble hole (12) and thermovent (13), its characterized in that: the center of the front surface of the organic carrier plate (1) is fixedly provided with an insulating plate (3).
2. The multi-chip integrated circuit package structure of claim 1, wherein: insulation board (3) openly inboard has seted up draw-in groove (4) all around, draw-in groove (4) openly corner all around has seted up notch (5), and notch (5) that draw-in groove (4) openly corner was seted up all around are equipped with everywhere, and symmetric distribution is around draw-in groove (4) openly, and the diameter size is unanimous.
3. The multi-chip integrated circuit package structure of claim 2, wherein: the clamping groove (4) is fixedly provided with a left chip (6) and a right chip (7) on the inner side of the front surface, and the two ends of the left chip (6) and the right chip (7) are connected to the inner side of the front surface of the clamping groove (4) through metal wire pressure welding and are connected with the organic carrier plate (1).
4. The multi-chip integrated circuit package structure of claim 3, wherein: the chip is characterized in that chip pins (8) are fixedly connected to the inner sides of the left chip (6) and the right chip (7), a melting point (9) is arranged at the center of each chip pin (8), the left chip (6) and the right chip (7) are fixedly connected through the chip pins (8), and the melting point (9) arranged at the center of each chip pin (8) is provided with a plurality of pins.
5. The multi-chip integrated circuit package structure of claim 2, wherein: the front of the clamping groove (4) is movably connected with a plastic package body (10), and clamping groove columns (11) are fixedly mounted at the corners around the bottom end of the plastic package body (10).
6. The multi-chip integrated circuit package structure of claim 5, wherein: the inner side of the front surface of the plastic package body (10) is provided with a thimble hole (12) and a heat dissipation port (13).
7. The multi-chip integrated circuit package structure of claim 6, wherein: the heat dissipation port (13) formed in the inner side of the front face of the plastic package body (10) is cuboid, is connected with the top pinhole (12) and is located on the surface of the plastic package body (10).
8. The multi-chip integrated circuit package structure of claim 7, wherein: and numbers are arranged in the thimble holes (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010999387.1A CN112234050A (en) | 2020-09-22 | 2020-09-22 | Multi-chip integrated circuit packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010999387.1A CN112234050A (en) | 2020-09-22 | 2020-09-22 | Multi-chip integrated circuit packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112234050A true CN112234050A (en) | 2021-01-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010999387.1A Pending CN112234050A (en) | 2020-09-22 | 2020-09-22 | Multi-chip integrated circuit packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112234050A (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000100990A (en) * | 1998-09-28 | 2000-04-07 | Rohm Co Ltd | Manufacture of semiconductor device |
| JP2003031724A (en) * | 2000-12-25 | 2003-01-31 | Hitachi Ltd | Semiconductor module |
| JP2003101080A (en) * | 2001-09-26 | 2003-04-04 | Ibiden Co Ltd | Board for ic chip mounting |
| US20060157843A1 (en) * | 2005-01-17 | 2006-07-20 | Sung-Wook Hwang | Stacked semiconductor package having interposing print circuit board |
| CN201038136Y (en) * | 2007-02-26 | 2008-03-19 | 番禺得意精密电子工业有限公司 | CPU device |
| US20140048324A1 (en) * | 2012-08-14 | 2014-02-20 | Charles W.C. Lin | Hybrid wiring board with built-in stopper, interposer and build-up circuitry |
| US20150342049A1 (en) * | 2014-05-22 | 2015-11-26 | KYOCERA Circuit Solutions, Inc. | Multi-piece wiring board and method for producing the same |
| CN106206510A (en) * | 2015-04-27 | 2016-12-07 | 南茂科技股份有限公司 | Multi-chip packaging structure, wafer-level chip packaging structure and method thereof |
| CN108766939A (en) * | 2018-08-15 | 2018-11-06 | 江苏盐芯微电子有限公司 | A kind of chip packaging device and packaging method |
| CN208478333U (en) * | 2018-07-12 | 2019-02-05 | 无锡市宏湖微电子有限公司 | A kind of multi-chip onboard audio power amplifier integrated circuit package structure |
| CN209544312U (en) * | 2019-05-16 | 2019-10-25 | 广东全芯半导体有限公司 | A kind of integrated circuit anti static device |
-
2020
- 2020-09-22 CN CN202010999387.1A patent/CN112234050A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000100990A (en) * | 1998-09-28 | 2000-04-07 | Rohm Co Ltd | Manufacture of semiconductor device |
| JP2003031724A (en) * | 2000-12-25 | 2003-01-31 | Hitachi Ltd | Semiconductor module |
| JP2003101080A (en) * | 2001-09-26 | 2003-04-04 | Ibiden Co Ltd | Board for ic chip mounting |
| US20060157843A1 (en) * | 2005-01-17 | 2006-07-20 | Sung-Wook Hwang | Stacked semiconductor package having interposing print circuit board |
| CN201038136Y (en) * | 2007-02-26 | 2008-03-19 | 番禺得意精密电子工业有限公司 | CPU device |
| US20140048324A1 (en) * | 2012-08-14 | 2014-02-20 | Charles W.C. Lin | Hybrid wiring board with built-in stopper, interposer and build-up circuitry |
| US20150342049A1 (en) * | 2014-05-22 | 2015-11-26 | KYOCERA Circuit Solutions, Inc. | Multi-piece wiring board and method for producing the same |
| CN106206510A (en) * | 2015-04-27 | 2016-12-07 | 南茂科技股份有限公司 | Multi-chip packaging structure, wafer-level chip packaging structure and method thereof |
| CN208478333U (en) * | 2018-07-12 | 2019-02-05 | 无锡市宏湖微电子有限公司 | A kind of multi-chip onboard audio power amplifier integrated circuit package structure |
| CN108766939A (en) * | 2018-08-15 | 2018-11-06 | 江苏盐芯微电子有限公司 | A kind of chip packaging device and packaging method |
| CN209544312U (en) * | 2019-05-16 | 2019-10-25 | 广东全芯半导体有限公司 | A kind of integrated circuit anti static device |
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