CN112234017A - Double-sided processing technology for glass carrier plate and wafer - Google Patents
Double-sided processing technology for glass carrier plate and wafer Download PDFInfo
- Publication number
- CN112234017A CN112234017A CN202011120980.0A CN202011120980A CN112234017A CN 112234017 A CN112234017 A CN 112234017A CN 202011120980 A CN202011120980 A CN 202011120980A CN 112234017 A CN112234017 A CN 112234017A
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- wafer
- glass carrier
- carrier plate
- face
- double
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
Abstract
The invention discloses a double-sided processing technology of a glass carrier plate and a wafer, and belongs to the field of wafer processing. A wafer double-side processing technology comprises the steps that femtosecond laser is used for scanning one end face of a glass carrier plate, a plurality of grooves are formed in the deconstructed end face of the glass carrier plate, each groove is enclosed to form a closed area, and the closed areas are concentrically arranged; bonding the other end face of the glass carrier plate with one end face of the wafer, and thinning the other end face of the wafer; etching to remove the glass carrier plate of the closed area, and bonding the glass carrier plate of the closed area and the wafer through laser; cleaning the bonding agent within the enclosed area using an oxygen plasma; carrying out double-sided process on the wafer; and fixing one end face of the wafer on a cutting die frame, and cutting the wafer.
Description
Technical Field
The disclosure relates to the field of wafer processing, in particular to a double-sided processing technology of a glass carrier plate and a wafer.
Background
In the conventional double-sided processing of wafers, there are two main process routes. One method is to bond a pseudo wafer with a ring-shaped edge on a glass carrier plate and then perform a wafer thinning process. And in the other process route, the traditional glass carrier plate is adopted for processing.
Both of these approaches have certain disadvantages, wherein in the tuo wafer process, the central portion of the wafer is bent and cannot be operated in a high rotation or vertical device, the horizontal type must gently contact the bottom surface of the wafer, otherwise the risk of wafer breakage is still high. In addition, in the wafer process, the wafer surface has a large step difference, so that the edge of the wafer is splashed when a photoresist or other coating processes are manufactured, the uniformity of the edge area is seriously affected, and the yield is greatly affected. In the conventional glass carrier process, it is difficult to process ultra-thin wafers.
Disclosure of Invention
Aiming at the defects of the prior art, the disclosure provides a double-sided processing technology of a glass carrier plate and a wafer.
The purpose of the disclosure can be realized by the following technical scheme:
a wafer double-side processing technology comprises the following steps:
scanning one end face of a glass carrier plate by using femtosecond laser, deconstructing one end face of the glass carrier plate to form a plurality of grooves, and connecting the heads of the grooves to enclose a closed area;
bonding the other end face of the glass carrier plate with one end face of the wafer, and thinning the other end face of the wafer;
etching to remove the glass carrier plate in the closed area, and bonding the glass carrier plate in the closed area with the wafer through laser;
cleaning the bonding agent within the enclosed area using an oxygen plasma.
Optionally, performing a double-sided process on the wafer after cleaning the bonding agent;
and fixing one end face of the wafer on a cutting die frame, and cutting the wafer.
Optionally, after the wafer is fixed on the cutting mold frame, oxygen plasma or laser is used.
Optionally, the closed region is fan-shaped, so that a cross-shaped supporting portion is formed at one end surface of the glass carrier plate.
A plurality of grooves are formed in one end face of the glass carrier plate through femtosecond laser scanning, the grooves are connected end to form a closed area, and the other end face of the glass carrier plate is bonded with a wafer.
Optionally, etching the glass carrier plate in the closed area to form a support part on one end surface of the glass carrier plate.
Optionally, the enclosed area is sector shaped.
Optionally, four support portions are arranged in the closed area to form a cross shape.
Drawings
The present disclosure is further described with reference to the following drawings.
Fig. 1 is a schematic structural view of a glass carrier after forming a trench according to the present disclosure;
fig. 2 is a schematic structural view of the etched glass carrier of the present disclosure;
FIG. 3 is a schematic view of a glass carrier bonded to a wafer according to the present disclosure;
fig. 4 is a schematic structural view of the glass carrier after the bonding agent is removed according to the present disclosure;
fig. 5 is a top view of a glass carrier plate in another example of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
In the description of the present disclosure, it is to be understood that the terms "aperture", "upper", "lower", "thickness", "top", "middle", "length", "inner", "periphery", and the like, indicate an orientation or positional relationship, merely for convenience in describing and simplifying the disclosure, and do not indicate or imply that the referenced component or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the disclosure.
As shown in fig. 1-4, in one example of the present disclosure, a wafer double-sided processing process is provided, which may include the steps of:
scanning one end face of the glass carrier plate 1 by using femtosecond laser, deconstructing one end face of the glass carrier plate 1, removing deconstructed materials to form a plurality of grooves 2, wherein each groove 2 is connected end to end and encloses a fan-shaped closed area 21, the closed areas 21 are arranged around the center of the glass carrier plate 1, and an annular outer edge supporting part 11 is formed at the outer edge of the glass carrier plate 1.
Bonding the other end face of the glass carrier plate 1 with one end face of the wafer 1 through a bonding agent 3, and thinning the other end face of the glass carrier plate 1; etching to remove the glass carrier plate 1 in the closed area 21, and debonding the glass carrier plate 1 in the closed area 21 and the wafer 1 through laser; cleaning the bonding agent 3 within the enclosed region 21 using an oxygen plasma; the deconstructed portion material is formed by femtosecond laser scanning and then other materials of the enclosed region 21 are removed by etching without entirely deconstructing the entire enclosed region 21, thereby improving processing efficiency and reducing production cost.
Subsequently, double-sided process of the wafer 1 can be carried out; and fixing one end face of the wafer 1 on a cutting die frame, and cutting the wafer 1.
Note that, in the present example, the closed region 21 is provided in a fan shape, and when four closed regions 21 are arranged, a cross-shaped central support portion 12 can be formed. However, in other examples of the present disclosure, the shape of the local area formed by the femtosecond laser deconstruction is not limited to a sector shape, and the central support portion 12 of the glass carrier plate 1 is not limited to a cross shape. As long as the non-thinned supporting parts are left at the outer edge and the middle part of the glass carrier plate 1 after the materials are deconstructed and removed, the purpose of the present disclosure can be achieved. Thus, for example, the shape of the enclosed area 21 in the present disclosure may also be rectangular, triangular, etc. Likewise, the shape of the central support portion 12 may also be a Chinese character 'mi', rectangle, triangle, or the like. In another example of the present disclosure, as shown in fig. 5, when the closed region 21 is rectangular, the central support portion 12 is formed at the middle of the glass carrier plate 1, and the purpose of the present disclosure can be achieved as well.
It can be understood that, with this process structure, because the central support portion 12 and the edge portion of the glass carrier plate 1 support the wafer 1, the wafer 1 is effectively prevented from being broken during processing, so that the wafer 1 can be processed under rigid contact or rotation. In the wafer processing process of this example, the edge portion and the center support portion 12 support each other, so that a difference in height between the edges of the wafer 1 can be eliminated, exposure and development pattern formation can be facilitated, and the occurrence of backsplash at the edges during resist formation or other coating processes can be avoided.
In addition, after the glass carrier plate 1 of the closed area 21 is removed by etching, a part of the bonding surface of the wafer 1 is exposed, so that two surfaces of the wafer 1 can be simultaneously processed in a bonding state at one time, and the end surface of the other end of the wafer 1 can be processed without debonding, and other processes such as wire packaging, integration of 3D elements and the like can be introduced by combining the process of the present example.
In addition, the disclosure also provides a glass carrier 1, wherein a plurality of grooves 2 are formed on one end surface of the glass carrier 1 through femtosecond laser scanning, the plurality of grooves 2 are connected end to enclose a closed area 21, and the other end surface of the glass carrier 1 is bonded with the wafer 1.
Optionally, the glass carrier 1 in the closed region 21 is etched, so that a support portion is formed on one end surface of the glass carrier 1.
Optionally, the closed area 21 is sector-shaped.
Optionally, four of the closed areas 21 are arranged, forming a cross-shaped central support 12.
The glass carrier 1 in this example and the application and structure of the glass carrier 1 in the above examples belong to the same inventive concept, and the detailed description thereof in the wafer processing field is omitted.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing illustrates and describes the general principles, principal features, and advantages of the present disclosure. It will be understood by those skilled in the art that the present disclosure is not limited to the embodiments described above, which are presented solely for purposes of illustrating the principles of the disclosure, and that various changes and modifications may be made to the disclosure without departing from the spirit and scope of the disclosure, which is intended to be covered by the claims.
Claims (8)
1. A wafer double-side processing technology is characterized by comprising the following steps:
scanning one end face of a glass carrier plate by using femtosecond laser, deconstructing one end face of the glass carrier plate to form a plurality of grooves, and connecting the heads of the grooves to enclose a closed area;
bonding the other end face of the glass carrier plate with one end face of the wafer, and thinning the other end face of the wafer;
etching to remove the glass carrier plate in the closed area, and bonding the glass carrier plate in the closed area with the wafer through laser;
cleaning the bonding agent within the enclosed area using an oxygen plasma.
2. The wafer double-sided processing technology as claimed in claim 1, wherein the wafer double-sided processing is performed after the bonding agent is cleaned;
and fixing one end face of the wafer on a cutting die frame, and cutting the wafer.
3. The double-sided processing technique for wafer as claimed in claim 1, wherein the wafer is fixed on the cutting mold frame and then oxygen plasma or laser is used.
4. The wafer double-sided processing technology as claimed in claim 1, wherein the closed area is fan-shaped, so that a cross-shaped supporting part is formed on one end surface of the glass carrier plate.
5. A glass carrier plate is characterized in that a plurality of grooves are formed in one end face of the glass carrier plate through femtosecond laser scanning, the grooves are connected end to enclose a closed area, and the other end face of the glass carrier plate is bonded with a wafer.
6. The glass carrier according to claim 5, wherein the glass carrier in the enclosed area is etched to form a support on one end surface of the glass carrier.
7. The glass carrier plate of claim 5 wherein the enclosed area is fan-shaped.
8. The glass carrier plate according to claim 5, wherein four support portions are arranged in the closed area, forming a cross shape.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011120980.0A CN112234017B (en) | 2020-10-19 | 2020-10-19 | Double-sided processing technology for glass carrier plate and wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011120980.0A CN112234017B (en) | 2020-10-19 | 2020-10-19 | Double-sided processing technology for glass carrier plate and wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112234017A true CN112234017A (en) | 2021-01-15 |
| CN112234017B CN112234017B (en) | 2023-07-14 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202011120980.0A Active CN112234017B (en) | 2020-10-19 | 2020-10-19 | Double-sided processing technology for glass carrier plate and wafer |
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| Country | Link |
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| CN (1) | CN112234017B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113035756A (en) * | 2021-03-24 | 2021-06-25 | 绍兴同芯成集成电路有限公司 | Method for radiating substrate in ultrathin wafer processing by using glass carrier plate |
| CN114121767A (en) * | 2021-11-19 | 2022-03-01 | 武汉新芯集成电路制造有限公司 | Wafer bonding structure and wafer bonding method |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003057422A (en) * | 2001-08-17 | 2003-02-26 | Japan Science & Technology Corp | Method for forming cyclic microstructure by femtosecond laser irradiation |
| US20110030763A1 (en) * | 2009-08-07 | 2011-02-10 | Jeffrey Lewis | Solar Panel Apparatus Created By Laser Etched Gratings on Glass Substrate |
| CN202977389U (en) * | 2012-11-20 | 2013-06-05 | 嘉盛半导体(苏州)有限公司 | Semiconductor wafer conveyer and pedestal thereof |
| US20150380291A1 (en) * | 2013-05-24 | 2015-12-31 | Fuji Electric Co., Ltd. | Method for manufacturing semiconductor device |
| US20160141210A1 (en) * | 2010-06-22 | 2016-05-19 | Wei-Sheng Lei | Wafer dicing using femtosecond-based laser and plasma etch |
| CN106392341A (en) * | 2016-11-07 | 2017-02-15 | 武汉华工激光工程有限责任公司 | Brittle material punching method |
| WO2018005401A1 (en) * | 2016-06-29 | 2018-01-04 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
| CN208570573U (en) * | 2018-07-11 | 2019-03-01 | 大族激光科技产业集团股份有限公司 | A kind of objective table and carrier system for wafer cutting |
| CN111033687A (en) * | 2017-08-31 | 2020-04-17 | 日本电气硝子株式会社 | Supporting glass substrate and laminated substrate using same |
| CN111446193A (en) * | 2020-03-05 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Glass carrier plate with central part removed |
| CN111446194A (en) * | 2020-03-05 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Glass carrier plate for wafer processing |
| CN111710648A (en) * | 2020-07-07 | 2020-09-25 | 绍兴同芯成集成电路有限公司 | Ultra-thin wafer back and double-side processing technology for bonded glass carrier plate |
-
2020
- 2020-10-19 CN CN202011120980.0A patent/CN112234017B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003057422A (en) * | 2001-08-17 | 2003-02-26 | Japan Science & Technology Corp | Method for forming cyclic microstructure by femtosecond laser irradiation |
| US20110030763A1 (en) * | 2009-08-07 | 2011-02-10 | Jeffrey Lewis | Solar Panel Apparatus Created By Laser Etched Gratings on Glass Substrate |
| US20160141210A1 (en) * | 2010-06-22 | 2016-05-19 | Wei-Sheng Lei | Wafer dicing using femtosecond-based laser and plasma etch |
| CN202977389U (en) * | 2012-11-20 | 2013-06-05 | 嘉盛半导体(苏州)有限公司 | Semiconductor wafer conveyer and pedestal thereof |
| US20150380291A1 (en) * | 2013-05-24 | 2015-12-31 | Fuji Electric Co., Ltd. | Method for manufacturing semiconductor device |
| WO2018005401A1 (en) * | 2016-06-29 | 2018-01-04 | Corning Incorporated | Inorganic wafer having through-holes attached to semiconductor wafer |
| CN106392341A (en) * | 2016-11-07 | 2017-02-15 | 武汉华工激光工程有限责任公司 | Brittle material punching method |
| CN111033687A (en) * | 2017-08-31 | 2020-04-17 | 日本电气硝子株式会社 | Supporting glass substrate and laminated substrate using same |
| CN208570573U (en) * | 2018-07-11 | 2019-03-01 | 大族激光科技产业集团股份有限公司 | A kind of objective table and carrier system for wafer cutting |
| CN111446193A (en) * | 2020-03-05 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Glass carrier plate with central part removed |
| CN111446194A (en) * | 2020-03-05 | 2020-07-24 | 绍兴同芯成集成电路有限公司 | Glass carrier plate for wafer processing |
| CN111710648A (en) * | 2020-07-07 | 2020-09-25 | 绍兴同芯成集成电路有限公司 | Ultra-thin wafer back and double-side processing technology for bonded glass carrier plate |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113035756A (en) * | 2021-03-24 | 2021-06-25 | 绍兴同芯成集成电路有限公司 | Method for radiating substrate in ultrathin wafer processing by using glass carrier plate |
| CN114121767A (en) * | 2021-11-19 | 2022-03-01 | 武汉新芯集成电路制造有限公司 | Wafer bonding structure and wafer bonding method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112234017B (en) | 2023-07-14 |
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