CN112233988B - Packaging substrate technology - Google Patents
Packaging substrate technology Download PDFInfo
- Publication number
- CN112233988B CN112233988B CN201911136790.5A CN201911136790A CN112233988B CN 112233988 B CN112233988 B CN 112233988B CN 201911136790 A CN201911136790 A CN 201911136790A CN 112233988 B CN112233988 B CN 112233988B
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- Prior art keywords
- chip
- bonding pad
- copper
- material layer
- insulating material
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
Abstract
The invention provides a packaging substrate process, and relates to the technical field of chip packaging. The high heat dissipation packaging substrate process comprises the following steps: s1, arranging three different chips IC1, IC2 and IC3 according to the size and packaging requirements, designing a copper bracket according to the size of the chip, arranging the bonding pad surfaces of the chips in opposite directions, arranging the non-bonding pad surfaces in opposite directions, and arranging the bonding pad surfaces on the copper bracket and combining the bonding pad surfaces with the copper bracket; s2, processing the chip set position and the two-sided via holes on the structural plate to form step grooves; s3, placing the copper bracket where the chip is located and the copper block for conduction in a step groove machined by the structural plate; and S4, respectively pressing the flexible insulating material layer 1 and the flexible insulating material layer 2 on the two sides of the structural plate. The scheme of the invention adopts the whole board production and processing, the circuit pattern transfer is completed through exposure, the circuit forming is completed through etching, the wire bonding is not needed to be connected with bonding pads one by one, the time and the production cost are saved, and the production efficiency is improved.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a packaging substrate process.
Background
The chip is used as a core device for controlling a circuit, converting signals and transmitting the signals, is widely applied to the electronic information industry, the electric energy consumed by the chip during the working period is mostly converted into heat for emission, the heat generated by the chip is rapidly increased, if the heat is not timely emitted, the chip can be continuously heated, the reliability is reduced, and finally the chip is invalid due to overheating, so that the heat dissipation capacity of the chip can be improved as much as possible in the chip packaging process, the chip performance is exponentially improved along with the rapid development of the electronic information technology, the heat productivity caused by the increase of power consumption is increased, and the heat dissipation capacity of the chip is required to be increased more and more.
The method is widely applied to the field of chip packaging at present and adopts Wire Bonding technology, metal wires (gold wires, aluminum wires and the like) are used for completing connection of internal interconnection wiring of a solid circuit in a microelectronic device, namely connection between the chip and the circuit or a lead frame by using hot-pressing or ultrasonic energy, and according to the processing principle of the prior art, the chip is only contacted with the chip by Wire Bonding metal except copper at the position of a packaging Bonding pad, the effective heat dissipation area is small, and the current carrying capacity is insufficient, so that the packaging mode is difficult to adapt to the heat dissipation requirement of a high-performance chip; in addition, the Wire Bonding technology adopts a Bonding pad-by-Bonding pad Wire Bonding mode, and the production efficiency is low.
Disclosure of Invention
(one) solving the technical problems
Aiming at the defects of the prior art, the invention provides a packaging substrate process, which solves the defects and the shortcomings in the prior art.
(II) technical scheme
In order to achieve the above purpose, the invention is realized by the following technical scheme: a package substrate process comprising the steps of:
s1, arranging three different chips IC1, IC2 and IC3 according to the size and packaging requirements, designing a copper bracket according to the size of the chip, arranging the bonding pad surfaces of the chips in opposite directions, arranging the non-bonding pad surfaces in opposite directions, and arranging the bonding pad surfaces on the copper bracket and combining the bonding pad surfaces with the copper bracket;
s2, processing the chip set position and the two-sided via holes on the structural plate to form step grooves;
s3, placing the copper bracket where the chip is located and the copper block for conduction in a step groove machined by the structural plate;
s4, respectively pressing the flexible insulating material layer 1 and the flexible insulating material layer 2 on the two sides of the structural plate;
s5, processing laser blind holes to realize the conduction of circuits on the two sides of the chip bonding pad and the packaging bonding pad, depositing the whole board to form bottom copper, pressing the exposed dry films on the upper side and the lower side, sequentially carrying out double-side exposure, development and copper plating to form the circuits on the two sides, and finally carrying out dry film stripping treatment and bottom copper etching to form the circuits on the two sides;
s6, laminating the flexible insulating material layer 3 and the flexible insulating material layer 4 on two sides, wherein the flexible insulating material layer 3 is a chip insulating protective layer, laser windowing and secondary copper plating treatment are carried out on the flexible insulating material layer 4 according to the specification requirements of a bonding pad packaged by a chip to form a packaging bonding pad, and the appearance of a chip monomer can be cut according to the specification and the size after surface treatment.
(III) beneficial effects
The invention provides a packaging substrate process. The beneficial effects are as follows:
1. the scheme of the invention adopts the whole board production and processing, the circuit pattern transfer is completed through exposure, the circuit forming is completed through etching, wire Bonding is not needed to be connected with Bonding pads one by one in a Wire Bonding mode, the time and the production cost are saved, and the production efficiency is improved.
2. The multiple chips realize two-sided wiring design, and are easy to realize integrated package of more chips and smaller package size.
3. The wiring design can increase the copper area as much as possible, improve the heat dissipation performance while improving the current carrying performance of the chip, and realize the packaging of the chip with higher performance.
4. The hole diameter of the blind hole can be reduced by adopting a copper block conducting method at the position of the through hole, and the hole filling copper plating capability of the product circuit during manufacturing is improved.
Drawings
FIGS. 1-6 are schematic flow diagrams of a first embodiment of the present invention;
fig. 7-12 are schematic flow diagrams in the second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one:
as shown in fig. 1-6, an embodiment of the present invention provides a package substrate process, including the following steps:
s1, arranging three different chips IC1, IC2 and IC3 according to the size and packaging requirements, designing a copper bracket according to the size of the chip, arranging the bonding pad surfaces of the chips in opposite directions, arranging the non-bonding pad surfaces in opposite directions, and arranging the bonding pad surfaces on the copper bracket and combining the bonding pad surfaces with the copper bracket, wherein the side view is shown in figure 1;
s2, processing the chip set position and the two-sided via holes on the structural plate to form step grooves, wherein the single-body section structure of the step grooves is shown in figure 2;
s3, placing the copper bracket where the chip is and the copper block for conduction in a step groove machined by the structural plate, wherein the single-body cross-section structure of the copper bracket is shown in figure 3;
s4, respectively pressing the flexible insulating material layer 1 and the flexible insulating material layer 2 on two sides of the structural plate, wherein the single cross-section structure of the flexible insulating material layer is shown in FIG. 4;
s5, processing laser blind holes to realize the conduction of circuits on two sides of a chip bonding pad and a packaging bonding pad, depositing a whole plate to form bottom copper, laminating an exposure Dry Film (DF) on the upper side and the lower side, sequentially performing double-side exposure, development and copper plating to form two-side circuits, and finally performing dry film stripping treatment and bottom copper etching to form the two-side circuits, wherein the single-body section structure is shown in figure 5;
s6, laminating the flexible insulating material layer 3 and the flexible insulating material layer 4 on two sides, wherein the flexible insulating material layer 3 is a chip insulating protective layer, the flexible insulating material layer 4 is subjected to laser windowing and secondary copper plating treatment according to the specification requirements of a bonding pad of chip packaging to form a packaging bonding pad, and the appearance of a chip monomer can be cut according to the specification and the size after surface treatment, and the cross-section structure of the chip monomer is shown in figure 6.
Embodiment two:
as shown in fig. 7-12, an embodiment of the present invention provides a package substrate process, which includes the following steps:
s1, pressing a photosensitive Dry Film (DF) on two sides of a copper sheet, exposing and developing, wherein the single-body cross-section structure is shown in figure 7;
s2, etching and stripping the copper sheet to form a metal frame structure, wherein the single-body section structure of the metal frame structure is shown in FIG 8;
s3, setting the chips IC1 and IC2, and laminating the flexible isolation material layer 1 on one surface of the whole plate, wherein the single-body section structure of the flexible isolation material layer is shown in FIG. 9;
s4, after the whole plate is turned over, the chip IC3 is set, the copper block for connecting the via hole is disconnected with the metal frame by utilizing a laser cutting process, so that the electrical connection function is ensured to be correct, and the single-body section structure is shown in FIG. 10;
s5, laminating the flexible isolation material layer 2 on one surface of the whole plate, wherein the single-body cross-section structure is shown in FIG. 11, and the cross-section structure formed at the moment is similar to that of FIG. 4 in the first embodiment;
s6, processing laser blind holes to realize the conduction of circuits on two sides of a chip bonding pad and a packaging bonding pad, depositing a whole board to form bottom copper, laminating an exposure Dry Film (DF) on the upper side and the lower side, sequentially performing double-side exposure, development and copper plating to form two-side circuits, and finally performing dry film stripping treatment and bottom copper etching to form two-side circuits;
s7, laminating the flexible insulating material layer 3 and the flexible insulating material layer 4 on two sides, wherein the flexible insulating material layer 3 is a chip insulating protective layer, the flexible insulating material layer 4 is subjected to laser windowing and secondary copper plating treatment according to the specification requirements of a bonding pad packaged by a chip to form a packaging bonding pad, and the surface treatment is performed to cut the appearance of a chip monomer according to the specification and the size, so that the multi-chip integrated packaging structure can be formed, and the sectional view is shown in FIG. 12.
As can be seen from the first embodiment and the second embodiment, the scheme of the invention adopts the whole board production and processing, the circuit pattern transfer is completed through exposure, the circuit forming is completed through etching, wire Bonding is not needed to be connected with each Bonding pad by Bonding pad, the time and the production cost are saved, and the production efficiency is improved; the multiple chips realize two-sided wiring design, so that integrated package of more chips and smaller package size are easy to realize; the wiring design can increase the copper area as much as possible, improve the heat dissipation performance while improving the current carrying performance of the chip, and realize the packaging of the chip with higher performance; the hole diameter of the blind hole can be reduced by adopting a copper block conducting method at the position of the through hole, and the hole filling copper plating capability of the product circuit during manufacturing is improved.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (1)
1. A process for packaging a substrate, comprising: the method comprises the following steps:
s1, arranging three different first ICs, second ICs and third ICs according to the size and packaging requirements, designing a copper bracket according to the size of the chip, arranging the bonding pad surfaces of the chip in opposite directions, arranging the non-bonding pad surfaces in opposite directions, and arranging the bonding pad surfaces on the upper side and the lower side of the copper bracket and combining the bonding pad surfaces with the copper bracket;
s2, processing a chip set position and two-sided via holes on the structural plate to form a through step groove;
s3, placing the copper bracket where the chip is located and the copper block for conduction in a step groove machined by the structural plate;
s4, respectively pressing the first flexible insulating material layer and the second flexible insulating material layer on two sides of the structural plate;
s5, processing laser blind holes to realize the conduction of circuits on the two sides of the chip bonding pad and the packaging bonding pad, depositing the whole board to form bottom copper, pressing the exposed dry films on the upper side and the lower side, sequentially carrying out double-side exposure, development and copper plating to form the circuits on the two sides, and finally carrying out dry film stripping treatment and bottom copper etching to form the circuits on the two sides;
s6, laminating a third flexible insulating material layer and a fourth flexible insulating material layer on the two sides, wherein the third flexible insulating material layer is a chip insulating protective layer, laser windowing and secondary copper plating treatment are carried out on the fourth flexible insulating material layer according to the specification requirements of a bonding pad packaged by a chip to form a packaging bonding pad, and the appearance of a chip monomer can be cut according to the specification and the size after surface treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911136790.5A CN112233988B (en) | 2019-11-19 | 2019-11-19 | Packaging substrate technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911136790.5A CN112233988B (en) | 2019-11-19 | 2019-11-19 | Packaging substrate technology |
Publications (2)
| Publication Number | Publication Date |
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| CN112233988A CN112233988A (en) | 2021-01-15 |
| CN112233988B true CN112233988B (en) | 2023-10-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201911136790.5A Active CN112233988B (en) | 2019-11-19 | 2019-11-19 | Packaging substrate technology |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646828A (en) * | 1995-02-24 | 1997-07-08 | Lucent Technologies Inc. | Thin packaging of multi-chip modules with enhanced thermal/power management |
| JP2007318047A (en) * | 2006-05-29 | 2007-12-06 | Ibiden Co Ltd | Multilayer wiring board and manufacturing method therefor |
| CN102065638A (en) * | 2009-11-17 | 2011-05-18 | 三星电机株式会社 | Printed circuit board having electro-component and manufacturing method thereof |
| CN204217201U (en) * | 2014-10-13 | 2015-03-18 | 东莞森玛仕格里菲电路有限公司 | Bury copper billet heat radiation PCB structure |
| CN107611114A (en) * | 2017-07-31 | 2018-01-19 | 华为技术有限公司 | A kind of embedded substrate |
| CN109003963A (en) * | 2017-06-07 | 2018-12-14 | 三星电子株式会社 | Semiconductor packages and the method for manufacturing it |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9024429B2 (en) * | 2013-08-29 | 2015-05-05 | Freescale Semiconductor Inc. | Microelectronic packages containing opposing devices and methods for the fabrication thereof |
-
2019
- 2019-11-19 CN CN201911136790.5A patent/CN112233988B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646828A (en) * | 1995-02-24 | 1997-07-08 | Lucent Technologies Inc. | Thin packaging of multi-chip modules with enhanced thermal/power management |
| JP2007318047A (en) * | 2006-05-29 | 2007-12-06 | Ibiden Co Ltd | Multilayer wiring board and manufacturing method therefor |
| CN102065638A (en) * | 2009-11-17 | 2011-05-18 | 三星电机株式会社 | Printed circuit board having electro-component and manufacturing method thereof |
| CN204217201U (en) * | 2014-10-13 | 2015-03-18 | 东莞森玛仕格里菲电路有限公司 | Bury copper billet heat radiation PCB structure |
| CN109003963A (en) * | 2017-06-07 | 2018-12-14 | 三星电子株式会社 | Semiconductor packages and the method for manufacturing it |
| CN107611114A (en) * | 2017-07-31 | 2018-01-19 | 华为技术有限公司 | A kind of embedded substrate |
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| Publication number | Publication date |
|---|---|
| CN112233988A (en) | 2021-01-15 |
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