TWI785651B - Package structure and its manufacturing method, circuit board and its manufacturing method - Google Patents
Package structure and its manufacturing method, circuit board and its manufacturing method Download PDFInfo
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本申請涉及一種封裝結構及其製造方法、電路板及其製造方法。 The present application relates to a packaging structure and a manufacturing method thereof, a circuit board and a manufacturing method thereof.
金屬-氧化物半導體場效應電晶體(MOSFET)作為常見的功率半導體,因為具有導通電阻小,損耗低,驅動電路簡單,熱阻特性佳等優點,所以廣泛應用於電路板中以實現電能轉換與電路控制。習知技術中,功率半導體埋入電路板後通常藉由微型導通孔實現與電路板內的線路層的導通,但是微型導通孔不僅加工困難,而且可靠性不佳。 As a common power semiconductor, Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) is widely used in circuit boards to realize power conversion and circuit control. In the conventional technology, after the power semiconductor is embedded in the circuit board, the conduction with the circuit layer in the circuit board is usually achieved through micro-vias, but the micro-vias are not only difficult to process, but also have poor reliability.
為解決習知技術中涉及的問題,本申請提供一種具有半導體的封裝結構。 In order to solve the problems involved in the prior art, the present application provides a package structure with a semiconductor.
另外,還有必要提供一種具有上述封裝結構的製造方法。 In addition, it is also necessary to provide a manufacturing method with the above packaging structure.
另外,還有必要提供一種具有上述封裝結構的電路板。 In addition, it is also necessary to provide a circuit board with the above packaging structure.
另外,還有必要提供一種上述電路板的製造方法。 In addition, it is also necessary to provide a method for manufacturing the above-mentioned circuit board.
一種封裝結構的製造方法包括步驟:提供一晶圓,所述晶圓包括多個半導體。於所述晶圓上設置連接板,所述連接板包括多個連接件,每一連接件電性連接至少一所述半導體,獲得一第一中間體。於所述第一中間體的外側設置封裝體,所述封裝體包覆所述晶圓及所述連接板。移除所述連接件對應的部分所述封裝體,獲得第二中間體,以及分割所述第二中間體,獲得多個所述封裝結構,其中,每一所述封裝結構包括至少一所述半導體及與電性連接所述半導體的至少一連接件。 A manufacturing method of a packaging structure includes the steps of: providing a wafer, and the wafer includes a plurality of semiconductors. A connecting board is arranged on the wafer, and the connecting board includes a plurality of connecting pieces, and each connecting piece is electrically connected to at least one of the semiconductors to obtain a first intermediate body. A packaging body is provided outside the first intermediate body, and the packaging body covers the wafer and the connecting board. removing a portion of the package body corresponding to the connector to obtain a second intermediate body, and dividing the second intermediate body to obtain a plurality of the package structures, wherein each package structure includes at least one of the A semiconductor and at least one connector electrically connected to the semiconductor.
一種封裝結構,包括至少一半導體、至少一連接件及封裝體,所述連接件設置於所述半導體上,所述連接件電性連接所述半導體,所述封裝體包覆所述半導體,部分所述連接件露出於所述封裝體。 A packaging structure, comprising at least one semiconductor, at least one connector and a package body, the connector is disposed on the semiconductor, the connector is electrically connected to the semiconductor, the package covers the semiconductor, partly The connector is exposed from the package.
進一步地,所述半導體為功率半導體,所述連接件包括導線架、金屬夾或者金屬片。 Further, the semiconductor is a power semiconductor, and the connector includes a lead frame, a metal clip or a metal sheet.
進一步地,所述半導體包括半導體本體、源極、柵極及漏極,所述源極及所述柵極設置於所述半導體本體的一側,所述漏極設置於所述半導體本體的另一側,所述柵極與所述漏極或所述源極絕緣,所述漏極與所述源極之間設置有PN結。 Further, the semiconductor includes a semiconductor body, a source, a gate and a drain, the source and the gate are arranged on one side of the semiconductor body, and the drain is arranged on the other side of the semiconductor body On one side, the gate is insulated from the drain or the source, and a PN junction is provided between the drain and the source.
進一步地,所述連接件包括連接件本體、內側連接墊及外側連接墊,所述連接件本體設置於所述內側連接墊與所述外側連接墊之間,所述內側連接墊電性連接所述源極、所述柵極或所述漏極,所述外側連接墊露出於所述封裝體。 Further, the connector includes a connector body, an inner connection pad and an outer connection pad, the connector body is arranged between the inner connection pad and the outer connection pad, and the inner connection pad is electrically connected to the The source, the gate or the drain, and the outer connection pads are exposed in the package.
進一步地,所述封裝結構還包括導電體,所述導電體設置於所述內側連接墊及所述源極、所述柵極或所述漏極之間。 Further, the package structure further includes a conductor, and the conductor is disposed between the inner connection pad and the source, the gate or the drain.
一種電路板的製造方法,包括步驟:提供第一電路基板,所述第一電路基板包括介質層及設置於所述介質層上的銅箔層,所述第一電路基板設置有開孔。 A method for manufacturing a circuit board, comprising the steps of: providing a first circuit substrate, the first circuit substrate includes a dielectric layer and a copper foil layer disposed on the dielectric layer, and the first circuit substrate is provided with openings.
提供上所述的封裝結構,將所述封裝結構設置於所述開孔內。於所述銅箔層上電鍍形成電鍍層,所述電鍍層覆蓋所述連接件,以及蝕刻所述電鍍層及所述銅箔層以形成線路層,所述線路層電性連接所述連接件。提供一第二電路基板及粘接層,設置所述粘接層於所述線路層及所述第二電路基板之間,壓合所述電路板、所述第二電路基板及所述粘接層,獲得所述電路板。 The above packaging structure is provided, and the packaging structure is disposed in the opening. Electroplating on the copper foil layer to form an electroplating layer, the electroplating layer covering the connector, and etching the electroplating layer and the copper foil layer to form a circuit layer, the circuit layer is electrically connected to the connector . Provide a second circuit substrate and an adhesive layer, arrange the adhesive layer between the circuit layer and the second circuit substrate, press the circuit board, the second circuit substrate and the adhesive layer, to obtain the circuit board.
進一步地,還包括步驟:於所述電路板設置通孔,所述通孔貫穿所述第一電路基板、所述粘接層及所述第二電路基板,以及於所述通孔內設置導通體,所述導通體電性連接所述線路層及所述第二電路基板。 Further, it also includes the step of: providing a through hole on the circuit board, the through hole passing through the first circuit substrate, the adhesive layer and the second circuit substrate, and providing a conductive connection in the through hole. body, and the conducting body is electrically connected to the circuit layer and the second circuit substrate.
一種電路板,包括第一電路基板、第二電路基板、粘接層及如上所述的封裝結構,所述第一電路基板包括介質層及設置於所述介質層上的線路層,所述第一電路基板設置有開孔,所述封裝結構設置於所述開孔,所述封裝結構設置於所述開孔內,所述連接件電性連接所述線路層,所述粘接層設置於所述第二電路基板及所述線路層之間。 A circuit board, comprising a first circuit substrate, a second circuit substrate, an adhesive layer and the packaging structure as described above, the first circuit substrate comprises a dielectric layer and a circuit layer arranged on the dielectric layer, the second A circuit substrate is provided with an opening, the packaging structure is provided in the opening, the packaging structure is provided in the opening, the connector is electrically connected to the circuit layer, and the adhesive layer is provided in the Between the second circuit substrate and the circuit layer.
進一步地,所述第一電路基板的厚度與所述封裝結構的厚度相同。 Further, the thickness of the first circuit substrate is the same as that of the packaging structure.
本申請提供的封裝結構藉由封裝體將半導體及連接件連接在一起,連接件電性連接半導體,部分露出於封裝體的連接件可以用於連接電路板中的線路層,從而無需設置微型導通孔,有利於提高半導體與線路層之間電性連接的可靠性。 The packaging structure provided by this application connects the semiconductor and the connectors together through the package body, the connectors are electrically connected to the semiconductor, and the connectors partially exposed from the package body can be used to connect the circuit layer in the circuit board, so that there is no need to set up micro-connections The hole is beneficial to improve the reliability of the electrical connection between the semiconductor and the circuit layer.
100:封裝結構 100: Package structure
10:半導體 10: Semiconductor
11:半導體本體 11: Semiconductor body
12:源極 12: source
13:柵極 13:Gate
14:漏極 14: Drain
21:第一連接件 21: The first connector
211:第一連接本體 211: The first connection body
212:第一內側連接墊 212: First inner connection pad
213:第一外側連接墊 213: first outer connection pad
22:第二連接件 22: Second connector
221:第二連接本體 221: The second connection body
222:第二內側連接墊 222: second inner connection pad
223:第二外側連接墊 223: second outer connection pad
231:第一導電體 231: The first conductor
232:第二導電體 232: Second conductor
30:封裝體 30: Encapsulation
41:第一銅箔層 41: The first copper foil layer
42:第二銅箔層 42: Second copper foil layer
43:第一介質層 43: The first medium layer
44:開孔 44: opening
51:第一電鍍層 51: The first electroplating layer
52:第二電鍍層 52: Second electroplating layer
61:第一線路層 61: The first line layer
62:第二線路層 62: Second line layer
200:電路板 200: circuit board
203:導通體 203: Conductor
300:第一電路基板 300: the first circuit substrate
301:第三中間體 301: The third intermediate
302:通孔 302: through hole
400:第二電路基板 400: the second circuit substrate
401:第二介質層 401: Second dielectric layer
402:第三線路層 402: Third line layer
D1、D2:厚度 D1, D2: Thickness
圖1為本申請一實施例提供的半導體的示意圖。 FIG. 1 is a schematic diagram of a semiconductor provided by an embodiment of the present application.
圖2為圖1所示的半導體設置第一連接件、第二連接件後的示意圖。 FIG. 2 is a schematic diagram of the semiconductor shown in FIG. 1 after the first connecting member and the second connecting member are provided.
圖3為本申請一實施例體用的封裝結構的示意圖。 FIG. 3 is a schematic diagram of a packaging structure used in an embodiment of the present application.
圖4為本申請一實施例提供的第一電路基板的示意圖。 FIG. 4 is a schematic diagram of a first circuit substrate provided by an embodiment of the present application.
圖5為圖4所述的第一電路基板設置封裝結構後的示意圖。 FIG. 5 is a schematic diagram of the first circuit substrate shown in FIG. 4 after being provided with a packaging structure.
圖6為圖5所示的第一電路基板電鍍形成第一電鍍層及第二電鍍層後的示意圖。 FIG. 6 is a schematic diagram of the first electroplating layer and the second electroplating layer formed by electroplating the first circuit substrate shown in FIG. 5 .
圖7為圖6所示的第一電路基板、粘接層、第二電路基板壓合前的示意圖。 FIG. 7 is a schematic diagram of the first circuit substrate, the adhesive layer, and the second circuit substrate shown in FIG. 6 before lamination.
圖8為圖6所示的第一電路基板、粘接層、第二電路基板壓合後的示意圖。 FIG. 8 is a schematic diagram of the first circuit substrate, the adhesive layer, and the second circuit substrate shown in FIG. 6 after lamination.
圖9為本申請一實施例提供的電路板的示意圖。 FIG. 9 is a schematic diagram of a circuit board provided by an embodiment of the present application.
下面將結合本申請實施例中的附圖,對本申請實施例中的技術方案進行清楚、完整地描述,顯然,所描述的實施例僅僅是本申請一部分實施例,而不是全部的實施例。 The following will clearly and completely describe the technical solutions in the embodiments of the application with reference to the drawings in the embodiments of the application. Apparently, the described embodiments are only some of the embodiments of the application, not all of them.
需要說明的是,當元件被稱為“固定於”另一個元件,它可以直接在另一個元件上或者也可以存在居中的元件。當一個元件被認為是“連接”另一個元件,它可以是直接連接到另一個元件或者可能同時存在居中元件。當一個元件被認為是“設置於”另一個元件,它可以是直接設置在另一個元件上或者可能同時存在居中元件。 It should be noted that when an element is referred to as being “fixed” to another element, it can be directly on the other element or there can also be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present.
請參見圖1至圖9,本申請一實施例提供一種電路板200的製造方法,包括步驟:
Referring to FIG. 1 to FIG. 9, an embodiment of the present application provides a method for manufacturing a
S1:請參見圖3,提供一封裝結構100,所述封裝結構100包括至少一半導體10、至少一第一連接件21、至少一第二連接件22及一封裝體30。所述第一連接件21與所述第二連接件22設置於所述半導體10的相對兩側。所述第一連接件21及所述第二連接件22電性連接所述半導體10。所述封裝體30包覆所述半導體10,部分所述第一連接件21及所述第二連接件22於所述封裝體30中露出。
S1: Referring to FIG. 3 , a
在本實施例中,所述第一連接件21包括第一連接本體211、第一內側連接墊212及第一外側連接墊213,所述第一內側連接墊212及所述第一外側連接墊213分別設置於所述第一連接本體211的相對兩側。所述第二連接件22包括第二連接本體221、第二內側連接墊222及第二外側連接墊223,所述第二內側連接墊222及所述第二外側連接墊223分別設置於所述第二連接本體221的相對兩側。所述半導體10包括半導體本體11、源極12、柵極13及漏極14,所述源極12及所述柵極13設置於所述半導體本體11的一側,所述漏極14設置於所述半導體本體11的另一側。所述柵極13與所述漏極14或所述源極12絕緣,所述漏極14與所述源極12之間有兩個PN結。所述第一內側連接墊212電性連
接所述源極12及所述柵極13,所述第二內側連接墊222電性連接所述漏極14。所述第一外側連接墊213及所述第二外側連接墊223露出於所述封裝體30。
In this embodiment, the
在本實施例中,請參見圖1至圖3,步驟S1中,所述封裝結構100的製造方法包括:
In this embodiment, please refer to FIG. 1 to FIG. 3 , in step S1, the manufacturing method of the
S10:提供一晶圓(圖未示),所述晶圓包括呈矩陣排列的多個所述半導體10(參見圖1),所述半導體10為功率半導體。
S10: Provide a wafer (not shown in the figure), the wafer includes a plurality of semiconductors 10 (see FIG. 1 ) arranged in a matrix, and the
S11:於所述晶圓的一側設置第一連接板(圖未示)以及於所述晶圓的另一側設置第二連接板(圖未示),所述第一連接板包括多個所述第一連接件21,所述第二連接板包括多個所述第二連接件22,請參見圖2,每一所述半導體10對應一個所述第一連接件21及一個所述第二連接件22,獲得一個第一中間體(圖未示)。其中,所述第一內側連接墊212電性連接所述源極12及所述柵極13,所述第二內側連接墊222電性連接所述漏極14。所述第一連接件21或所述第二連接件22包括導線架、金屬夾或者金屬片等。
S11: setting a first connecting plate (not shown) on one side of the wafer and setting a second connecting plate (not shown) on the other side of the wafer, the first connecting plate includes a plurality of The
在本實施例中,請參見圖2,步驟S11包括:於所述第一內側連接墊212與所述源極12或所述柵極13之間設置一第一導電體231,以及於所述第二內側連接墊222與所述漏極14之間設置一第二導電體232,所述第一導電體231用於連接並電性導通所述第一內側連接墊212與所述源極12或所述柵極13,所述第二導電體232用於連接並電性導通所述第二內側連接墊222及所述漏極14。所述第一導電體231及所述第二導電體232的材質包括導電膠、焊料等。
In this embodiment, please refer to FIG. 2 , step S11 includes: disposing a
S12:於所述第一中間體的外側設置所述封裝體30,所述封裝體30包覆所述晶圓及所述連接板。
S12: Disposing the
S13:請參見圖3,移除與所述第一外側連接墊213及所述第二外側連接墊223對應的部分所述封裝體30,使得所述第一外側連接墊213及所述第二外側連接墊223暴露於所述封裝體30外,獲得一第二中間體(圖未示)。
S13: Referring to FIG. 3 , remove the part of the
S14:分割所述第二中間體,獲得多個所述封裝結構100。
S14: Divide the second intermediate body to obtain a plurality of
S2:請參見圖4,提供一第一電路基板300,所述第一電路基板300包括第一銅箔層41、第二銅箔層42及設置於所述第一銅箔層41及所述第二銅
箔層42之間的第一介質層43,所述第一電路基板300具有開孔44,所述開孔44依次貫穿所述第一銅箔層41、所述第一介質層43及所述第二銅箔層42。
S2: Please refer to FIG. 4 , providing a
S3:請參見圖5,將所述封裝結構100設置於所述開孔44內,所述第一電路基板300的厚度D1大致與所述封裝結構100的厚度D2(參見圖3)相同,使所述第一外側連接墊213的外側面大致與所述第一銅箔層41的外側面平齊,以及所述第二外側連接墊223的外側面大致與所述第二銅箔層42的外側面平齊。
S3: Please refer to FIG. 5, dispose the
S4:請參見圖6,於所述第一銅箔層41上電鍍形成第一電鍍層51,所述第一電鍍層51覆蓋所述第一外側連接墊213;以及於所述第二銅箔層42上電鍍形成第二電鍍層52,所述第二電鍍層52覆蓋所述第二外側連接墊223。
S4: Please refer to FIG. 6, forming a
S5:請參見圖7,蝕刻所述第一銅箔層41及所述第一電鍍層51以形成第一線路層61,蝕刻所述第二銅箔層42及所述第二電鍍層52以形成第二線路層62,獲得一第三中間體301。其中,所述第一線路層61電性連接所述第一外側連接墊213,所述第二線路層62電性連接所述第二外側連接墊223。
S5: Please refer to FIG. 7, etch the first
S6:提供一第二電路基板400及一粘接層70,設置粘接層70於所述第三中間體301及所述第二電路基板400之間,以及壓合所述第三中間體301、所述粘接層70及所述第二電路基板400,獲得所述電路板200。
S6: providing a
在本實施例中,所述第二電路基板400包括多個第二介質層401及多個第三線路層402,所述第三線路層402與所述第二介質層401交錯疊設,所述粘接層70設置於在最外側的所述第三線路層402及所述第一線路層61之間。步驟S6之後還包括:於所述電路板200設置通孔302,所述通孔302貫穿所述第二電路基板400、所述粘接層70及所述第三中間體301,以及於所述通孔302內設置導通體203,所述導通體203電性連接所述第一線路層61、所述第二線路層62及多個所述第三線路層402。
In this embodiment, the
相比於習知技術,本申請提供的電路板200的製造方法具有以下優點:
Compared with the prior art, the manufacturing method of the
(一)藉由先製備封裝結構100,該封裝結構100包括半導體10、連接件(第一連接件21、第二連接件22)及包覆半導體10及連接件的封裝體
30,然後再將封裝結構100埋入電路板200中,該封裝結構100藉由第一外側連接墊213或第二外側連接墊223電性連接線路層(第一線路層61、第二線路層62),從而無需設置微型導通孔,可以提高了半導體10連接線路層的可靠性,而且該方法步驟簡單。
(1) By first preparing the
(二)封裝結構100藉由第一外側連接墊213或第二外側連接墊223電性連接線路層,第一外側連接墊213與第二外側連接墊223的面積相較於微型導通孔有明顯提高,從而可以提高該半導體10將熱量藉由第一外側連接墊213或第二外側連接墊223傳導至電路板乃至外界的效率。
(2) The
(三)藉由先製備封裝結構100,然後測試該封裝結構100,可以有效提高最終電路板200的良品率。
(3) By preparing the
(四)藉由先製備封裝結構100,然後將該封裝結構100埋入電路板200中,最後藉由壓合的方式對該電路板200進行增層,可以減少該半導體10在壓合過程中損壞的風險。
(4) By first preparing the
請參見圖9,本申請還提供一種電路板200,所述電路板200包括第一電路基板300、第二電路基板400、粘接層70及所述的封裝結構100,所述第一電路基板300包括第一介質層43及設置於所述第一介質層43上的第一線路層61,所述第一電路基板300設置有開孔44,所述封裝結構100設置於所述開孔44內,所述第一連接件21電性連接所述第一線路層61,所述粘接層70設置於所述第二電路基板400及所述第一線路層60之間。
Please refer to FIG. 9, the present application also provides a
以上說明僅僅是對本申請一種優化的具體實施方式,但在實際的應用過程中不能僅僅局限於這種實施方式。對本領域的普通技術人員來說,根據本申請的技術構思做出的其他變形和改變,都應該屬於本申請的保護範圍。 The above description is only an optimized specific implementation manner of the present application, but it should not be limited to this implementation manner only in the actual application process. For those of ordinary skill in the art, other deformations and changes made according to the technical concept of the present application should fall within the scope of protection of the present application.
100:封裝結構 100: Package structure
12:源極 12: source
11:半導體本體 11: Semiconductor body
14:漏極 14: Drain
223:第二外側連接墊 223: second outer connection pad
221:第二連接本體 221: The second connection body
222:第二內側連接墊 222: Second inner connection pad
22:第二連接件 22: Second connector
30:封裝體 30: Encapsulation
13:柵極 13:Gate
213:第一外側連接墊 213: first outer connection pad
211:第一連接本體 211: The first connection body
212:第一內側連接墊 212: First inner connection pad
21:第一連接件 21: The first connector
231:第一導電體 231: The first conductor
232:第二導電體 232: Second conductor
D2:厚度 D2: Thickness
Claims (6)
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US20150028448A1 (en) * | 2013-07-26 | 2015-01-29 | Infineon Technologies Ag | Chip Package with Embedded Passive Component |
US20160005684A1 (en) * | 2014-07-07 | 2016-01-07 | Infineon Technologies Austria Ag | Electronic component and method for electrically coupling a semiconductor die to a contact pad |
US20200176412A1 (en) * | 2018-11-29 | 2020-06-04 | Infineon Technologies Ag | Package comprising chip contact element of two different electrically conductive materials |
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US20150028448A1 (en) * | 2013-07-26 | 2015-01-29 | Infineon Technologies Ag | Chip Package with Embedded Passive Component |
US20160005684A1 (en) * | 2014-07-07 | 2016-01-07 | Infineon Technologies Austria Ag | Electronic component and method for electrically coupling a semiconductor die to a contact pad |
US20200176412A1 (en) * | 2018-11-29 | 2020-06-04 | Infineon Technologies Ag | Package comprising chip contact element of two different electrically conductive materials |
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