CN115483116A - Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof - Google Patents

Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof Download PDF

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Publication number
CN115483116A
CN115483116A CN202110666659.0A CN202110666659A CN115483116A CN 115483116 A CN115483116 A CN 115483116A CN 202110666659 A CN202110666659 A CN 202110666659A CN 115483116 A CN115483116 A CN 115483116A
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CN
China
Prior art keywords
layer
semiconductor
circuit
circuit substrate
package structure
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Pending
Application number
CN202110666659.0A
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Chinese (zh)
Inventor
李建成
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Boardtek Electronics Corp
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Boardtek Electronics Corp
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Publication date
Application filed by Boardtek Electronics Corp filed Critical Boardtek Electronics Corp
Priority to CN202110666659.0A priority Critical patent/CN115483116A/en
Publication of CN115483116A publication Critical patent/CN115483116A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The application provides a packaging structure, which comprises at least one semiconductor, at least one connecting piece and a packaging body, wherein the connecting piece is arranged on the semiconductor, the connecting piece is electrically connected with the semiconductor, the packaging body wraps the semiconductor, and part of the connecting piece is exposed out of the packaging body. The application provides a packaging structure need not to set up miniature conducting hole, is favorable to improving the reliability that the semiconductor is electrically connected. In addition, the application also provides a manufacturing method of the packaging structure, and in addition, the application also provides a circuit board and a manufacturing method thereof.

Description

Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof
Technical Field
The application relates to a packaging structure and a manufacturing method thereof, and a circuit board and a manufacturing method thereof.
Background
Metal-oxide semiconductor field effect transistors (MOSFETs), which are common power semiconductors, are widely used in circuit boards to achieve power conversion and circuit control because of their advantages of small on-resistance, low loss, simple driving circuits, good thermal resistance, and the like. In the prior art, the power semiconductor is generally conducted with a circuit layer in a circuit board through a micro via hole after being embedded in the circuit board, but the micro via hole is difficult to process and has poor reliability.
Disclosure of Invention
To solve the problems involved in the prior art, the present application provides a package structure with a semiconductor.
In addition, it is also necessary to provide a manufacturing method having the above package structure.
In addition, it is also necessary to provide a circuit board having the above package structure.
In addition, a manufacturing method of the circuit board is also needed to be provided.
A manufacturing method of a package structure includes the steps of: a wafer is provided, the wafer including a plurality of semiconductors. And arranging a connecting plate on the wafer, wherein the connecting plate comprises a plurality of connecting pieces, and each connecting piece is electrically connected with at least one semiconductor to obtain a first intermediate. And arranging a packaging body at the outer side of the first intermediate body, wherein the packaging body wraps the wafer and the connecting plate. Removing a part of the packaging body corresponding to the connecting piece to obtain a second intermediate body, and dividing the second intermediate body to obtain a plurality of packaging structures, wherein each packaging structure comprises at least one semiconductor and at least one connecting piece electrically connected with the semiconductor.
A packaging structure comprises at least one semiconductor, at least one connecting piece and a packaging body, wherein the connecting piece is arranged on the semiconductor and is electrically connected with the semiconductor, the packaging body wraps the semiconductor, and part of the connecting piece is exposed out of the packaging body.
Furthermore, the semiconductor is a power semiconductor, and the connecting member includes a lead frame, a metal clip or a metal sheet.
Further, the semiconductor comprises a semiconductor body, a source electrode, a grid electrode and a drain electrode, wherein the source electrode and the grid electrode are arranged on one side of the semiconductor body, the drain electrode is arranged on the other side of the semiconductor body, the grid electrode is insulated from the drain electrode or the source electrode, and a PN junction is arranged between the drain electrode and the source electrode.
Further, the connecting element includes a connecting element body, an inner connecting pad and an outer connecting pad, the connecting element body is disposed between the inner connecting pad and the outer connecting pad, the inner connecting pad is electrically connected to the source, the gate or the drain, and the outer connecting pad is exposed from the package.
Furthermore, the package structure further comprises a conductor disposed between the inner pad and the source, the gate, or the drain.
A method of manufacturing a circuit board, comprising the steps of: providing a first circuit substrate, wherein the first circuit substrate comprises a dielectric layer and a copper foil layer arranged on the dielectric layer, and the first circuit substrate is provided with an opening.
Providing the above-mentioned package structure, and disposing the package structure in the opening. And electroplating the copper foil layer to form an electroplated layer, wherein the electroplated layer covers the connecting piece, and etching the electroplated layer and the copper foil layer to form a circuit layer which is electrically connected with the connecting piece. Providing a second circuit substrate and an adhesive layer, arranging the adhesive layer between the circuit layer and the second circuit substrate, and pressing the circuit board, the second circuit substrate and the adhesive layer to obtain the circuit board.
Further, the method also comprises the following steps: and arranging a through hole in the circuit board, wherein the through hole penetrates through the first circuit substrate, the bonding layer and the second circuit substrate, and arranging a conducting body in the through hole, and the conducting body is electrically connected with the circuit layer and the second circuit substrate.
A circuit board comprises a first circuit substrate, a second circuit substrate, an adhesive layer and the packaging structure, wherein the first circuit substrate comprises a dielectric layer and a circuit layer arranged on the dielectric layer, the first circuit substrate is provided with an opening, the packaging structure is arranged in the opening, the connecting piece is electrically connected with the circuit layer, and the adhesive layer is arranged between the second circuit substrate and the circuit layer.
Further, the thickness of the first circuit substrate is the same as the thickness of the package structure.
The application provides a packaging structure links together semiconductor and connecting piece through the packaging body, and connecting piece electric connection semiconductor, part expose in the connecting piece of packaging body can be used for the circuit layer in the connecting circuit board to need not to set up miniature conducting hole, be favorable to improving electric connection's reliability between semiconductor and the circuit layer.
Drawings
Fig. 1 is a schematic view of a semiconductor according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of the semiconductor device shown in fig. 1 after a first connecting element and a second connecting element are disposed.
Fig. 3 is a schematic diagram of a package structure for use in an embodiment of the present application.
Fig. 4 is a schematic view of a first circuit substrate according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of the first circuit substrate shown in fig. 4 after a package structure is disposed.
FIG. 6 is a schematic view of the first circuit board shown in FIG. 5 after a first plating layer and a second plating layer are formed by plating.
Fig. 7 is a schematic diagram of the first circuit substrate, the adhesive layer, and the second circuit substrate shown in fig. 6 before being laminated.
Fig. 8 is a schematic view of the first circuit substrate, the adhesive layer, and the second circuit substrate shown in fig. 6 after being laminated.
Fig. 9 is a schematic diagram of a circuit board according to an embodiment of the present application.
Description of the main elements
Package structure 100
Semiconductor 10
Semiconductor body 11
Source electrode 12
Grid 13
Drain electrode 14
First connecting member 21
First connection body 211
First inner connecting pad 212
First outer connecting pad 213
Second connecting member 22
Second connecting body 221
Second inner connecting pad 222
Second external connection pad 223
First conductor 231
Second electrical conductor 232
Package 30
First copper foil layer 41
Second copper foil layer 42
First dielectric layer 43
Opening 44
First plating layer 51
Second plating layer 52
First wiring layer 61
Second wiring layer 62
Circuit board 200
Conductive body 203
First circuit board 300
Third intermediate 301
Through hole 302
Second circuit board 400
Second dielectric layer 401
Third wiring layer 402
Thickness D1, D2
The following detailed description will further illustrate the present application in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present.
Referring to fig. 1 to 9, an embodiment of the present application provides a method for manufacturing a circuit board 200, including the steps of:
s1 referring to fig. 3, a package structure 100 is provided, where the package structure 100 includes at least one semiconductor 10, at least one first connector 21, at least one second connector 22, and a package body 30. The first connecting element 21 and the second connecting element 22 are disposed on opposite sides of the semiconductor 10. The first connecting element 21 and the second connecting element 22 are electrically connected to the semiconductor 10. The package 30 encapsulates the semiconductor 10, and a portion of the first connecting element 21 and the second connecting element 22 is exposed in the package 30.
In the present embodiment, the first connecting member 21 includes a first connecting body 211, a first inner connecting pad 212 and a first outer connecting pad 213, and the first inner connecting pad 212 and the first outer connecting pad 213 are respectively disposed on two opposite sides of the first connecting body 211. The second connecting member 22 includes a second connecting body 221, a second inner connecting pad 222 and a second outer connecting pad 223, wherein the second inner connecting pad 222 and the second outer connecting pad 223 are respectively disposed on two opposite sides of the second connecting body 221. The semiconductor 10 includes a semiconductor body 11, a source 12, a gate 13 and a drain 14, wherein the source 12 and the gate 13 are disposed on one side of the semiconductor body 11, and the drain 14 is disposed on the other side of the semiconductor body 11. The gate 13 is insulated from the drain 14 or the source 12, and there are two PN junctions between the drain 14 and the source 12. The first inner pad 212 is electrically connected to the source 12 and the gate 13, and the second inner pad 222 is electrically connected to the drain 14. The first outer connecting pad 213 and the second outer connecting pad 223 are exposed from the package body 30.
In this embodiment, referring to fig. 1 to fig. 3, in step S1, the manufacturing method of the package structure 100 includes:
s10, providing a wafer (not shown), wherein the wafer includes a plurality of semiconductors 10 (see fig. 1) arranged in a matrix, and the semiconductors 10 are power semiconductors.
S11, a first connecting board (not shown) is disposed on one side of the wafer, and a second connecting board (not shown) is disposed on the other side of the wafer, wherein the first connecting board includes a plurality of the first connecting members 21, the second connecting board includes a plurality of the second connecting members 22, referring to fig. 2, each of the semiconductors 10 corresponds to one of the first connecting members 21 and one of the second connecting members 22, and a first intermediate (not shown) is obtained. The first inner pad 212 is electrically connected to the source 12 and the gate 13, and the second inner pad 222 is electrically connected to the drain 14. The first connecting member 21 or the second connecting member 22 includes a lead frame, a metal clip or a metal sheet.
In this embodiment, referring to fig. 2, step S11 includes: a first conductor 231 is disposed between the first inner pad 212 and the source electrode 12 or the gate electrode 13, and a second conductor 232 is disposed between the second inner pad 222 and the drain electrode 14, wherein the first conductor 231 is used for connecting and electrically connecting the first inner pad 212 and the source electrode 12 or the gate electrode 13, and the second conductor 232 is used for connecting and electrically connecting the second inner pad 222 and the drain electrode 14. The material of the first conductor 231 and the second conductor 232 includes conductive adhesive, solder, and the like.
And S12, arranging the packaging body 30 on the outer side of the first intermediate body, wherein the packaging body 30 covers the wafer and the connecting plate.
Referring to fig. 3, portions of the package body 30 corresponding to the first outer connecting pad 213 and the second outer connecting pad 223 are removed, such that the first outer connecting pad 213 and the second outer connecting pad 223 are exposed outside the package body 30, and a second intermediate body (not shown) is obtained.
And S14, segmenting the second intermediate to obtain a plurality of packaging structures 100.
S2, referring to fig. 4, a first circuit substrate 300 is provided, where the first circuit substrate 300 includes a first copper foil layer 41, a second copper foil layer 42, and a first dielectric layer 43 disposed between the first copper foil layer 41 and the second copper foil layer 42, the first circuit substrate 300 has an opening 44, and the opening 44 sequentially penetrates through the first copper foil layer 41, the first dielectric layer 43, and the second copper foil layer 42.
S3, referring to fig. 5, the package structure 100 is disposed in the opening 44, the thickness D1 of the first circuit substrate 300 is substantially the same as the thickness D2 (see fig. 3) of the package structure 100, such that the outer side of the first outer connecting pad 213 is substantially flush with the outer side of the first copper foil layer 41, and the outer side of the second outer connecting pad 223 is substantially flush with the outer side of the second copper foil layer 42.
S4, referring to FIG. 6, a first electroplated layer 51 is formed on the first copper foil layer 41 by electroplating, and the first electroplated layer 51 covers the first external connecting pad 213; and forming a second plating layer 52 on the second copper foil layer 42 by plating, wherein the second plating layer 52 covers the second external connection pad 223.
S5, referring to fig. 7, the first copper foil layer 41 and the first plating layer 51 are etched to form a first circuit layer 61, and the second copper foil layer 42 and the second plating layer 52 are etched to form a second circuit layer 62, so as to obtain a third intermediate 301. The first circuit layer 61 is electrically connected to the first outer connecting pad 213, and the second circuit layer 62 is electrically connected to the second outer connecting pad 223.
S6, providing a second circuit substrate 400 and an adhesive layer 70, arranging the adhesive layer 70 between the third intermediate body 301 and the second circuit substrate 400, and laminating the third intermediate body 301, the adhesive layer 70 and the second circuit substrate 400 to obtain the circuit board 200.
In this embodiment, the second circuit board 400 includes a plurality of second dielectric layers 401 and a plurality of third circuit layers 402, the third circuit layers 402 are stacked with the second dielectric layers 401 in an interlaced manner, and the adhesive layer 70 is disposed between the outermost third circuit layer 402 and the first circuit layer 61. Step S6 is followed by: a through hole 302 is formed in the circuit board 200, the through hole 302 penetrates through the second circuit substrate 400, the adhesive layer 70 and the third intermediate body 301, and a via 203 is formed in the through hole 302, wherein the via 203 is electrically connected to the first circuit layer 61, the second circuit layer 62 and the plurality of third circuit layers 402.
Compared with the prior art, the manufacturing method of the circuit board 200 provided by the application has the following advantages:
firstly, the package structure 100 is prepared, the package structure 100 includes the semiconductor 10, the connecting component (the first connecting component 21, the second connecting component 22) and the package body 30 covering the semiconductor 10 and the connecting component, and then the package structure 100 is embedded into the circuit board 200, the package structure 100 electrically connects the circuit layers (the first circuit layer 61 and the second circuit layer 62) through the first outer connecting pad 213 or the second outer connecting pad 223, so that a micro via hole is not required to be arranged, the reliability of the circuit layers connected to the semiconductor 10 can be improved, and the method has simple steps.
The package structure 100 is electrically connected to the circuit layer through the first outer connecting pad 213 or the second outer connecting pad 223, and the area of the first outer connecting pad 213 and the second outer connecting pad 223 is significantly increased compared to the micro via hole, so as to increase the efficiency of the semiconductor 10 in transferring heat to the circuit board or the external environment through the first outer connecting pad 213 or the second outer connecting pad 223.
And thirdly, the packaging structure 100 is prepared first, and then the packaging structure 100 is tested, so that the yield of the final circuit board 200 can be effectively improved.
Fourthly, the risk of damage to the semiconductor 10 during the lamination process can be reduced by preparing the package structure 100, then embedding the package structure 100 into the circuit board 200, and finally laminating the circuit board 200.
Referring to fig. 9, the present application further provides a circuit board 200, where the circuit board 200 includes a first circuit substrate 300, a second circuit substrate 400, an adhesive layer 70 and the package structure 100, the first circuit substrate 300 includes a first dielectric layer 43 and a first circuit layer 61 disposed on the first dielectric layer 43, the first circuit substrate 300 is provided with an opening 44, the package structure 100 is disposed in the opening 44, the first connecting element 21 is electrically connected to the first circuit layer 61, and the adhesive layer 70 is disposed between the second circuit substrate 400 and the first circuit layer 60.
The above description is only an optimized specific embodiment of the present application, but in practical application, the present application is not limited to this embodiment. Other modifications and variations to the technical concept of the present application should fall within the scope of the present application for those skilled in the art.

Claims (10)

1. A method for manufacturing a package structure, comprising the steps of:
providing a wafer, wherein the wafer comprises a plurality of semiconductors;
arranging a connecting plate on the wafer, wherein the connecting plate comprises a plurality of connecting pieces, and each connecting piece is electrically connected with at least one semiconductor to obtain a first intermediate;
arranging a packaging body on the outer side of the first intermediate body, wherein the packaging body wraps the wafer and the connecting plate;
removing a part of the packaging body corresponding to the connecting piece to obtain a second intermediate body; and
and cutting the second intermediate body to obtain a plurality of packaging structures, wherein each packaging structure comprises at least one semiconductor and at least one connecting piece electrically connected with the semiconductor.
2. A packaging structure is characterized by comprising at least one semiconductor, at least one connecting piece and a packaging body, wherein the connecting piece is arranged on the semiconductor and is electrically connected with the semiconductor, the packaging body wraps the semiconductor, and part of the connecting piece is exposed out of the packaging body.
3. The package structure of claim 2, wherein the semiconductor is a power semiconductor and the connector comprises a leadframe, a metal clip, or a metal sheet.
4. The package structure of claim 2, wherein the semiconductor comprises a semiconductor body, a source, a gate, and a drain, the source and the gate being disposed on one side of the semiconductor body, the drain being disposed on the other side of the semiconductor body, the gate being insulated from the drain or the source, and a PN junction being disposed between the drain and the source.
5. The package structure of claim 4, wherein the connecting element comprises a connecting element body, an inner connecting pad and an outer connecting pad, the connecting element body is disposed between the inner connecting pad and the outer connecting pad, the inner connecting pad is electrically connected to the source, the gate or the drain, and the outer connecting pad is exposed from the package body.
6. The package structure of claim 5, further comprising an electrical conductor disposed between the inner bonding pad and the source, the gate, or the drain.
7. A method of manufacturing a circuit board, comprising the steps of:
providing a first circuit substrate, wherein the first circuit substrate comprises a dielectric layer and a copper foil layer arranged on the dielectric layer, and the first circuit substrate is provided with an opening;
providing a package structure according to any one of claims 2 to 6, said package structure being arranged within said opening;
electroplating the copper foil layer to form an electroplated layer, wherein the electroplated layer covers the connecting piece;
etching the electroplated layer and the copper foil layer to form a circuit layer, wherein the circuit layer is electrically connected with the connecting piece;
providing a second circuit substrate and an adhesive layer, arranging the adhesive layer between the circuit layer and the second circuit substrate, and pressing the circuit board, the second circuit substrate and the adhesive layer to obtain the circuit board.
8. The method of manufacturing of claim 7, further comprising the steps of:
arranging a through hole on the circuit board, wherein the through hole penetrates through the first circuit substrate, the bonding layer and the second circuit substrate; and the number of the first and second groups,
and arranging a conducting body in the through hole, wherein the conducting body is electrically connected with the circuit layer and the second circuit substrate.
9. A circuit board, comprising a first circuit substrate, a second circuit substrate, an adhesive layer and the package structure of any one of claims 2 to 6, wherein the first circuit substrate comprises a dielectric layer and a circuit layer disposed on the dielectric layer, the first circuit substrate is provided with an opening, the package structure is disposed in the opening, the connecting member is electrically connected to the circuit layer, and the adhesive layer is disposed between the second circuit substrate and the circuit layer.
10. The circuit board of claim 9, wherein a thickness of the first circuit substrate is the same as a thickness of the encapsulation structure.
CN202110666659.0A 2021-06-16 2021-06-16 Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof Pending CN115483116A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110666659.0A CN115483116A (en) 2021-06-16 2021-06-16 Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110666659.0A CN115483116A (en) 2021-06-16 2021-06-16 Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN115483116A true CN115483116A (en) 2022-12-16

Family

ID=84420048

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110666659.0A Pending CN115483116A (en) 2021-06-16 2021-06-16 Packaging structure and manufacturing method thereof, circuit board and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN115483116A (en)

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