CN113035724B - Multi-chip packaging structure and manufacturing method thereof - Google Patents
Multi-chip packaging structure and manufacturing method thereof Download PDFInfo
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- CN113035724B CN113035724B CN202110195619.2A CN202110195619A CN113035724B CN 113035724 B CN113035724 B CN 113035724B CN 202110195619 A CN202110195619 A CN 202110195619A CN 113035724 B CN113035724 B CN 113035724B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 51
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 66
- 229910052751 metal Inorganic materials 0.000 claims abstract description 66
- 239000000758 substrate Substances 0.000 claims abstract description 63
- 238000001465 metallisation Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 19
- 238000000059 patterning Methods 0.000 claims description 17
- 239000000126 substance Substances 0.000 claims description 6
- 230000007797 corrosion Effects 0.000 claims description 4
- 238000005260 corrosion Methods 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 10
- 238000003384 imaging method Methods 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 229910052802 copper Inorganic materials 0.000 abstract description 3
- 239000010949 copper Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000003989 dielectric material Substances 0.000 abstract description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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Abstract
The invention discloses a multi-chip packaging structure and a manufacturing method thereof. The multi-core module packaging is completed through the technological processes of copper substrate imaging, crystal fixing and conductive layer connection, dielectric material or top conductive layer manufacturing, dielectric imaging and hole forming, hole metallization, metal imaging on the dielectric, middle dielectric layer manufacturing, integral hole processing, hole metallization or dielectric filling, upper/lower metal imaging and the like; the whole process is completely compatible with PCB equipment and processes, and the obtained multi-core module has the advantages of simple structure, short electrical path, short heat dissipation path, excellent low resistance characteristic and heat dissipation effect, and can realize the effects of miniaturization, lightness and thinness.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a multi-chip packaging structure and a manufacturing method thereof.
Background
MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOSFET) and IGBT (Insulated Gate Bipolar Transistor) power modules are almost applied to all power industry products, and power devices are developed towards high-performance, fast, and multi-chip connection packaging. Conventional wire bonding and double-sided copper Clip interconnection processes have difficulty meeting these high performance, fast speed, multi-chip connection packaging and modular requirements. In the future, the power semiconductor packaging technology will develop towards more excellent PLFO (Panel level Fan-out) process-based packaging.
Disclosure of Invention
In view of the deficiencies of the prior art, the present invention provides a multi-chip package structure and a method for manufacturing the same. The multi-core packaging structure provided by the invention adopts a packaging scheme of double-sided heat dissipation. The traditional Wire Bonding is replaced by metal filling interconnection, and the PCB manufacturing process is based on the PCB manufacturing process, so that the PCB has the characteristics of excellent reliability and functionality, low cost and the like.
In the invention, the multi-core module packaging is completed through the technological processes of copper substrate imaging, crystal solidification and conductive layer connection, dielectric material or top conductive layer manufacturing, dielectric imaging and hole opening, hole metallization, metal imaging on the dielectric, middle dielectric layer manufacturing, whole hole processing, hole metallization or dielectric filling, upper/lower metal imaging and the like. The conductive layers on the first dielectric layer and the second dielectric layer can be directly laminated and coated to manufacture the seventh conductive layer and the eighth conductive layer, and can also be directly metalized to manufacture the third conductive layer and the fourth conductive layer after the first dielectric layer and the second dielectric layer are holed. The invention is realized by adopting the following technical scheme.
The invention provides a method for manufacturing a multi-chip packaging structure, which comprises the following specific steps:
step 1: providing a first patterned metal substrate and a second patterned metal substrate;
step 2: respectively manufacturing a first conducting layer and a second conducting layer on a first metal substrate and a second metal substrate, and respectively placing a first chip and a second chip on the first conducting layer and the second conducting layer;
and 3, step 3: manufacturing a first dielectric layer based on the first metal substrate, the side edge of the first conducting layer and the first chip, and manufacturing a second dielectric layer based on the second metal substrate, the side edge of the second conducting layer and the second chip;
and 4, step 4: opening a hole right above the first chip and the second chip;
and 5: metallizing the inner hole walls of the first dielectric layer and the second dielectric layer after the holes are formed and the upper surfaces of the first dielectric layer and the second dielectric layer after the holes are formed, and respectively manufacturing a third conductive layer and a fourth conductive layer;
and 6: and patterning the third conductive layer and the fourth conductive layer by chemical and physical corrosion modes to expose part of the first dielectric layer and part of the second dielectric layer.
And 7: placing the first metal substrate, the first conducting layer, the first chip and the third conducting layer in an inverted mode, and manufacturing a third dielectric layer between the third conducting layer and the fourth conducting layer;
and step 8: the module is provided with a through hole, and the first metal substrate, the second metal substrate, the third conducting layer, the fourth conducting layer, the first dielectric layer, the second dielectric layer and the third dielectric layer penetrate through the through hole;
and step 9: metallizing the through hole and the surfaces of the first metal substrate and the second metal substrate to respectively manufacture a fifth conducting layer and a sixth conducting layer, wherein the other two conducting layers are in contact with the surfaces and the side edges of the first metal substrate and the second metal substrate, the side edges of the third conducting layer and the fourth conducting layer, the side edges of the first dielectric layer and the second dielectric layer and the side edge of the third dielectric layer; the holes are filled with metallization or side wall metallization, and the middle of the holes is made of nonmetal;
step 10: and patterning the fifth conductive layer and the sixth conductive layer to expose part of the first dielectric layer and the second dielectric layer, thereby completing the logic manufacture of the module.
In the present invention, step 3 further comprises: manufacturing a seventh conducting layer and an eighth conducting layer on the first dielectric layer and the second dielectric layer; step 4 comprises a process of patterning the seventh conductive layer and the eighth conductive layer; and replacing the steps from step 5 to step 10 as follows:
and 5: metalizing the inner walls of the holes of the first dielectric layer and the second dielectric layer after the holes are formed and the upper surfaces of the seventh conducting layer and the eighth conducting layer after the holes are formed, and manufacturing a third conducting layer and a fourth conducting layer;
and 6: patterning the third conducting layer, the fourth conducting layer, the seventh conducting layer and the eighth conducting layer in a chemical and physical corrosion mode to expose partial first dielectric layer and partial second dielectric layer;
and 7: placing the first metal substrate, the first conducting layer, the first chip, the seventh conducting layer and the third conducting layer in an inverted mode, and manufacturing a third dielectric layer among the seventh conducting layer, the third conducting layer, the eighth conducting layer and the fourth conducting layer;
and 8: manufacturing a through hole on the module, and penetrating the first metal substrate, the second metal substrate, the seventh conducting layer, the eighth conducting layer, the third conducting layer, the fourth conducting layer, the first dielectric layer, the second dielectric layer and the third dielectric layer;
and step 9: metallizing the through hole and the surfaces of the first metal substrate and the second metal substrate to manufacture a fifth conducting layer and a sixth conducting layer, wherein the conducting layers are in contact with the surfaces and the side edges of the first metal substrate and the second metal substrate, the seventh conducting layer, the side edge of the eighth conducting layer, the third conducting layer and the side edge of the fourth conducting layer, the side edges of the first dielectric layer and the second dielectric layer and the side edge of the third dielectric layer; the holes can be completely filled with metallization or side wall metallization and non-metallization manufacturing;
step 10: and patterning the fifth conductive layer and the sixth conductive layer to expose part of the first dielectric layer and the second dielectric layer, thereby completing the logic manufacture of the module.
The invention further provides a multi-chip packaging structure obtained by the manufacturing method.
Compared with the Wire Bonding technology in the prior art, the invention has the beneficial effects that:
1. compared with the traditional process, the structure is simpler, the electric path is short, the heat dissipation path is short, the low resistance characteristic and the heat dissipation effect are excellent, and the effects of miniaturization, lightness and thinness can be realized;
2. the invention has the advantages of special technique, simultaneous encapsulation of multiple chips of Face down and Face up, and flexible interconnection
And (4) characteristics. The Face Downm chip can dissipate heat through the Top surface, and the Face Up chip can dissipate heat through the Bottom surface, so that the Face Down chip has an excellent double-sided heat dissipation function;
3. the whole process is completely compatible with PCB equipment and process, can realize double-sided heat dissipation, and has more excellent electrical property,
And (4) heat dissipation property.
Drawings
Fig. 1 is step 1 metal substrate patterning in example 1.
FIG. 2 shows die attachment in step 2 of example 1.
FIG. 3 is step 3 chip dielectric overlay in example 1.
FIG. 4 is step 4 dielectric blinding in example 1.
Fig. 5 shows surface and hole metallization in step 5 of example 1.
FIG. 6 is a step 6 inner layer patterning in example 1.
Fig. 7 is a step 7 three-dimensional stacking in example 1.
FIG. 8 is a step 8 through-hole formation in example 1.
Fig. 9 is the surface and through hole metallization of step 9 in example 1.
Fig. 10 is a step 10 surface patterning in example 1.
Detailed Description
The technical scheme of the invention is explained in detail in the following by combining the drawings and the embodiment.
Example 1
In an embodiment, a novel chip package structure is provided, and a manufacturing method thereof is as follows:
s101, providing a first metal substrate 101 and a second metal substrate 102 (fig. 1) for patterning.
S102, a first conductive layer 201 and a second conductive layer 202 are formed on the first metal substrate 101 and the second metal substrate 102, and a first chip 203 and a first chip 204 are respectively disposed on the first conductive layer 201 and the second conductive layer 202 (fig. 2).
S103, fabricating a first dielectric layer 301 and a second dielectric layer 302 on the first metal substrate 101, the second metal substrate 102, the side edge of the first conductive layer 201, the side edge of the second conductive layer 202, the first chip 203 and the second chip 204, and fabricating a seventh conductive layer 303 and an eighth conductive layer 304 on the first dielectric layer 301 and the second dielectric layer 302. The seventh conductive layer 303 and the eighth conductive layer 304 may not be formed (fig. 3).
S104, the seventh conductive layer 303, and the eighth conductive layer 304 are patterned on the first chip 203 and the second chip 204
Openings are made directly above or directly above the first chip 203 and the second chip 204 (fig. 4).
S105, metalizing the inner walls of the holes of the first dielectric layer 301 and the second dielectric layer 302 after the holes are formed, the upper surfaces of the seventh conductive layer 303, the eighth conductive layer 304, the seventh conductive layer 303 and the eighth conductive layer 304 to manufacture a third conductive layer 501 and a fourth conductive layer 502;
or the inner walls of the holes of the first dielectric layer 301 and the second dielectric layer 302 after the holes are opened and the first dielectric layer 301 and the second dielectric layer after the holes are opened
The upper surface of the layer 302 is metallized to form a third conductive layer 501 and a fourth conductive layer 502 (fig. 5).
S106, patterning the third conductive layer 501, the fourth conductive layer 502, the seventh conductive layer 303, and the eighth conductive layer 304 by chemical and physical etching to expose a portion of the first dielectric layer 301 and the second dielectric layer 302.
Or patterning the third conductive layer 501 and the fourth conductive layer 502 by chemical and physical etching to expose a portion of the first dielectric layer 301 and the second dielectric layer 302 (fig. 6).
S107, inversely placing the first metal substrate 101, the first conducting layer 201, the first chip 203, the seventh conducting layer 303 and the third conducting layer 501, and manufacturing a third dielectric layer 701 among the seventh conducting layer 303, the third conducting layer 501, the eighth conducting layer 304 and the fourth conducting layer 502;
or the first metal substrate 101, the first conductive layer 201, the first chip 203 and the third conductive layer 501 are patterned
A third dielectric layer 701 is formed between the third conductive layer 501 and the fourth conductive layer 502 by placing them upside down (fig. 7).
S108, making a through hole in the module, and making the first metal substrate 101, the second metal substrate 102, the seventh conductive layer 303, the eighth conductive layer 304, the third conductive layer 501, the fourth conductive layer 502, the first dielectric layer 301, the second dielectric layer 302, and the third dielectric layer 701 penetrate through the through hole;
or making a through hole in the module, and forming the first metal substrate 101, the second metal substrate 102, the third conductive layer 501, and the third conductive layer
The four conductive layers 502, the first dielectric layer 301, the second dielectric layer 302, and the third dielectric layer 701 penetrate through (fig. 8).
S109, metallizing the through hole and the surfaces of the first metal substrate 101 and the second metal substrate 102 to form a fifth conductive layer 901 and a sixth conductive layer 902, wherein the conductive layers are in contact with the surfaces and the sides of the first metal substrate 101 and the second metal substrate 102, the seventh conductive layer 303, the side of the eighth conductive layer 304, the side of the third conductive layer 501 and the fourth conductive layer 502, the side of the first dielectric layer 301, the side of the second dielectric layer 302 and the side of the third dielectric layer 701; the holes can be filled with metallization or side wall metallization and made of middle non-metallization.
Or metallizing the through hole and the surfaces of the first metal substrate 101 and the second metal substrate 102 to manufacture a fifth conductive layer 901 and a sixth conductive layer 902, wherein the conductive layers are in contact with the side edges of the first metal substrate 101 and the second metal substrate 102, the third conductive layer 501, the fourth conductive layer 502, the first dielectric layer 301, the second dielectric layer 302 and the third dielectric layer 701; the holes may be filled entirely with metallization or with sidewall metallization intermediate non-metallization (fig. 9).
S110, patterning the fifth conductive layer 901 and the sixth conductive layer 902 to expose a part of the first dielectric layer 301 and the second dielectric layer 302, and completing the module logic manufacturing. Finally, the multi-core module package is completed through a cutting test (figure 10).
The whole process is completely compatible with PCB equipment and processes, and the obtained multi-core module has the advantages of simple structure, short electrical path, short heat dissipation path, excellent low resistance characteristic and heat dissipation effect, and can realize the effects of miniaturization, lightness and thinness.
Claims (3)
1. A manufacturing method of a multi-chip packaging structure is characterized by comprising the following specific steps:
the conductive layers on the first dielectric layer (301) and the second dielectric layer (302) can be directly pressed and coated to manufacture the seventh conductive layer (303) and the eighth conductive layer (304), or can be directly metalized after the first dielectric layer (301) and the second dielectric layer (302) are perforated to manufacture the third conductive layer (501) and the fourth conductive layer (502)
Step 1: providing a first patterned metal substrate (101) and a second patterned metal substrate (102);
and 2, step: respectively manufacturing a first conductive layer (201) and a second conductive layer (202) on a first metal substrate (101) and a second metal substrate (102), and respectively placing a first chip (203) and a second chip (204) on the first conductive layer (201) and the second conductive layer (202);
and 3, step 3: manufacturing a first dielectric layer (301) based on a first metal substrate (101), the side edge of a first conductive layer (201) and a first chip (203), and manufacturing a second dielectric layer (302) based on a second metal substrate (102), the side edge of a second conductive layer (202) and a second chip (204);
and 4, step 4: forming a hole right above the first chip (203) and the second chip (204);
and 5: metalizing the inner wall of the hole after the first dielectric layer (301) and the second dielectric layer (302) are opened and the upper surfaces of the first dielectric layer (301) and the second dielectric layer (302) to respectively manufacture a third conductive layer (501) and a fourth conductive layer (502);
and 6: patterning the third conductive layer (501) and the fourth conductive layer (502) in a chemical and physical corrosion mode to expose part of the first dielectric layer (301) and the second dielectric layer (302);
and 7: inversely placing a first metal substrate (101), a first conducting layer (201), a first chip (203) and a third conducting layer (501), and manufacturing a third dielectric layer (701) between the third conducting layer (501) and a fourth conducting layer (502);
and step 8: the method comprises the steps that through holes are formed in a module, and a first metal substrate (101) and a second metal substrate (102), a third conducting layer (501) and a fourth conducting layer (502), a first dielectric layer (301), a second dielectric layer (302) and a third dielectric layer (701) are penetrated through;
and step 9: metallizing the through hole and the surfaces of the first metal substrate (101) and the second metal substrate (102) to respectively manufacture a fifth conducting layer (901) and a sixth conducting layer (902), wherein the other two conducting layers are in contact with the surfaces and the side edges of the first metal substrate (101) and the second metal substrate (102), the third conducting layer (501) and the fourth conducting layer (502), the first dielectric layer (301), the second dielectric layer (302) and the third dielectric layer (701); the holes are filled with metallization or side wall metallization and are made of non-metallization;
step 10: and patterning the fifth conductive layer (901) and the sixth conductive layer (902) to expose part of the first dielectric layer (301) and the second dielectric layer (302) to complete the logic manufacture of the module.
2. The method of claim 1, wherein step 3 further comprises: manufacturing a seventh conducting layer (303) and an eighth conducting layer (304) on the first dielectric layer (301) and the second dielectric layer (302); the step 4 includes a process of patterning the seventh conductive layer (303) and the eighth conductive layer (304); and replacing the steps from step 5 to step 10 as follows:
and 5: metalizing the upper surfaces of the first dielectric layer (301), the second dielectric layer (302), the seventh conducting layer (303), the eighth conducting layer (304), the seventh conducting layer (303) and the eighth conducting layer (304) after the holes are formed, and manufacturing a third conducting layer (501) and a fourth conducting layer (502);
and 6: patterning the third conductive layer (501), the fourth conductive layer (502), the seventh conductive layer (303) and the eighth conductive layer (304) in a chemical and physical corrosion mode to expose part of the first dielectric layer (301) and the second dielectric layer (302);
and 7: the method comprises the steps that a first metal substrate (101), a first conducting layer (201), a first chip (203), a seventh conducting layer (303) and a third conducting layer (501) are placed in an inverted mode, and a third dielectric layer (701) is manufactured among the seventh conducting layer (303), the third conducting layer (501), an eighth conducting layer (304) and a fourth conducting layer (502);
and step 8: manufacturing a through hole in the module, and penetrating a first metal substrate (101), a second metal substrate (102), a seventh conducting layer (303), an eighth conducting layer (304), a third conducting layer (501), a fourth conducting layer (502), a first dielectric layer (301), a second dielectric layer (302) and a third dielectric layer (701);
and step 9: metallizing the through hole and the surfaces of the first metal substrate (101) and the second metal substrate (102) to manufacture a fifth conducting layer (901) and a sixth conducting layer (902), wherein the conducting layers are in contact with the first metal substrate (101), the surface and the side of the second metal substrate (102), the seventh conducting layer (303), the side of the eighth conducting layer (304), the third conducting layer (501) and the side of the fourth conducting layer (502), the first dielectric layer (301), the second dielectric layer (302) and the third dielectric layer (701); the holes can be completely filled with metallization or side wall metallization and non-metallization manufacturing;
step 10: and patterning the fifth conductive layer (901) and the sixth conductive layer (902) to expose part of the first dielectric layer (301) and the second dielectric layer (302) to complete the logic manufacture of the module.
3. A multi-chip package structure obtained by the manufacturing method according to any one of claims 1-2.
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| CN202110195619.2A CN113035724B (en) | 2021-02-22 | 2021-02-22 | Multi-chip packaging structure and manufacturing method thereof |
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| CN202110195619.2A CN113035724B (en) | 2021-02-22 | 2021-02-22 | Multi-chip packaging structure and manufacturing method thereof |
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| CN113035724A CN113035724A (en) | 2021-06-25 |
| CN113035724B true CN113035724B (en) | 2022-07-22 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101772841A (en) * | 2007-08-07 | 2010-07-07 | 美光科技公司 | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
| CN110211931A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of three-dimension packaging structure and its manufacturing method |
| CN110335851A (en) * | 2019-06-27 | 2019-10-15 | 深圳第三代半导体研究院 | A kind of novel chip-packaging structure and preparation method thereof |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101772841A (en) * | 2007-08-07 | 2010-07-07 | 美光科技公司 | Packaged integrated circuit devices with through-body conductive vias, and methods of making same |
| CN110211931A (en) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | A kind of three-dimension packaging structure and its manufacturing method |
| CN110335851A (en) * | 2019-06-27 | 2019-10-15 | 深圳第三代半导体研究院 | A kind of novel chip-packaging structure and preparation method thereof |
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