CN112218016B

CN112218016B - Display device

Info

Publication number: CN112218016B
Application number: CN201910616404.6A
Authority: CN
Inventors: 黄飞; 李见
Original assignee: Hisense Visual Technology Co Ltd
Current assignee: Hisense Visual Technology Co Ltd
Priority date: 2019-07-09
Filing date: 2019-07-09
Publication date: 2021-11-12
Anticipated expiration: 2039-07-09
Also published as: CN112218016A

Abstract

The invention discloses a display device, which comprises a circuit board, wherein the circuit board is provided with at least 2 first I2S bus interfaces; a receiving circuit for receiving sound source data having a plurality of channels; the initial decoding circuit is used for decoding sound source data into original audio data corresponding to each sound channel; the recoding circuit is electrically connected with the at least 2 first I2S bus interfaces and is used for recoding the original audio data according to a preset coding rule and outputting the recoded data through the at least 2 first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all first I2S bus interfaces. Therefore, the original audio data corresponding to all the sound channels in the sound source file can be transmitted to the multi-channel equipment, and the playing effect of the multi-channel equipment is further improved.

Description

Display device

Technical Field

The invention relates to the technical field of display, in particular to a display device.

Background

In order to achieve true and full sound effect, a multi-channel recording sound source file is usually adopted. However, when a sound source file with multiple channels is transmitted and played, due to the limitation of transmission conditions, all the channels in the sound source file cannot be transmitted to a power amplifier during transmission, so that output of multiple channels cannot be realized during playing, and the playing effect is poor.

Disclosure of Invention

The display device provided by the embodiment of the invention is used for improving the playing effect.

The circuit board is provided with at least 2 first I2S bus interfaces;

a receiving circuit for receiving sound source data having a plurality of channels;

the initial decoding circuit is used for decoding the sound source data to obtain original audio data corresponding to each sound channel;

the recoding circuit is electrically connected with the at least 2 first I2S bus interfaces and is used for recoding the original audio data according to a preset coding rule and outputting the recoded original audio data through the at least 2 first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all of the first I2S bus interfaces.

Optionally, the method further includes: a re-decode circuit electrically connected to the at least 2 first I2S bus interfaces;

the re-decoding circuit is used for receiving the target audio data transmitted by each first I2S bus interface according to a second frame clock and a second bit clock, and re-decoding the received data according to the preset coding rule to obtain each original audio data; the timing of the second frame clock is the same as the timing of the first frame clock, and the timing of the second bit clock is the same as the timing of the first bit clock.

Optionally, after re-encoding the original audio data according to a preset encoding rule, outputting the re-encoded original audio data through at least 2 first I2S bus interfaces, including:

determining target audio data corresponding to each channel of each first I2S bus interface according to all the original audio data, the total number of channels of all the first I2S bus interfaces and the communication rule of each channel of the first I2S bus interface; wherein the data bits of the target audio data are larger than the data bits of the original audio data;

and outputting the obtained target audio data through a channel of the corresponding first I2S bus interface.

Optionally, the determining target audio data corresponding to each channel of each first I2S bus interface includes:

upon determining that the quantity Q of all of the original audio data satisfies the formula:

and is

Then, and is added to all the original audio data

The same amount of blank original audio data, and selecting all the original audio data and the generated blank original audio data

Splitting original audio data to generate split audio data; wherein N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces, the data bits of the blank original audio data and the original audioThe data bits of the data are the same;

will be provided with

An original audio data and

each split audio data is combined into one target audio data.

then, selecting from all the original audio data

Splitting original audio data to generate split audio data; wherein, N is a positive even number, and M represents the total number of channels of all the first I2S bus interfaces;

will be provided with

An original audio data and

and splicing the split audio data into the target audio data.

Optionally, split audio data in two target audio data corresponding to the same I2S bus interface belongs to the same original audio data.

Optionally, the plurality of channels includes: the sound system comprises a left sound channel, a right sound channel, a left surrounding sound channel, a right surrounding sound channel, a left sky sound channel, a right sky sound channel, a middle sound channel and a subwoofer sound channel;

selecting the split original audio data comprises: and the original audio data corresponding to the middle audio channel and the original audio data corresponding to the subwoofer audio channel.

Optionally, the outputting the obtained target audio data through a channel of a corresponding first I2S bus interface includes:

changing the sampling bit number of a first bit clock and/or changing the sampling frequency of the first bit clock, and transmitting data bits of a single channel according to the first bit clock at the beginning of the pulse of the 2 nd first bit clock after the edge change of a first frame clock, so that each first I2S bus interface transmits target audio data of two channels in one period of one first frame clock;

wherein the number of sampling bits of the first bit clock is the same as the number of data bits of the target audio data.

Optionally, after the re-encoding the original audio data according to a preset encoding rule and outputting the re-encoded original audio data through at least 2 first I2S bus interfaces, the method further includes:

receiving target audio data transmitted by each first I2S bus interface according to a second frame clock and a second bit clock, and re-decoding the received data according to the preset coding rule to obtain each original audio data; the timing of the second frame clock is the same as the timing of the first frame clock, and the timing of the second bit clock is the same as the timing of the first bit clock.

Optionally, the receiving, according to a second frame clock and a second bit clock, the target audio data transmitted by each of the first I2S bus interfaces includes:

receiving the target audio data transmitted by each first I2S bus interface according to one second frame clock and one second bit clock; alternatively, the first and second electrodes may be,

receiving target audio data transmitted by each first I2S bus interface according to a plurality of second frame clocks and a plurality of second bit clocks; wherein a first I2S bus interface corresponds to a second frame clock and a second bitclock.

The invention has the following beneficial effects:

according to the display device provided by the embodiment of the invention, the original audio data corresponding to each channel is decoded from the sound source data, and the total number of the channels is greater than the total number of the channels of all the first I2S bus interfaces, so that the original audio data of all the channels can be output through at least 2 first I2S bus interfaces after being recoded according to the preset coding rule. Therefore, the original audio data corresponding to all the sound channels in the sound source file can be transmitted to the multi-channel equipment, and the playing effect of the multi-channel equipment is further improved.

Drawings

FIG. 1 is a signal timing diagram of an I2S bus interface according to an embodiment of the present invention;

FIG. 2 is a flowchart of an audio processing method according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a multi-channel device according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating original audio data according to an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating an output of the first I2S bus interface according to an embodiment of the present invention;

FIG. 6 is a timing diagram illustrating an embodiment of the present invention for receiving data output from the first I2S bus interface;

FIG. 7 is a timing diagram illustrating an embodiment of the present invention for intercepting data in target audio data;

FIG. 8 is a second schematic diagram of original audio data according to an embodiment of the present invention;

FIG. 9 is a third schematic diagram of original audio data according to an embodiment of the present invention;

FIG. 10 is a second timing diagram illustrating the output of data from the first I2S bus interface according to the present invention;

FIG. 11a is a second timing diagram illustrating the process of receiving data output from the first I2S bus interface according to the second embodiment of the present invention;

FIG. 11b is a third timing diagram illustrating the receiving of data output from the first I2S bus interface according to the present invention;

FIG. 11c is a fourth timing diagram illustrating the receiving of data output by the first I2S bus interface according to the present invention;

FIG. 12 is a second timing diagram illustrating the capturing of data in the target audio data according to the embodiment of the present invention;

FIG. 13a is a third timing diagram illustrating the output of data from the first I2S bus interface according to the present invention;

FIG. 13b is a fourth timing diagram illustrating the output of data from the first I2S bus interface according to the present invention;

FIG. 13c is a fifth timing diagram illustrating the output of data from the first I2S bus interface according to the present invention;

FIG. 14a is a fifth timing diagram illustrating the timing of receiving data output from the first I2S bus interface according to the present invention;

FIG. 14b is a sixth timing diagram illustrating the receiving of data output from the first I2S bus interface according to the present invention;

FIG. 14c is a seventh timing diagram illustrating the receiving of data output from the first I2S bus interface according to the present invention;

FIG. 15 is a third timing diagram illustrating the process of intercepting data in the target audio data according to the embodiment of the present invention;

FIG. 16 is a fourth schematic diagram of original audio data according to an embodiment of the present invention;

FIG. 17 is a sixth schematic timing diagram illustrating the output of data from the first I2S bus interface according to the present invention;

FIG. 18 is an eighth timing diagram illustrating the receiving of data output by the first I2S bus interface according to the present invention;

FIG. 19 is a fourth timing diagram illustrating the capturing of data in the target audio data according to the embodiment of the present invention;

fig. 20 is a schematic structural diagram of an audio processing apparatus according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the drawings of the embodiments of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. And the embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in the present application do not denote any order, quantity, or importance, but rather the terms are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the sizes and shapes of the figures in the drawings are not to be considered true scale, but are merely intended to schematically illustrate the present invention. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

With the rapid development of Display technology, Liquid Crystal Display (LCD), Organic Light Emitting Diode (OLED) Display, and the like have been used in life of people. These display devices may receive video data and sound source data and process these data to display images and output sound.

In general, in order to improve the experience, the sound source data may have a plurality of channels, for example, 8 channels, 9 channels, 12 channels, and the like. Illustratively, 8 channels may include: a left channel L, a right channel R, a left surround channel SL, a right surround channel SR, a left sky channel TOPL, a right sky channel TOPR, a center channel center, a subwoofer channel woofer. In order to enable the output of the above channels, the display device may be provided with a plurality of speakers so that one speaker plays the audio of one channel correspondingly. For example, as shown in fig. 3, the display device is provided with 8 speakers Y1 to Y8, wherein the speaker Y1 plays audio data corresponding to the left channel L, the speaker Y2 plays audio data corresponding to the right channel R, the speaker Y3 plays audio data corresponding to the left surround channel SL, the speaker Y4 plays audio data corresponding to the right surround channel SR, the speaker Y5 plays audio data corresponding to the left sky channel TOPL, the speaker Y6 plays audio data corresponding to the right sky channel TOPR, the speaker Y7 plays audio data corresponding to the center channel center, and the speaker Y8 plays audio data corresponding to the subwoofer channel woofer, so that the display device plays these channels of the sound source data as a multi-channel device.

An I2S bus interface is generally used to transmit audio data to a display apparatus as a multi-channel device. No matter how many bits of data are valid, the most significant bit of data always appears at the 2 nd bit clock BCLK pulse after the occurrence edge of the frame clock WS (i.e., the beginning of a frame) in the I2S bus interface transport format signal. This allows the valid data bits to be different between the receiving end and the transmitting end. If the effective data bits which can be processed by the receiving end are less than that of the transmitting end, redundant low data bits in the data frame can be abandoned; if the receiving end can process more effective data bits than the transmitting end, the rest bits can be self-complemented. The synchronization mechanism facilitates the transmission of audio data by using the I2S bus interface and does not cause data dislocation.

However, the main chip for processing sound source data in the multi-channel device generally outputs audio data by using 2I 2S bus interfaces or 3I 2S bus interfaces, so that when the total number of channels of the I2S bus interfaces is less than the total number of channels of the audio data, audio data corresponding to a part of channels may be missing during transmission, thereby resulting in incomplete audio data transmitted to the multi-channel device and reducing the playing effect of the multi-channel device.

As shown in fig. 1, the signals of the I2S bus interface mainly involved in transmission are as follows:

(1) the serial clock BCLK, i.e., a bit clock, corresponds to each data bit of the digital audio signal, and the frequency of BCLK is 2 × sampling frequency × number of sampling bits. For example, BCLK has a frequency of 2 × 48KHz × 16bit of 1.536 MHz.

(2) And a frame clock WS for switching data of the left and right channels. For example, WS of "1" indicates that data of the left channel is being transmitted, and WS of "0" indicates that data of the right channel is being transmitted. The frequency of WS is equal to the sampling frequency.

(3) Serial data SDATA, audio data represented by two's complement.

Of course, in practical applications, the signals involved in the transmission of the I2S bus interface may also include some relevant signals, such as: the MCLK master clock (i.e. the system clock) is used to better synchronize the systems, and the frequency of MCLK is 256 or 384 times the sampling frequency, for example, 48KHz 256 to 12.288 MHz.

As shown in fig. 1, when the I2S bus interface is transmitting, WS is 0(WS is a low level signal), which indicates that Left Channel (Left Channel) data is being transmitted. WS is 1(WS is a high level signal), and indicates that data of a Right Channel (Right Channel) is being transmitted. That is, an I2S bus interface has two channels for transmitting audio data. Alternatively, WS may be set to 1(WS is a high level signal) to indicate that Left Channel (Left Channel) data is being transmitted. WS is 0(WS is a low level signal), and indicates that data of a Right Channel (Right Channel) is being transmitted. Of course, in practical applications, this needs to be determined according to the practical application environment, and is not limited herein.

As shown in fig. 1, one channel of the I2S bus interface transmits audio data corresponding to the left channel, and the other channel transmits audio data corresponding to the right channel. Also, WS may change at the rising or falling edge of the serial clock BCLK, and the WS signal need not necessarily be symmetrical. Generally, on the slave side, the most significant bit of data always appears at the pulse of the 2 nd bit clock BCLK after the falling edge of the frame clock WS (i.e., the start of a frame). I.e. WS always changes one clock cycle before the most significant bit transfer, which makes it possible for the slave to get time to synchronize with the serial DATA being transferred and for the receiver to store the current command and clear space for the next command.

An embodiment of the present invention provides an audio processing method, as shown in fig. 2, which may include the following steps:

s100, receiving sound source data with a plurality of sound channels;

s200, decoding the sound source data to obtain original audio data corresponding to each sound channel;

s300, recoding the original audio data according to a preset coding rule, and outputting the recoded original audio data through at least 2 first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all first I2S bus interfaces.

According to the audio processing method provided by the embodiment of the invention, the original audio data corresponding to each sound channel is decoded from the sound source data, and the total number of the sound channels is larger than the total number of the channels of all the first I2S bus interfaces, so that the original audio data of all the sound channels can be output through at least 2 first I2S bus interfaces after being recoded according to the preset coding rule. Therefore, the original audio data corresponding to all the sound channels in the sound source file can be transmitted to the multi-channel equipment, and the playing effect of the multi-channel equipment is further improved.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

The first embodiment,

In a specific implementation, in the embodiment of the present invention, after re-encoding the original audio data according to the preset encoding rule, the output is performed through at least 2 first I2S bus interfaces, which may include:

determining target audio data corresponding to each channel of each first I2S bus interface according to all original audio data, the total number of channels of all first I2S bus interfaces and the communication rule of each channel of the first I2S bus interface; wherein, the data bit of the target audio data is larger than the data bit of the original audio data;

In a specific implementation, in the embodiment of the present invention, determining target audio data corresponding to each channel of each first I2S bus interface may include:

upon determining that the quantity Q of all the original audio data satisfies the formula:

and is

Then, the sum is added to all the original audio data

The same amount of blank original audio data, and selecting all original audio data and the generated blank original audio data

Splitting original audio data to generate split audio data; wherein, N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces, and the data bits of the blank original audio data are the same as the data bits of the original audio data;

will be provided with

An original audio data and

the split audio data are combined into one target audio data.

For example, in implementation, in the embodiment of the present invention, the number of the first I2S bus interfaces may be 2, and the total number of channels of all the first I2S bus interfaces is 4, that is, M is 4. Since the total number of channels of the sound source data may be greater than the total number of channels of all the first I2S bus interfaces, the total number of channels may be made to be 5, 6, 8, 12, 16, etc., and is not limited herein.

For example, in practical implementation, in the embodiment of the present invention, the number of the first I2S bus interfaces may also be 3, and the total number of channels of all the first I2S bus interfaces is 6, that is, M is 6. Since the total number of channels of the sound source data may be greater than the total number of channels of all the first I2S bus interfaces, the total number of channels may be made to be 7, 8, 9, 12, 16, 18, 24, etc., and is not limited herein.

Of course, in practical applications, the number of the first I2S bus interfaces may be determined according to practical application environments, and is not limited herein.

For example, in the implementation, in the embodiment of the present invention, N may be 2, N may be 4, N may be 6, or the like. Of course, in practical applications, the number of N may be determined according to practical application environments, and is not limited herein.

The multi-channel device of the general Dolby panoramic sound (Dolby Atmos)5.1.2 technology can realize better sound effect. Illustratively, in particular implementations, in embodiments of the present invention, the plurality of channels may include: the sound channel comprises a left sound channel, a right sound channel, a left surrounding sound channel, a right surrounding sound channel, a left sky sound channel, a right sky sound channel, a middle sound channel and a subwoofer sound channel. Therefore, the sound source file can be played by adopting a multichannel device of Dolby panoramic sound (Dolby Atmos)5.1.2 technology. Of course, in practical applications, the specific channels of the channels may be designed according to the practical application environment, and are not limited herein.

Illustratively, in practical implementation, in an embodiment of the present invention, selecting the original audio data to be split includes: original audio data corresponding to the center channel and original audio data corresponding to the subwoofer channel. Therefore, the split data are spliced during subsequent decoding, and the original audio data corresponding to the middle audio channel and the original audio data corresponding to the subwoofer audio channel are obtained. Generally, when a multi-channel device plays sound, the influence of the center channel and the subwoofer channel on the playing effect is small. And in general, the transmission process may affect the split data, which is not beneficial to the subsequent decoding and splicing. According to the embodiment of the invention, the original audio data corresponding to the middle channel and the original audio data corresponding to the subwoofer channel are split, so that when the split data are influenced in the transmission process, the original audio data corresponding to the middle channel and the original audio data corresponding to the subwoofer channel can not be decoded in the following process, but the influence on the playing effect of the multi-channel equipment is small.

Typical digital sound recordings typically use 16bit (bit), 20bit or 24bit binary complements to make sound source files for music. Illustratively, in particular implementation, in the embodiment of the present invention, the original audio data may be made into a digital signal having K data bits. Illustratively, the original audio data may be a binary digital signal having 16 bits (i.e., K-16), 20 bits (i.e., K-20), or 24 bits (i.e., K-24).

Illustratively, in particular implementations, in embodiments of the present invention, one split audio data may be made to have adjacent ones

A digital signal of data bits; wherein K is a positive integer. For example, taking K-16 as an example, for example, a digital signal with original audio data of 0100001000011101, the original audio data may be split according to adjacent 8 data bits, so as to split into two split audio data: one split audio data is 01000010 and the other split audio data is 00011101. Illustratively, as shown in FIG. 4, having the original audio data ch6:16bit generates split audio data ch6: high 8bit, ch6: low 8 bit; original audio data ch7:16bit is made to generate split audio data ch7: high 8bit and ch7: low 8 bit; making the blank original audio data ch8:16bit generates split audio data ch8: high 8bit, ch8: low 8 bit.

Note that the blank original audio data does not carry audio information of a sound source, and it may be data formed with "0". For example, the original audio data is a digital signal of 0100001000011101, the blank original audio data may be a digital signal of 0000000000000000.

In order to improve the stability of transmission, reduce the time for subsequent decoding, and improve the efficiency of subsequent decoding, in a specific implementation, in the embodiment of the present invention, split audio data in two target audio data corresponding to the same first I2S bus interface may belong to the same original audio data.

In a specific implementation, in an embodiment of the present invention, outputting the obtained target audio data through a channel of the corresponding first I2S bus interface may include:

and changing the sampling bit number of the first bit clock, and transmitting the data bits of the single channel according to the first bit clock at the beginning of the pulse of the 2 nd first bit clock after the edge change of the first frame clock, so that each first I2S bus interface transmits the target audio data of two channels in one period of the first frame clock.

Illustratively, in particular implementations, in embodiments of the present invention, one cycle of the first bit clock transfers one data bit. That is, the first bit clock employs single edge sampling. For example, one data bit is sampled with the rising or falling edge of each cycle.

Illustratively, in particular implementations, in embodiments of the present invention, two data bits are transferred for one cycle of the first bit clock. That is, the first bit clock employs double edge sampling. For example, one data bit is sampled with the rising and falling edges of each cycle.

Illustratively, in implementation, in the embodiment of the present invention, the number of sampling bits of the first bit clock may be made the same as the data bits of the target audio data.

In specific implementation, in the embodiment of the present invention, after re-encoding the original audio data according to a preset encoding rule and outputting the re-encoded original audio data through at least 2 first I2S bus interfaces, the method may further include:

receiving target audio data transmitted by each first I2S bus interface according to a second frame clock and a second bit clock, and re-decoding the received data according to a preset coding rule to obtain each original audio data; the time sequence of the second frame clock is the same as that of the first frame clock, and the time sequence of the second bit clock is the same as that of the first bit clock. Thus, the target audio data transmitted by each first I2S bus interface can be stably received. And original audio data is restored.

In practical implementation, in the embodiment of the present invention, receiving the target audio data transmitted by each first I2S bus interface according to the second frame clock and the second bit clock may include: the target audio data transmitted by each of the first I2S bus interfaces may be received according to a second frame clock and a second bitclock. This can reduce the number of signals of the second frame clock and the second bit clock to be output.

In specific implementation, in the embodiment of the present invention, receiving the target audio data transmitted by each first I2S bus interface according to the second frame clock and the second bit clock may also include: receiving target audio data transmitted by each first I2S bus interface according to a plurality of second frame clocks and a plurality of second bit clocks; wherein a first I2S bus interface corresponds to a second frame clock and a second bit clock. Therefore, the target audio data transmitted by each first I2S bus interface can be independently received, so that transmission interference is avoided, and the transmission stability is improved.

Illustratively, in practical implementation, in the embodiment of the present invention, the data bits of the target audio data may be at most the data bits that can be transmitted by one channel of the first I2S bus interface. For example, a channel of the general first I2S bus interface can transmit 32-bit data, and the data bit of the target audio data can be up to 32-bit.

For example, in a specific implementation, in the embodiment of the present invention, after re-decoding the received data according to a preset encoding rule to obtain each original audio data, the method may further include: outputting each obtained original audio data to multi-channel equipment by adopting a plurality of second I2S bus interfaces; wherein the number of the second I2S bus interfaces is one half of all the channels. That is, one second I2S bus interface corresponds to two original audio data.

The following describes the audio processing method provided by the present invention with reference to fig. 4 to fig. 7 by taking 16 bits of original audio data and 3 first I2S bus interfaces as examples. The reader should appreciate that the specific process is not so limited. The 3 first I2S bus interfaces are I2S _0, I2S _1, and I2S _2, respectively. Fig. 5 and 6 are only for explaining the transmission process of the target audio data SD1_0 and the target audio data SD2_0 as an example.

The audio processing method provided by the embodiment of the invention can comprise the following steps:

(1) sound source data having a left channel, a right channel, a left surround channel, a right surround channel, a left sky channel, a right sky channel, a center channel, and a subwoofer channel is received. The sound source data may be stored in a USB storage medium, or may be directly acquired through a network.

(2) And decoding the sound source data to obtain original audio data corresponding to each sound channel. The sound source data can be decoded by adopting the existing arbitrary decoding mode to decode the original audio data corresponding to each sound channel. For example, as shown in fig. 4, 16-bit original audio data ch0:16bit corresponding to the left channel, 16-bit original audio data ch1:16bit corresponding to the right channel, 16-bit original audio data ch2:16bit corresponding to the left surround channel, 16-bit original audio data ch3:16bit corresponding to the right surround channel, 16-bit original audio data ch4:16bit corresponding to the left sky channel, 16-bit original audio data ch5:16bit corresponding to the right channel, 16-bit original audio data ch6:16bit corresponding to the center channel, and 16-bit original audio data ch7:16bit corresponding to the subwoofer channel can be decoded.

(3) The total number of all original audio data is 8, i.e., Q-8, and the total number of channels of all first I2S bus interfaces is 6, i.e., M-6. Then N is 2. With reference to fig. 4, 1 blank original audio data ch8:16bit is added to all original audio data, so that 3 original audio data of 16-bit original audio data ch6:16bit corresponding to a center channel, 16-bit original audio data ch7:16bit corresponding to a subwoofer channel, and blank original audio data ch8:16bit are selected from all original audio data and generated blank original audio data for splitting, and the original audio data ch6:16bit generates split audio data ch6: high 8bit and ch6: low 8 bit; original audio data ch7:16bit is made to generate split audio data ch7: high 8bit and ch7: low 8 bit; making the blank original audio data ch8:16bit generates split audio data ch8: high 8bit, ch8: low 8 bit.

(4) With reference to fig. 4 and 5, original audio data ch0:16bit and split audio data ch6: high 8bit are spliced into target audio data SD1_0, original audio data ch1:16bit and split audio data ch6: low 8bit are spliced into target audio data SD2_0, original audio data ch2:16bit and split audio data ch7: high 8bit are spliced into target audio data SD1_1, original audio data ch3:16bit and split audio data ch7: low 8bit are spliced into target audio data SD2_1, original audio data ch4:16bit and split audio data ch8: high 8bit are spliced into target audio data SD1_2, and original audio data ch5:16bit and split audio data ch8: low 8bit are spliced into target audio data SD2_ 392.

(5) Referring to fig. 4 and 5, since the data bits of a target audio data are changed from 16 bits to 24 bits of the original audio data, the number of sampling bits of the first bit clock BCLK1 can be changed such that the number of sampling bits of the first bit clock BCLK1 is the same as the number of data bits of a target audio data. And, one data bit is transferred at the rising edge within each cycle of the first bit clock BCLK 1.

When WS1 is equal to 0, the first I2S bus interface I2S _0 is controlled to correspond to the channel transfer target audio data SD1_0 of the left channel. Specifically, the target audio data SD1_0 is transferred according to the first bit clock BCLK1 starting at the 2 nd first bit clock BCLK1 after the falling edge of the first frame clock WS1, so that the target audio data SD1_0 is output using the channel corresponding to the left channel of the first I2S bus interface I2S _ 0. When the target audio data SD1_0 is transmitted, the original audio data ch0:16 bits are transmitted in sequence from the highest bit, and then the split audio data ch6: high 16 bits are transmitted in sequence from the highest bit.

When WS1 is equal to 1, the first I2S bus interface I2S _0 is controlled to correspond to the channel transfer target audio data SD2_0 of the right channel. Specifically, the target audio data SD2_0 is transferred according to the first bit clock BCLK1 starting at the 2 nd first bit clock BCLK1 after the rising edge of the first frame clock WS1, so that the target audio data SD2_0 is output using the channel corresponding to the right channel of the first I2S bus interface I2S _ 0. When the target audio data SD2_0 is transmitted, the original audio data ch1:16 bits are transmitted in sequence from the highest bit, and then the split audio data ch6: low 16 bits are transmitted in sequence from the highest bit.

Similarly, when WS1 is equal to 0, the first I2S bus interface I2S _1 is controlled to transmit the target audio data SD1_1 corresponding to the channel of the left channel. When WS1 is equal to 1, the first I2S bus interface I2S _1 is controlled to correspond to the channel transfer target audio data SD2_1 of the right channel.

And when WS1 is equal to 0, the first I2S bus interface I2S _2 is controlled to correspond to the channel transfer target audio data SD1_2 of the left channel. When WS1 is equal to 1, the first I2S bus interface I2S _2 is controlled to correspond to the channel transfer target audio data SD2_2 of the right channel.

(6) As shown in fig. 4 to 6, the timing of controlling the second frame clock WS2 is the same as the timing of the first frame clock WS1, and the timing of the second bit clock BCLK2 is the same as the timing of the first bit clock BCLK 1.

According to the second frame clock WS2 and the second bit clock BCLK2, control is made to receive the target audio data SD1_0 and SD2_0 transferred by the first I2S bus interface I2S _0, control is made to receive the target audio data SD1_1 and SD2_1 transferred by the first I2S bus interface I2S _1, and control is made to receive the target audio data SD1_2 and SD2_2 transferred by the first I2S bus interface I2S _ 2.

And according to the above-mentioned preset encoding rule, respectively intercepting the data of the first 16 bits in the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2 and SD2_2 by using a preset clock signal YCLK, that is, respectively intercepting the original audio data ch0:16 bits, ch1:16 bits, ch2:16 bits, ch3:16 bits, ch4:16 bits, ch5:16 bits, respectively storing the original audio data ch0:16 bits and ch1:16 bits in the channel stack of the corresponding left channel and the channel stack of the corresponding right channel of the first second I2 bus interface S, respectively storing the original audio data ch2:16 bits and ch3:16 bits in the stack of the corresponding left channel and the channel stack of the corresponding right channel of the second I2 bus interface 4684, respectively storing the original audio data ch2:16 bits and the stack of the corresponding left channel in the corresponding right channel stack of the second I2 bus interface S, so as to restore original audio data ch0:16bit, ch1:16bit, ch2:16bit, ch3:16bit, ch4:16bit and ch5:16 bit.

Then, the last 8bit data in the target audio data SD1_0, SD2_0, SD1_1, and SD2_1 are respectively intercepted, the last 8bit data in the target audio data SD2_0 is spliced after the last 8bit data in the target audio data SD1_0, so as to splice and restore the original audio data ch6:16bit, and the restored original audio data ch6:16bit is stored in the channel stack of the corresponding left channel of the fourth second I2S bus interface. The rear 8bit data in the target audio data SD2_1 is spliced after the rear 8bit data in the target audio data SD1_1 so as to splice and restore the original audio data ch7:16bit, and the restored original audio data ch7:16bit is stored in the channel stack of the corresponding right channel of the fourth second I2S bus interface. Thereby restoring original audio data ch6:16bit and ch7:16 bit.

And then, the restored original audio data can be output to a power amplifier in the multi-channel equipment by adopting the second I2S bus interfaces so as to drive a loudspeaker to sound through the power amplifier.

It should be noted that the preset clock signal may be a preset stored clock signal. Also, the period of the preset clock signal may be the same as the period of the bit clock. In practical applications, the frequency of the preset clock signal may be designed according to practical application environments, which is not described herein.

It should be noted that, since the last 8-bit data in the target audio data SD1_2 and SD2_2 is obtained by splitting blank original audio data, which is not carried in the sound source data, the last 8-bit data in the target audio data SD1_2 and SD2_2 can be directly deleted.

It can be seen from the above embodiments that, when the number of the I2S bus interfaces is 3, sound source data with more than 6 channels can be transmitted, so that original audio data corresponding to all channels in a sound source file can be transmitted to a multi-channel device, thereby improving the playing effect of the multi-channel device.

Of course, the received target audio data SD1_0 to SD2_2 may be buffered first, and then intercepted by the preset clock signal YCLK according to the above embodiment. For specific implementation, reference may be made to the above-described embodiments, which are not described in detail herein.

Example II,

The present embodiment is modified with respect to some embodiments in the first embodiment. Only the differences between the present embodiment and the first embodiment will be described below, and the descriptions of the same parts are omitted here.

In a specific implementation, in the embodiment of the present invention, determining target audio data corresponding to each channel of each first I2S bus interface may also include:

then, select from all the original audio data

will be provided with

An original audio data and

and splicing the split audio data into target audio data.

The following describes the audio processing method provided by the present invention with reference to fig. 5 to 8 by taking 16 bits of original audio data and 3 first I2S bus interfaces as examples. The reader should appreciate that the specific process is not so limited. The 3 first I2S bus interfaces are I2S _0, I2S _1, and I2S _2, respectively.

(1) receiving sound source data at least comprising 9 sound channels including a right sound channel, a left surround sound channel, a right surround sound channel, a left sky sound channel, a right sky sound channel, a middle sound channel, a subwoofer sound channel and a ninth sound channel.

(2) The sound source data is decoded to decode 16-bit original audio data ch0:16bit corresponding to the left channel, 16-bit original audio data ch1:16bit corresponding to the right channel, 16-bit original audio data ch2:16bit corresponding to the left surround channel, 16-bit original audio data ch3:16bit corresponding to the right surround channel, 16-bit original audio data ch4:16bit corresponding to the left sky channel, 16-bit original audio data ch5:16bit corresponding to the right channel, 16-bit original audio data ch6:16bit corresponding to the center channel, 16-bit original audio data ch7:16bit corresponding to the subwoofer channel, and 16-bit original audio data ch9:16bit corresponding to the ninth channel.

(3) The total number of all original audio data is 9, i.e., Q ═ 9, and the total number of channels of all first I2S bus interfaces is 6, i.e., M ═ 6. Then N is 2. With reference to fig. 8, 3 pieces of original audio data including 16-bit original audio data ch6:16bit corresponding to a center channel, 16-bit original audio data ch7:16bit corresponding to a subwoofer channel, and original audio data ch9:16bit corresponding to a ninth channel may be directly selected from all the original audio data to split, so that the original audio data ch6:16bit generates split audio data ch6: high 8bit and ch6: low 8 bit; original audio data ch7:16bit is made to generate split audio data ch7: high 8bit and ch7: low 8 bit; let the original audio data ch9:16bit generate split audio data ch9: high 8bit, ch9: low 8 bit.

(4) With reference to fig. 8 and 5, original audio data ch0:16bit and split audio data ch6: high 8bit are spliced into target audio data SD1_0, original audio data ch1:16bit and split audio data ch6: low 8bit are spliced into target audio data SD2_0, original audio data ch2:16bit and split audio data ch7: high 8bit are spliced into target audio data SD1_1, original audio data ch3:16bit and split audio data ch7: low 8bit are spliced into target audio data SD2_1, original audio data ch4:16bit and split audio data ch9: high 8bit are spliced into target audio data SD1_2, and original audio data ch5:16bit and split audio data ch9: low 8bit are spliced into target audio data SD2_ 392.

(5) Referring to fig. 8 and 5, since the data bits of one target audio data are changed from 16 bits to 24 bits of the original audio data, the number of sampling bits of the first bit clock BCLK1 can be changed such that the number of sampling bits of the first bit clock BCLK1 is the same as the number of data bits of one target audio data. And, one data bit is transferred at the rising edge within each cycle of the first bit clock BCLK 1.

(6) As shown in fig. 5 to 8, the timing of controlling the second frame clock WS2 is the same as the timing of the first frame clock WS1, and the timing of the second bit clock BCLK2 is the same as the timing of the first bit clock BCLK 1.

And according to the above-mentioned preset coding rule, respectively intercepting the data of the first 16 bits in the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2 and SD2_2, i.e. respectively intercepting the original audio data ch0:16 bits, ch1:16 bits, ch2:16 bits, ch3:16 bits, ch4:16 bits, ch5:16 bits, respectively storing the original audio data ch0:16 bits and ch1:16 bits in the channel stack of the corresponding left channel and the stack of the corresponding right channel of the first and second I2S bus interfaces, respectively storing the original audio data ch2:16 bits and ch3:16 bits in the stack of the corresponding left channel and the stack of the corresponding right channel of the second I2S bus interface, and storing the original audio data ch2:16 bits and ch 73716 bits in the stack of the corresponding left channel and the corresponding right channel stack of the corresponding right channel of the second I2 bus interface, respectively, so as to restore original audio data ch0:16bit, ch1:16bit, ch2:16bit, ch3:16bit, ch4:16bit and ch5:16 bit.

Then, the last 8bit data in the target audio data SD1_0, SD2_0, SD1_1, and SD2_1 are respectively intercepted, the last 8bit data in the target audio data SD2_0 is spliced after the last 8bit data in the target audio data SD1_0, so as to splice and restore the original audio data ch6:16bit, and the restored original audio data ch6:16bit is stored in the channel stack of the corresponding left channel of the fourth second I2S bus interface. The rear 8bit data in the target audio data SD2_1 is spliced after the rear 8bit data in the target audio data SD1_1 so as to splice and restore the original audio data ch7:16bit, and the restored original audio data ch7:16bit is stored in the channel stack of the corresponding right channel of the fourth second I2S bus interface. And splicing the rear 8bit data in the target audio data SD2_2 after the rear 8bit data in the target audio data SD1_2 so as to splice and restore the original audio data ch8:16bit, and storing the restored original audio data ch8:16bit in a channel stack of a corresponding left channel of a fifth second I2S bus interface. Thereby restoring original audio data ch6:16bit, ch7:16bit and ch8:16 bit.

Example III,

when in use, will

Combining the original audio data into a target audio data; where N is a positive even number and M represents the total number of channels of all the first I2S bus interfaces.

Illustratively, when the number of the first I2S bus interfaces is 2, and the total number of channels of all the first I2S bus interfaces is 4, then when the number of all the original audio data is 8, it may be determined that each target audio data includes 2 original audio data, that is, N — 4.

Illustratively, when the number of the first I2S bus interfaces is 3, and the total number of channels of all the first I2S bus interfaces is 6, then when the number of all the original audio data is 12, it may be determined that each target audio data includes 2 original audio data, that is, N — 4.

Of course, in practical applications, the number of the first I2S bus interfaces and the number of all the original audio data may be determined according to practical application environments, and is not limited herein.

In specific implementation, in the embodiment of the present invention, when N is 4, two original audio data in the same target audio data may be set as original audio data corresponding to the same type of channel. Illustratively, at least one of the channels includes: the sound channel comprises a left sound channel, a right sound channel, a left surrounding sound channel, a right surrounding sound channel, a left sky sound channel, a right sky sound channel, a middle sound channel and a subwoofer sound channel. The left channel and the right channel may be the same type of main channel, the left surround channel and the right surround channel may be the same type of surround channel, the left sky channel and the right sky channel may be the same type of sky channel, and the center channel and the subwoofer channel may be the same type of enhancement channel. For the same reason, the description is omitted here.

The following describes the audio processing method provided by the present invention with reference to fig. 9 to fig. 12 by taking 16 bits of original audio data and 3 first I2S bus interfaces as examples. The reader should appreciate that the specific process is not so limited. The 3 first I2S bus interfaces are I2S _0, I2S _1, and I2S _2, respectively. Fig. 10 is only an example of the transmission process of the target audio data SD1_0 and the target audio data SD2_ 0.

(1) sound source data having 12 channels is received. For example, the channels include at least: the sound channel comprises a left sound channel, a right sound channel, a left surrounding sound channel, a right surrounding sound channel, a left sky sound channel, a right sky sound channel, a middle sound channel and a subwoofer sound channel. The remaining channels may be designed according to the actual application environment, and are not limited herein.

(2) As shown in fig. 9, the sound source data is decoded by using an existing arbitrary decoding method to decode the original audio data corresponding to the 12 channels: ch0:16bit, ch1:16bit, ch2:16bit, ch3:16bit, ch4:16bit, ch5:16bit, ch6:16bit, ch7:16bit, ch8:16bit, ch9:16bit, ch10:16bit and ch11:16 bit. The channel 0:16bit and the channel 1:16bit can be used as original audio data corresponding to the same type of channel, the channel 2:16bit and the channel 3:16bit can be used as original audio data corresponding to the same type of channel, the channel 4:16bit and the channel 5:16bit can be used as original audio data corresponding to the same type of channel, the channel 6:16bit and the channel 7:16bit can be used as original audio data corresponding to the same type of channel, the channel 8:16bit and the channel 9:16bit can be used as original audio data corresponding to the same type of channel, and the channel 10:16bit and the channel 11:16bit can be used as original audio data corresponding to the same type of channel.

(3) Since the number of the first I2S bus interfaces is 3, the total number of channels of all the first I2S bus interfaces is 6, i.e., M is 6. The number of all original audio data is 12, i.e., Q is 12. N may be made 4 so that two original audio data are combined into one target audio data. For example, ch0:16bit and ch1:16bit are made as one target audio data SD1_0, ch2:16bit and ch3:16bit are made as one target audio data SD2_0, ch4:16bit and ch5:16bit are made as one target audio data SD1_1, ch6:16bit and ch7:16bit are made as one target audio data SD2_1, ch8:16bit and ch9:16bit are made as one target audio data SD1_2, and ch10:16bit and ch11:16bit are made as one target audio data SD2_ 2.

(4) Referring to fig. 9 and 10, since the data bits of a target audio data are changed from 16 bits to 32 bits of the original audio data, the number of sampling bits of the first bit clock BCLK1 can be changed without changing the sampling frequency of the first bit clock BCLK1, so that the number of sampling bits of the first bit clock BCLK1 is the same as the data bits of a target audio data. And, one data bit is transferred at the rising edge within each cycle of the first bit clock BCLK 1.

When WS1 is equal to 0, the first I2S bus interface I2S _0 is controlled to correspond to the channel transfer target audio data SD1_0 of the left channel. Specifically, the target audio data SD1_0 is transferred according to the first bit clock BCLK1 starting at the 2 nd first bit clock BCLK1 after the falling edge of the first frame clock WS1, so that the target audio data SD1_0 is output using the channel corresponding to the left channel of the first I2S bus interface I2S _ 0. When the target audio data SD1_0 is transmitted, the original audio data ch0:16 bits are transmitted in sequence from the most significant bit, and then the original audio data ch1:16 bits are transmitted in sequence from the most significant bit.

When WS1 is equal to 1, the first I2S bus interface I2S _0 is controlled to correspond to the channel transfer target audio data SD2_0 of the right channel. Specifically, the target audio data SD2_0 is transferred according to the first bit clock BCLK1 starting at the 2 nd first bit clock BCLK1 after the falling edge of the first frame clock WS1, so that the target audio data SD2_0 is output using the channel corresponding to the right channel of the first I2S bus interface I2S _ 0. When the target audio data SD2_0 is transmitted, the original audio data ch2:16 bits are transmitted in sequence from the most significant bit, and then the original audio data ch3:16 bits are transmitted in sequence from the most significant bit.

(5) As shown in fig. 9 to 12, the first I2S bus interface I2S _0 corresponds to the second frame clock WS2_0 and the second bit clock BCLK2_0, the first I2S bus interface I2S _1 corresponds to the second frame clock WS2_1 and the second bit clock BCLK2_1, and the first I2S bus interface I2S _2 corresponds to the second frame clock WS2_2 and the second bit clock BCLK2_ 2. The timings of the second frame clocks WS2_0 to WS2_2 are controlled to be the same as the timing of the first frame clock WS1, and the timings of the second bit clocks BCLK2_0 to BCLK2_2 are controlled to be the same as the timing of the first bit clock BCLK 1.

The reception of the target audio data SD1_0 and SD2_0 transferred by the first I2S bus interface I2S _0 is controlled according to the second frame clock WS2_0 and the second bit clock BCLK2_ 0. The reception of the target audio data SD1_1 and SD2_1 transferred by the first I2S bus interface I2S _1 is controlled according to the second frame clock WS2_1 and the second bit clock BCLK2_ 1. The reception of the target audio data SD1_2 and SD2_2 transferred by the first I2S bus interface I2S _2 is controlled according to the second frame clock WS2_2 and the second bit clock BCLK2_ 2.

And according to the above-mentioned preset encoding rule, respectively intercepting the data of the first 16 bits in the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2 and SD2_2 by using a preset clock signal YCLK, that is, respectively intercepting the original audio data ch0:16 bits, ch2:16 bits, ch4:16 bits, ch6:16 bits, ch8:16 bits, and ch10:16 bits, and storing the original audio data ch0:16 bits in the channel stack of the corresponding left channel of the first second I2S bus interface, storing the original audio data ch2:16 bits in the channel stack of the corresponding left channel of the second I2 bus interface S, storing the original audio data ch6:16 bits in the channel stack of the corresponding left channel of the third second I2S bus interface, storing the original audio data ch6:16 bits in the channel stack of the corresponding left channel of the second I2 bus interface 6, original audio data ch8:16 bits are stored in the channel stack of the corresponding left channel of the fifth second I2S bus interface, and original audio data ch10:16 bits are stored in the channel stack of the corresponding left channel of the sixth second I2S bus interface. So as to restore original audio data ch0:16bit, ch2:16bit, ch4:16bit, ch6:16bit, ch8:16bit and ch10:16 bit.

Then, a preset clock signal YCLK is adopted to respectively intercept the data of the last 16 bits in the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2 and SD2_2, namely respectively intercept the original audio data ch1:16 bits, ch3:16 bits, ch5:16 bits, ch7:16 bits, 737ch 6:16 bits and ch11:16 bits, and store the original audio data ch1:16 bits in the channel stack of the corresponding right channel of the first and second I2S bus interface, store the original audio data 3:16 bits in the channel stack of the corresponding right channel of the second I2S bus interface, store the original audio data ch5:16 bits in the channel stack of the corresponding right channel of the third and second I2S bus interface, store the original audio data ch7:16 bits in the channel stack of the corresponding right channel of the second I2 bus interface, store the original audio data ch5:16 bits in the stack of the corresponding right channel stack of the second I2 bus interface, store the corresponding right channel stack of the fifth and the original audio data channel stack of the second I2 bus interface 9, and storing the original audio data ch11:16bit in the channel stack of the corresponding left channel of the sixth second I2S bus interface. So as to restore original audio data ch1:16bit, ch3:16bit, ch5:16bit, ch7:16bit, ch9:16bit and ch11:16 bit.

And then, the restored original audio data ch0:16 bit-ch 11:16bit can be output to a power amplifier in the multi-channel equipment by adopting the second I2S bus interfaces, so that a loudspeaker is driven to sound through the power amplifier.

It should be noted that, when there are 2I 2S bus interfaces, the process of transmitting sound source data may refer to the foregoing embodiments, which are not described herein again.

Example four,

This embodiment is modified with respect to some embodiments in the third embodiment. Only the differences between the present embodiment and the third embodiment will be described below, and the same parts will not be described herein.

The audio processing method provided by the embodiment of the invention, besides the steps (1) to (3), can also comprise the following steps:

(4) referring to fig. 9 and fig. 13a to 13c, since the data bits of a target audio data are changed from 16 bits to 32 bits of the original audio data, the sampling frequency of the first bit clock BCLK1 can be changed without changing the number of sampling bits of the first bit clock BCLK1, so that the number of sampling bits of the first bit clock BCLK1 is the same as the data bits of a target audio data. Wherein one data bit is transmitted on each rising and falling edge within each cycle of the first bit clock BCLK 1.

(5) Referring to fig. 9 and fig. 14a to 15, the first I2S bus interface I2S _0 corresponds to the second frame clock WS2_0 and the second bit clock BCLK2_0, the first I2S bus interface I2S _1 corresponds to the second frame clock WS2_1 and the second bit clock BCLK2_1, and the first I2S bus interface I2S _2 corresponds to the second frame clock WS2_2 and the second bit clock BCLK2_ 2. The timings of the second frame clocks WS2_0 to WS2_2 are controlled to be the same as the timing of the first frame clock WS1, and the timings of the second bit clocks BCLK2_0 to BCLK2_2 are controlled to be the same as the timing of the first bit clock BCLK 1.

It should be noted that. The timing of the preset clock signal YCLK may be the same as the timing of the second bit clock.

Example V,

in time, and is added to all the original audio data

The same amount of blank original audio data, and in all original audioSelecting data and generated blank original audio data

will be provided with

An original audio data and

the split audio data are combined into one target audio data.

In a specific implementation, in an embodiment of the present invention, selecting the original audio data to be split may include: blank original audio data. When the split data is affected in the transmission process, the original audio data can not be decoded subsequently, but the play effect of the multi-channel equipment is not affected.

In the following, taking 2 first I2S bus interfaces as an example, M is 4. The audio processing method provided by the embodiment of the invention can comprise the following steps:

(1) sound source data having a left channel, a right channel, a left surround channel, a right surround channel, a left sky channel, a right sky channel, a center channel, and a subwoofer channel is received.

(2) With reference to fig. 16, the sound source data is decoded by using an existing arbitrary decoding method to decode 16-bit original audio data ch0:16bit corresponding to the left channel, 16-bit original audio data ch1:16bit corresponding to the right channel, 16-bit original audio data ch2:16bit corresponding to the left surround channel, 16-bit original audio data ch3:16bit corresponding to the right surround channel, 16-bit original audio data ch4:16bit corresponding to the left sky channel, 16-bit original audio data ch5:16bit corresponding to the right sky channel, 16-bit original audio data ch6:16bit corresponding to the center channel, and 16-bit original audio data 7:16bit corresponding to the subwoofer channel.

(3) The total number of all original audio data is 8, i.e., Q-8, and the total number of channels of all first I2S bus interfaces is 4, i.e., M-4. Then N is 4. With reference to fig. 16, 4 blank original audio data ch01:16bit, ch02:16bit, ch03:16bit and ch04:16bit are added to all the original audio data, so that 4 original audio data of the blank original audio data ch01:16bit, ch02:16bit, ch03:16bit and ch04:16bit can be selected from all the original audio data and the generated blank original audio data for splitting, and the blank original audio data ch01:16bit generates split audio data ch01: high 8bit and ch01: low 8 bit; blank original audio data ch02:16bit is made to generate split audio data ch02: high 8bit and ch02: low 8 bit; making the blank original audio data ch03:16bit generates split audio data ch03: high 8bit, ch03: low 8bit, and making the blank original audio data ch04:16bit generates split audio data ch04: high 8bit, ch04: low 8 bit.

(4) With reference to fig. 16 and 17, original audio data ch0:16bit, ch1:16bit and split audio data ch01: high 8bit, ch01: low 8bit are spliced into target audio data SD1_0, original audio data ch2:16bit, ch3:16bit and split audio data ch02: high 8bit, ch02: low 8bit are spliced into target audio data SD2_0, original audio data ch4:16bit, ch5:16bit and split audio data ch03: high 8bit, and ch03: low 8bit are spliced into target audio data SD1_1, and original audio data ch6:16bit, ch7:16bit and split audio data ch04: high 8bit, and ch04: low 8bit are spliced into target audio data SD2_ 5391. Taking the target audio data SD1_0 as an example, the ch01: high 8bit may be spliced after the lowest bit of the ch0:16bit, the highest bit of the ch1:16bit may be spliced after the lowest bit of the ch01: high 8bit, and the lowest bit of the ch01: low 8bit may be spliced after the lowest bit of the ch1:16 bit. The same goes for the other reasons, and so on, and is not limited herein.

(5) Referring to fig. 16 and 17, the data bits of the target audio data are changed from 16 bits to 48 bits of the original audio data, so that the sampling bit number and the sampling frequency of the first bit clock BCLK1 can be changed, and the target audio data can be transmitted according to the first bit clock BCLK 1. Also, one data bit is transferred at the rising edge and the falling edge in each cycle of the first bit clock BCLK 1.

When WS1 is equal to 0, the first I2S bus interface I2S _0 is controlled to correspond to the channel transfer target audio data SD1_0 of the left channel. Specifically, the target audio data SD1_0 is transferred according to the first bit clock BCLK1 starting at the 2 nd first bit clock BCLK1 after the falling edge of the first frame clock WS1, so that the target audio data SD1_0 is output using the channel corresponding to the left channel of the first I2S bus interface I2S _ 0. When the target audio data SD1_0 is transmitted, the original audio data ch0:16bit is transmitted in sequence from the highest bit, then the split audio data ch01: high 16bit is transmitted in sequence from the highest bit, then the original audio data ch1:16bit is transmitted in sequence from the highest bit, and then the split audio data ch01: low 16bit is transmitted in sequence from the highest bit.

When WS1 is equal to 1, the first I2S bus interface I2S _0 is controlled to correspond to the channel transfer target audio data SD2_0 of the right channel. Specifically, the target audio data SD2_0 is transferred according to the first bit clock BCLK1 starting at the 2 nd first bit clock BCLK1 after the rising edge of the first frame clock WS1, so that the target audio data SD2_0 is output using the channel corresponding to the right channel of the first I2S bus interface I2S _ 0. When the target audio data SD2_0 is transmitted, the original audio data ch2:16bit is transmitted in sequence from the highest bit, then the split audio data ch02: high 16bit is transmitted in sequence from the highest bit, then the original audio data ch3:16bit is transmitted in sequence from the highest bit, and then the split audio data ch02: low 16bit is transmitted in sequence from the highest bit.

(6) As shown in fig. 16 to 19, the timing of controlling the second frame clock WS2 is the same as the timing of the first frame clock WS1, and the timing of the second bit clock BCLK2 is the same as the timing of the first bit clock BCLK 1.

According to the preset coding rule, a preset clock signal YCLK is adopted to respectively intercept the first 16bit data of the target audio data SD1_0, SD2_0, SD1_1 and SD2_1, namely the original audio data ch0:16bit, ch2:16bit, ch4:16bit and ch6:16bit are respectively intercepted, the original audio data ch0:16bit is stored in the channel stack of the corresponding left channel of the first and second I2S bus interface, the original audio data ch2:16bit is stored in the channel stack of the corresponding left channel of the second and second I2S bus interface, the original audio data ch4:16bit is stored in the channel stack of the corresponding left channel of the third and second I2S bus interface, and the original audio data ch6:16bit is stored in the channel stack of the corresponding left channel of the fourth and second I2S bus interface. Thereby original audio data ch0:16bit, ch2:16bit, ch4:16bit and ch6:16bit are restored.

Then, the preset clock signal YCLK is used to respectively intercept the later 8-bit data of the target audio data SD1_0, SD2_0, SD1_1 and SD2_1, namely the data are respectively intercepted by ch01: high 8bit, ch02: high 8bit, ch04: high 8bit and ch06: high 8bit, and the data can be directly deleted.

Then, a preset clock signal YCLK is used to respectively intercept the later 16-bit data in the target audio data SD1_0, SD2_0, SD1_1 and SD2_1, that is, the original audio data ch1:16bit, ch3:16bit, ch5:16bit and ch7:16bit, and the original audio data ch1:16bit is stored in the channel stack of the right channel corresponding to the first and second I2S bus interfaces, the original audio data ch3:16bit is stored in the channel stack of the right channel corresponding to the second I2S bus interface, the original audio data ch5:16bit is stored in the channel stack of the right channel corresponding to the third and second I2S bus interfaces, and the original audio data ch7:16bit is stored in the channel stack of the right channel corresponding to the fourth and second I2S bus interface. Thereby original audio data ch1:16bit, ch3:16bit, ch5:16bit and ch7:16bit are restored.

The data in the deleted SD1_0, SD2_0, SD1_1, SD2_1 may then be deleted directly.

Based on the same inventive concept, an embodiment of the present invention further provides an audio processing apparatus, as shown in fig. 20, including:

at least 2 first I2S bus interfaces 110;

a receiving circuit 120 for receiving sound source data having a plurality of channels;

a primary decoding circuit 130, configured to decode the sound source data into original audio data corresponding to each channel;

the recoding circuit 140 is electrically connected with the at least 2 first I2S bus interfaces, and is used for recoding the original audio data according to a preset coding rule and outputting the recoded data through the at least 2 first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all first I2S bus interfaces.

In specific implementation, in the embodiment of the present invention, as shown in fig. 20, the audio processing apparatus may further include: a re-decode circuit 150 electrically connected to at least 2 first I2S bus interfaces 150. The re-decoding circuit 150 is configured to receive target audio data transmitted by each first I2S bus interface according to a second frame clock and a second bit clock, and re-decode the received data according to a preset coding rule to obtain each original audio data; the time sequence of the second frame clock is the same as that of the first frame clock, and the time sequence of the second bit clock is the same as that of the first bit clock.

In particular, in the embodiment of the present invention, as shown in fig. 20, the re-decoding circuit 150 transmits the re-decoded original audio data to the multi-channel device 160 through a plurality of second I2S bus interfaces 170. That is, the re-decoding circuit 150 may be electrically connected to the multi-channel device 160 through a plurality of second I2S bus interfaces 170.

The working principle and the specific implementation of the audio processing apparatus are the same as those of the audio processing method in the above embodiment, and therefore, the working method of the audio processing apparatus can be implemented by referring to the specific implementation of the audio processing method in the above embodiment, and is not described herein again.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, where the display device includes a circuit board, and the circuit board is provided with:

at least 2 first I2S bus interfaces;

the initial decoding circuit is used for decoding the sound source data into original audio data corresponding to each sound channel;

the recoding circuit is electrically connected with the at least 2 first I2S bus interfaces and is used for recoding the original audio data according to a preset coding rule and outputting the recoded data through the at least 2 first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all first I2S bus interfaces.

In specific implementation, in the embodiment of the present invention, the display device may further include: a re-decode circuit electrically connected to at least 2 first I2S bus interfaces. The re-decoding circuit is used for receiving the target audio data transmitted by each first I2S bus interface according to a second frame clock and a second bit clock, and re-decoding the received data according to a preset coding rule to obtain each original audio data; wherein, the time sequence of the second frame clock is the same as that of the first frame clock, and the time sequence of the second bit clock is the same as that of the first bit clock

In practical implementation, in the embodiment of the present invention, the re-decoding circuit transmits the re-decoded original audio data to the multi-channel device through a plurality of second I2S bus interfaces. That is, the re-decoding circuit may be electrically connected to the multi-channel device through a plurality of second I2S bus interfaces.

The working principle and the specific implementation of the display device are the same as those of the audio processing method in the above embodiment, and therefore, the working method of the audio processing device can be implemented by referring to the specific implementation of the audio processing method in the above embodiment, and is not described herein again.

In particular implementations, the various circuits described above may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects within an embodiment of the invention. Illustratively, the initial decoding circuit may be a decoder capable of performing its function. The re-encoding circuit may be an encoder capable of performing its function. The re-decoding circuit may be a decoder or an XMOS chip capable of implementing its function. Further, the first I2S bus interface, the receiving circuit, the initial decoding circuit, and the re-encoding circuit may form a master chip.

Based on the same inventive concept, the embodiment of the invention also provides a multi-channel system, which comprises multi-channel equipment and the audio processing device provided by the embodiment of the invention. The principle of the multi-channel system to solve the problem is similar to the aforementioned audio processing apparatus, so the implementation of the multi-channel system can be referred to the implementation of the aforementioned audio processing apparatus, and the repeated parts are not described herein again.

In practical implementation, in the embodiment of the present invention, the multi-channel device may be any product or component having a display function, such as a television, a notebook computer, and the like, which is not limited herein.

Based on the same inventive concept, embodiments of the present invention also provide a computer-readable storage medium, on which a computer program is stored, and the program, when executed by a processor, implements the steps of any one of the audio processing methods provided by the embodiments of the present invention. In particular, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, and the like) having computer-usable program code embodied therein.

Based on the same inventive concept, an embodiment of the present invention further provides a computer device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and when the processor executes the computer program, the processor implements any of the steps of the audio processing method provided by the embodiment of the present invention.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A display device comprises a circuit board, wherein at least 2 first I2S bus interfaces are arranged on the circuit board;

the recoding circuit is electrically connected with the at least 2 first I2S bus interfaces and is used for recoding the original audio data according to a preset coding rule and outputting the recoded original audio data through the at least 2 first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all of the first I2S bus interfaces;

a re-decode circuit electrically connected to the at least 2 first I2S bus interfaces;

the re-decoding circuit is used for receiving the target audio data transmitted by each first I2S bus interface according to a second frame clock and a second bit clock, and re-decoding the received data according to the preset coding rule to obtain each original audio data; the time sequence of the second frame clock is the same as that of the first frame clock, and the time sequence of the second bit clock is the same as that of the first bit clock;

wherein, after re-encoding the original audio data according to a preset encoding rule, outputting the re-encoded original audio data through at least 2 first I2S bus interfaces, including:

outputting the obtained target audio data through a channel of a corresponding first I2S bus interface;

the determining target audio data corresponding to each channel of each first I2S bus interface comprises:

and is

Then, and is added to all the original audio data

Splitting original audio data to generate split audio data; wherein N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces, and the data bits of the blank original audio data are the same as the data bits of the original audio data;

will be provided with

An original audio data and

each split audio data is combined into one target audio data.

2. The display apparatus as claimed in claim 1, wherein said determining target audio data corresponding to each channel of each of said first I2S bus interfaces comprises:

then, selecting from all the original audio data

will be provided with

An original audio data and

and splicing the split audio data into the target audio data.

3. The display device according to claim 2, wherein the split audio data of the two target audio data corresponding to the same first I2S bus interface belongs to the same original audio data.

4. The display device of claim 2, wherein the plurality of channels comprises: the sound system comprises a left sound channel, a right sound channel, a left surrounding sound channel, a right surrounding sound channel, a left sky sound channel, a right sky sound channel, a middle sound channel and a subwoofer sound channel;

5. The display device according to any one of claims 1 to 4, wherein the outputting of the obtained target audio data through the channel of the corresponding first I2S bus interface includes:

6. The display apparatus according to claim 5, further comprising, after the re-encoding the original audio data according to a preset encoding rule and outputting the re-encoded original audio data through at least 2 first I2S bus interfaces:

7. The display device according to claim 6, wherein the receiving the target audio data transmitted by each of the first I2S bus interfaces according to the second frame clock and the second bit clock comprises: