WO2021004046A1

WO2021004046A1 - Audio processing method and apparatus, and display device

Info

Publication number: WO2021004046A1
Application number: PCT/CN2020/070890
Authority: WO
Inventors: 李见; 黄飞
Original assignee: 海信视像科技股份有限公司
Priority date: 2019-07-09
Filing date: 2020-01-08
Publication date: 2021-01-14
Also published as: WO2021004048A1; WO2021004045A1; WO2021004049A1; WO2021004047A1

Abstract

Disclosed in the present application are an audio processing method and apparatus, and a display device; sound source data is decoded into original audio data corresponding to each audio channel, and as the total number of audio channels is greater than the total number of channels of all of the first I2S bus interfaces, after the original audio data is re-encoded according to a preset encoding rule, the original audio data of all of the audio channels can be outputted by means of at least two first I2S bus interfaces.

Description

Audio processing method and device, and display equipment

This patent application requires the application number of 201910614701.7 filed on July 9, 2019; the application number of 201910613160.6 filed on July 9, 2019; the application number of 201910613254.3 filed on July 9, 2019; The application number submitted on July 9, 2019 is 201910615836.5; the application number submitted on July 9, 2019 is 201910616404.6; the application number submitted on August 2, 2019 is 201910710346.3; on July 9, 2019 The priority of the Chinese patent application filed on July 22, 2019 with application number 2019106185413; application number 201910659488.1 filed on July 22, 2019, the full text of which is incorporated herein by reference.

Technical field

This application relates to the field of display technology, in particular to audio processing methods and devices, and display equipment.

Background technique

In order to better achieve the fullness of sound effects, multi-channel recording of sound source files is usually used. However, when transmitting and playing a sound source file with multiple channels, due to the limitation of the transmission conditions, it is impossible to transmit all the channels in the sound source file to the power amplifier during transmission, which makes it impossible to realize multiple channels during playback. The output of the sound channel, which in turn leads to problems such as poor playback.

Application content

The audio processing method and device and the display device provided by the embodiments of the present application are used to improve the playback effect.

The embodiment of the application provides an audio processing method, including:

Receive sound source data with multiple channels;

Decoding the sound source data to obtain original audio data corresponding to each of the channels;

After re-encoding the original audio data according to a preset encoding rule, it is output through at least two first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all the first I2S bus interfaces.

In some embodiments, in the embodiments of the present application, after the original audio data is re-encoded according to a preset encoding rule, and then output through at least two first I2S bus interfaces, it includes:

Determine each channel of each first I2S bus interface according to all the original audio data, the total number of channels of all the first I2S bus interfaces, and the communication rules of each channel of the first I2S bus interface Corresponding target audio data; wherein the data bits of the target audio data are greater than the data bits of the original audio data;

The obtained target audio data is output through the corresponding channel of the first I2S bus interface.

In some embodiments, in the embodiments of the present application, the determining the target audio data corresponding to each channel of each of the first I2S bus interface includes:

When determining that the quantity Q of all the original audio data satisfies the formula:, combine the original audio data into one target audio data; where N is a positive even number, and M represents the total number of channels of all the first I2S bus interfaces ;or,

When it is determined that the quantity Q of all the original audio data satisfies the formula:, add the same amount of blank original audio data to all the original audio data, and add the same amount of blank original audio data to all the original audio data and the generated blank original audio Select one piece of original audio data from the data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interface, and the data bits of the blank original audio data are the same as those of the The data bits of the original audio data are the same;

Combine pieces of original audio data and pieces of split audio data into one target audio data.

In some embodiments, in the embodiments of the present application, the original audio data selected for splitting includes: blank original audio data.

When it is determined that the quantity Q of all the original audio data satisfies the formula: and, the same number of blank original audio data is added to all the original audio data, and all the original audio data and the generated blank Select one piece of original audio data from the original audio data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interface, and the data bits of the blank original audio data are The data bits of the original audio data are the same;

When it is determined that the quantity Q of all the original audio data satisfies the formula:, select one original audio data from all the original audio data for splitting to generate split audio data; where N is a positive even number, and M represents all The total number of channels of the first I2S bus interface;

Splicing pieces of original audio data and pieces of split audio data into one target audio data.

In some embodiments, in the embodiments of the present application, the original audio data is a digital signal with K data bits, and one of the split audio data is a digital signal with adjacent data bits; where K Is a positive integer.

In some embodiments, in the embodiments of the present application, the split audio data in the two target audio data corresponding to the same first I2S bus interface belong to the same original audio data.

In some embodiments, in the embodiments of the present application, the multiple channels include: left channel, right channel, left surround channel, right surround channel, left sky channel, right sky channel, middle channel Set channel, subwoofer channel;

The original audio data selected for splitting includes: original audio data corresponding to the center channel and original audio data corresponding to the subwoofer channel.

In some embodiments, in the embodiments of the present application, outputting the obtained target audio data through the corresponding channel of the first I2S bus interface includes:

Change the number of sampling bits of the first bit clock and/or change the sampling frequency of the first bit clock, starting from the second pulse of the first bit clock after the edge change of the first frame clock, according to the first bit clock The clock transmits data bits of a single channel, so that each of the first I2S bus interfaces transmits target audio data of two channels in one cycle of the first frame clock.

In some embodiments, in the embodiments of the present application, two data bits are transmitted in one cycle of the first bit clock; or, one data bit is transmitted in one cycle of the first bit clock.

In some embodiments, in the embodiments of the present application, the sampling bit number of the first bit clock is the same as the data bit of the target audio data.

In some embodiments, in the embodiments of the present application, after the original audio data is re-encoded according to a preset encoding rule and then output through at least two first I2S bus interfaces, the method further includes:

Receiving the target audio data transmitted by each of the first I2S bus interfaces according to the second frame clock and the second bit clock, and re-decoding the received data according to the preset encoding rule to obtain each of the original audio data; wherein , The timing of the second frame clock is the same as the timing of the first frame clock, and the timing of the second bit clock is the same as the timing of the first bit clock.

In some embodiments, in the embodiments of the present application, the receiving target audio data transmitted by each of the first I2S bus interfaces according to the second frame clock and the second bit clock includes:

Receiving the target audio data transmitted by each of the first I2S bus interfaces according to the second frame clock and the second bit clock; or,

Receive the target audio data transmitted by each of the first I2S bus interfaces according to multiple second frame clocks and multiple second bit clocks; wherein, one first I2S bus interface corresponds to one second frame clock and one first Two-bit clock.

An embodiment of the present application also provides an audio processing device, including:

At least 2 first I2S bus interfaces;

A receiving circuit for receiving sound source data with multiple channels;

A preliminary decoding circuit, which is used to decode the sound source data to obtain original audio data corresponding to each of the channels;

The re-encoding circuit is electrically connected to the at least two first I2S bus interfaces, and is configured to re-encode the original audio data according to a preset encoding rule, and output it through at least two first I2S bus interfaces; The total number of channels is greater than the total number of channels of all the first I2S bus interfaces.

In some embodiments, in the embodiments of the present application, it further includes: a re-decoding circuit electrically connected to the at least two first I2S bus interfaces;

The re-decoding circuit is used to receive the target audio data transmitted by each of the first I2S bus interfaces according to the second frame clock and the second bit clock, and to re-decode the received data according to the preset encoding rule to obtain each The original audio data; wherein the timing of the second frame clock is the same as the timing of the first frame clock, and the timing of the second bit clock is the same as the timing of the first bit clock.

An embodiment of the present application also provides a multi-channel system, including: a multi-channel device and the above audio processing device.

An embodiment of the present application also provides a display device, including a display screen, configured to present image data;

The speaker is configured to reproduce sound data;

An audio processor, configured to receive sound source data having multiple channels, and decode the sound source data to obtain original audio data corresponding to each of the channels;

A controller, configured to re-encode the original audio data according to a preset encoding rule, and output to the speaker through at least two first I2S bus interfaces;

Wherein, the total number of channels is greater than the total number of channels of all the first I2S bus interfaces.

The beneficial effects of this application are as follows:

The audio processing method and device and the display device provided by the embodiments of the application decode the sound source data to obtain the original audio data corresponding to each channel. Since the total number of channels is greater than the total number of channels of all the first I2S bus interfaces, After the original audio data is re-encoded by the preset encoding rule, the original audio data of all channels can be output through at least two first I2S bus interfaces. In this way, the original audio data corresponding to all channels in the sound source file can be transmitted to the multi-channel device, thereby improving the playback effect of the multi-channel device.

Description of the drawings

FIG. 1 is a signal timing diagram of an I2S bus interface provided by an embodiment of the application;

2 is a flowchart of an audio processing method provided by an embodiment of the application;

FIG. 3 is a schematic structural diagram of a multi-channel device provided by an embodiment of the application;

FIG. 4 is one of the schematic diagrams of original audio data provided by an embodiment of this application;

FIG. 5 is one of the timing diagrams when the first I2S bus interface provides data output according to an embodiment of the application;

FIG. 6 is one of the timing diagrams when receiving data output by the first I2S bus interface according to an embodiment of the application;

FIG. 7 is one of the schematic diagrams of time sequence when intercepting data in target audio data provided by an embodiment of the application;

FIG. 8 is the second schematic diagram of original audio data provided by an embodiment of this application;

FIG. 9 is the third schematic diagram of original audio data provided by an embodiment of this application;

FIG. 10 is the second schematic diagram of the time sequence when the first I2S bus interface provides data output according to an embodiment of the application;

FIG. 11a is the second schematic diagram of the time sequence when receiving data output by the first I2S bus interface according to an embodiment of the application; FIG.

FIG. 11b is the third schematic diagram of the time sequence when receiving data output by the first I2S bus interface according to an embodiment of the application;

FIG. 11c is a fourth schematic diagram of a timing sequence when receiving data output by the first I2S bus interface according to an embodiment of the application; FIG.

FIG. 12 is a second schematic diagram of a time sequence when data in target audio data is intercepted according to an embodiment of the application;

FIG. 13a is the third schematic diagram of the time sequence when the first I2S bus interface provides data output according to an embodiment of the application;

FIG. 13b is a fourth schematic diagram of a timing sequence when the first I2S bus interface provides data output according to an embodiment of the application;

FIG. 13c is the fifth schematic diagram of the time sequence when the first I2S bus interface provides data output according to an embodiment of the application;

FIG. 14a is the fifth schematic diagram of the time sequence when receiving data output by the first I2S bus interface according to an embodiment of the application;

FIG. 14b is a sixth schematic diagram of the timing sequence when receiving data output by the first I2S bus interface according to an embodiment of the application;

FIG. 14c is the seventh schematic diagram of the time sequence when receiving data output by the first I2S bus interface according to an embodiment of the application; FIG.

15 is the third schematic diagram of the time sequence when intercepting data in target audio data provided by an embodiment of the application;

16 is the fourth schematic diagram of original audio data provided by an embodiment of this application;

FIG. 17 is a sixth schematic diagram of a time sequence when the first I2S bus interface provides data output according to an embodiment of the application;

FIG. 18 is the eighth schematic diagram of the time sequence when receiving data output by the first I2S bus interface provided by an embodiment of the application; FIG.

FIG. 19 is a fourth schematic diagram of a time sequence when data in target audio data is intercepted according to an embodiment of the application;

FIG. 20 is a schematic structural diagram of an audio processing device provided by an embodiment of the application;

FIG. 21 is a schematic diagram of a display device provided in Embodiment 1 of the present application;

FIG. 22 is a block diagram of the hardware configuration of the display device provided in Embodiment 1 of the present application.

Detailed ways

In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. And if there is no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the application, all other embodiments obtained by a person of ordinary skill in the art without creative labor are within the protection scope of the application.

Unless otherwise defined, the technical or scientific terms used in this application shall have the usual meanings understood by those with ordinary skills in the field to which this application belongs. The "first", "second" and similar words used in this application do not denote any order, quantity or importance, but are only used to distinguish different components. "Include" or "include" and other similar words mean that the element or item appearing before the word encompasses the element or item listed after the word and its equivalents, but does not exclude other elements or items. Similar words such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the size and shape of each figure in the drawings do not reflect the true proportions, and the purpose is only to illustrate the content of this application. And the same or similar reference numerals indicate the same or similar elements or elements with the same or similar functions.

With the rapid development of display technology, liquid crystal display devices (Liquid Crystal Display, LCD), organic light emitting diode (Organic Light Emitting Diode, OLED) display devices, etc. have been applied to people's lives. These display devices can receive video data and sound source data, and process these data to display images and output sounds.

Generally, in order to improve the sense of experience, the sound source data may have multiple channels, such as 8 channels, 9 channels, 12 channels, and so on. Exemplarily, 8 channels may include: left channel L, right channel R, left surround channel SL, right surround channel SR, left sky channel TOPL, right sky channel TOPR, center channel center, Subwoofer channel woofer. In order to enable the output of the aforementioned channels, the display device may be provided with multiple speakers, so that one speaker correspondingly plays one channel of audio.

For example, as shown in Figure 3, the display device is provided with 8 speakers Y1 to Y8, wherein the speaker Y1 plays the audio data corresponding to the left channel L, the speaker Y2 plays the audio data corresponding to the right channel R, and the speaker Y3 plays the corresponding audio data. The audio data of the left surround channel SL, the speaker Y4 plays the audio data corresponding to the right surround channel SR, the speaker Y5 plays the audio data corresponding to the left sky channel TOPL, the speaker Y6 plays the audio data corresponding to the right sky channel TOPR, and the speaker Y7 Play the audio data corresponding to the center channel center, and the speaker Y8 plays the audio data corresponding to the subwoofer channel woofer, so that the display device acts as a multi-channel device to play these channels of the sound source data.

Generally, the I2S bus interface is used to transmit audio data to the display device as a multi-channel device. No matter how many bits of valid data are in the signal of the I2S bus interface transmission format, the highest bit of the data always appears at the second bit clock BCLK pulse after the occurrence edge of the frame clock WS (that is, the beginning of a frame). In this way, the effective data bits of the receiving end and the transmitting end can be different. If the receiving end can handle less effective data bits than the sending end, it can give up the excess low data bits in the data frame; if the receiving end can handle more effective data bits than the sending end, it can make up the remaining bits by itself. This synchronization mechanism makes it more convenient to use the I2S bus interface to transmit audio data without causing data misalignment.

However, the main chip that processes sound source data in a multi-channel device generally uses 2 I2S bus interfaces or 3 I2S bus interfaces to output audio data. This makes it possible when the total number of I2S bus interfaces is less than the total number of audio data channels. This will cause the audio data corresponding to some channels to be missing during transmission, resulting in incomplete audio data transmitted to the multi-channel device, and reducing the playback effect of the multi-channel device.

As shown in Figure 1, the main signals involved in the transmission of the I2S bus interface are as follows:

(1) The serial clock BCLK, namely the bit clock, corresponds to each data bit of the digital audio signal, the frequency of BCLK=2×sampling frequency×sampling bits. For example, the frequency of BCLK=2*48KHz*16bit=1.536MHz.

(2) The frame clock WS is used to switch the data of the left and right channels. For example, WS of "1" means that the data of the left channel is being transmitted, and WS of "0" means that the data of the right channel is being transmitted. The frequency of WS is equal to the sampling frequency.

(3) Serial data SDATA, audio data expressed in twos complement.

Of course, in practical applications, the signals involved in the transmission of the I2S bus interface can also include some related signals, for example: MCLK master clock (ie system clock), the purpose is to enable better synchronization between systems, the frequency of MCLK is The sampling frequency is 256 times or 384 times, for example, 48KHz*256=12.288MHz.

As shown in Figure 1, when the I2S bus interface is transmitting, WS=0 (WS is a low-level signal), indicating that the data of the left channel (Left Channel) is being transmitted. WS=1 (WS is a high-level signal), indicating that the right channel (Right Channel) data is being transmitted. In other words, an I2S bus interface has two channels for transmitting audio data. Alternatively, WS=1 (WS is a high-level signal), indicating that the data of the left channel (Left Channel) is being transmitted. WS=0 (WS is a low-level signal), indicating that the data of the right channel (Right Channel) is being transmitted. Of course, in actual applications, this needs to be designed and determined according to the actual application environment, which is not limited here.

As shown in Figure 1, one channel of the I2S bus interface transmits audio data corresponding to the left channel, and the other channel transmits audio data corresponding to the right channel. Moreover, WS can change on the rising or falling edge of the serial clock BCLK, and the WS signal does not need to be symmetrical. Generally, on the slave device side, the highest bit of data always appears at the second bit clock BCLK pulse after the falling edge of the frame clock WS (that is, the start of a frame). That is, WS always changes one clock cycle before the highest bit transmission, so that the slave device can get the time synchronized with the serial data DATA being transmitted, and the receiving end can store the current command and clear space for the next command .

The embodiment of the present application provides an audio processing method, as shown in FIG. 2, which may include the following steps:

S100. Receive sound source data with multiple channels;

S200: Decode the sound source data to obtain original audio data corresponding to each channel;

S300. After re-encoding the original audio data according to a preset encoding rule, it is output through at least two first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all first I2S bus interfaces.

The audio processing method provided by the embodiment of the application first decodes the sound source data to obtain the original audio data corresponding to each channel. Since the total number of channels is greater than the total number of channels of all the first I2S bus interfaces, the original After the audio data is re-encoded, the original audio data of all channels can be output through at least two first I2S bus interfaces. In this way, the original audio data corresponding to all channels in the sound source file can be transmitted to the multi-channel device, thereby improving the playback effect of the multi-channel device.

The application will be described in detail below in conjunction with specific embodiments. It should be noted that the purpose of this embodiment is to better explain the application, but does not limit the application.

In the embodiment of the present application, after the original audio data is re-encoded according to a preset encoding rule, and outputted through at least two first I2S bus interfaces, it may include:

Determine the target audio data corresponding to each channel of each first I2S bus interface according to all the original audio data, the total number of channels of all the first I2S bus interfaces, and the communication rules of each channel of the first I2S bus interface; The data bits of the target audio data are greater than the data bits of the original audio data;

In the embodiment of the present application, determining the target audio data corresponding to each channel of each first I2S bus interface may include:

When it is determined that the quantity Q of all original audio data satisfies the formula: and, then add the same amount of blank original audio data to all original audio data, and select an original audio from all original audio data and the generated blank original audio data Data is split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces, and the data bits of the blank original audio data are the same as those of the original audio data;

The original audio data and the split audio data are combined into one target audio data.

Exemplarily, in the embodiment of the present application, the number of first I2S bus interfaces may be 2, and the total number of channels of all the first I2S bus interfaces is 4, that is, M=4. Since the total number of channels of the sound source data can be greater than the total number of channels of all the first I2S bus interfaces, the total number of channels can be 5, 6, 8, 12, 16, etc., which are not limited here.

Exemplarily, in the embodiment of the present application, the number of first I2S bus interfaces may also be three, and the total number of channels of all the first I2S bus interfaces is 6, that is, M=6. Since the total number of sound source data channels can be greater than the total number of channels of all the first I2S bus interfaces, the total number of channels can be 7, 8, 9, 12, 16, 18, 24, etc. , It is not limited here.

Of course, in actual applications, the number of the first I2S bus interface can be designed and determined according to the actual application environment, which is not limited here.

Illustratively, in the embodiment of the present application, N=2 may be set, or N=4 may be set, or N=6 may also be set. Of course, in actual applications, the number of N can be designed and determined according to the actual application environment, and is not limited here.

Generally, Dolby Atmos 5.1.2 technology multi-channel equipment can achieve better sound effects. Exemplarily, during specific implementation, in the embodiment of the present application, multiple channels may include: left channel, right channel, left surround channel, right surround channel, left sky channel, right sky channel , Center channel, subwoofer channel. In this way, the sound source file can be played using a multi-channel device with Dolby Atmos 5.1.2 technology. Of course, in actual applications, the specific sound channels of the sound channels can be designed and determined according to the actual application environment, which is not limited here.

Exemplarily, in the embodiment of the present application, the original audio data selected for splitting includes: original audio data corresponding to the center channel and original audio data corresponding to the subwoofer channel. In this way, the split data is spliced during subsequent decoding, so as to obtain the original audio data corresponding to the center channel and the original audio data corresponding to the subwoofer channel.

Generally, when playing sound on a multi-channel device, the center channel and the subwoofer channel have less influence on the playback effect. In addition, the split data may be affected during the general transmission process, which is not conducive to subsequent decoding and splicing. The embodiment of this application splits the original audio data corresponding to the center channel and the original audio data corresponding to the subwoofer channel. When the split data is affected during the transmission process, the center channel may not be decoded later. The original audio data corresponding to the sound channel and the original audio data corresponding to the subwoofer sound channel have little impact on the playback effect of the multi-channel device.

Generally, digital recording usually uses 16-bit (bit), 20-bit or 24-bit two's complement to make music sound source files. Exemplarily, during specific implementation, in the embodiment of the present application, the original audio data may be a digital signal with K data bits. Exemplarily, the original audio data may be a binary digital signal with data bits such as 16 bits (ie K=16), 20 bits (ie K=20), or 24 bits (ie K=24).

Exemplarily, in the embodiment of the present application, one piece of split audio data can be a digital signal with adjacent data bits; where K is a positive integer. Exemplarily, taking K=16 as an example, for example, if the original audio data is a digital signal of 0100 0010 0001 1101, the original audio data can be split according to the adjacent 8 data bits, thereby splitting into two Split audio data: One split audio data is 0100 0010, and the other split audio data is 0001 1101.

Exemplarily, as shown in Figure 4, the original audio data ch6: 16bit is used to generate split audio data ch6: high 8bit, ch6: low 8bit; the original audio data ch7: 16bit is generated to generate split audio data ch7: high 8bit, ch7 :low 8bit; Use blank original audio data ch8:16bit to generate split audio data ch8:high 8bit, ch8:low 8bit.

It should be noted that the blank original audio data does not carry audio information of the sound source, and it may be data formed by using "0". For example, if the original audio data is a digital signal of 0100 0010 0001 1101, the blank original audio data can be a digital signal of 0000 0000 0000 0000.

In order to improve the stability of transmission, reduce the time of subsequent decoding, and improve the efficiency of subsequent decoding, in the embodiment of the present application, the split audio data in the two target audio data corresponding to the same first I2S bus interface can be used Belong to the same original audio data.

In the embodiment of the present application, outputting the obtained target audio data through the corresponding channel of the first I2S bus interface may include:

Change the number of sampling bits of the first bit clock, start with the second pulse of the first bit clock after the edge change of the first frame clock, transmit the data bits of a single channel according to the first bit clock, so that each first I2S The bus interface transmits the target audio data of two channels in one cycle of a first frame clock.

Exemplarily, in the embodiment of the present application, one data bit is transmitted in one cycle of the first bit clock. In other words, the first bit clock uses single edge sampling. For example, use the rising or falling edge of each cycle to sample one data bit.

Exemplarily, in the embodiment of the present application, two data bits are transmitted in one cycle of the first bit clock. In other words, the first bit clock uses double-edge sampling. For example, use the rising and falling edges of each cycle to sample one data bit.

Exemplarily, in the embodiment of the present application, the sampling bit number of the first bit clock may be the same as the data bit of the target audio data.

In the embodiment of the present application, after the original audio data is re-encoded according to a preset encoding rule and then output through at least two first I2S bus interfaces, it may further include:

Receive the target audio data transmitted by each first I2S bus interface according to the second frame clock and the second bit clock, and re-decode the received data according to the preset encoding rules to obtain the original audio data; among them, the second frame clock The timing is the same as the timing of the first frame clock, and the timing of the second bit clock is the same as the timing of the first bit clock. In this way, the target audio data transmitted by each first I2S bus interface can be stably received. And restore the original audio data.

In the embodiment of the present application, receiving the target audio data transmitted by each first I2S bus interface according to the second frame clock and the second bit clock may include: receiving each first frame clock according to a second frame clock and a second bit clock. Target audio data transmitted by the I2S bus interface. This can reduce the number of output signals of the second frame clock and the second bit clock.

In the embodiment of the present application, receiving the target audio data transmitted by each first I2S bus interface according to the second frame clock and the second bit clock may also include: receiving each data according to multiple second frame clocks and multiple second bit clocks. The target audio data transmitted by the first I2S bus interface; wherein, one first I2S bus interface corresponds to a second frame clock and a second bit clock. In this way, the target audio data transmitted by each first I2S bus interface can be received independently, thereby avoiding transmission interference and improving transmission stability.

Exemplarily, in the embodiment of the present application, the data bits of the target audio data may be at most the data bits that can be transmitted in one channel of the first I2S bus interface. For example, generally one channel of the first I2S bus interface can transmit 32 bits of data, and the data bits of the target audio data can be at most 32 bits.

Exemplarily, in the embodiment of the present application, after re-decoding the received data according to a preset encoding rule to obtain each original audio data, it may further include: using multiple second I2S buses for each obtained original audio data The interface is output to a multi-channel device; among them, the number of the second I2S bus interface is one-half of all channels. In other words, one second I2S bus interface corresponds to two original audio data.

In the following, with reference to FIG. 4 to FIG. 7, taking the original audio data of 16 bits and the first I2S bus interface as an example, the audio processing method provided by the present application will be described through specific embodiments. However, readers should know that the specific process is not limited to this. Among them, the three first I2S bus interfaces are I2S_0, I2S_1, and I2S_2 respectively. FIG. 5 and FIG. 6 only take the transmission process of the target audio data SD1_0 and the target audio data SD2_0 as an example for description.

The audio processing method provided by the embodiments of the present application may include the following steps:

(1) Receive sound source data with left channel, right channel, left surround channel, right surround channel, left sky channel, right sky channel, center channel, and subwoofer channel. Wherein, the sound source data may be stored in a USB storage medium, or directly obtained through the network.

(2) Decode the sound source data to obtain the original audio data corresponding to each channel. Among them, any existing decoding method can be used to decode the sound source data to decode the original audio data corresponding to each channel.

For example, in conjunction with Figure 4, you can decode the 16bit original audio data ch0:16bit corresponding to the left channel, the 16bit original audio data ch1:16bit corresponding to the right channel, and the 16bit original audio data corresponding to the left surround channel. ch2:16bit, the 16bit original audio data corresponding to the right surround channel ch3:16bit, the 16bit original audio data corresponding to the left sky channel ch4:16bit, the 16bit original audio data corresponding to the right sky channel ch5:16bit, middle 16bit original audio data ch6:16bit corresponding to the set channel and 16bit original audio data ch7:16bit corresponding to the subwoofer channel.

(3) The number of all original audio data is 8, that is, Q=8, and the total number of channels of all the first I2S bus interfaces is 6, that is, M=6. Then N=2.

As shown in Figure 4, add 1 blank original audio data ch8:16bit to all original audio data, so that the 16bit original audio corresponding to the center channel can be selected from all the original audio data and the generated blank original audio data The data ch6:16bit, the 16bit original audio data ch7:16bit corresponding to the subwoofer channel, and the blank original audio data ch8:16bit are divided into 3 original audio data, so that the original audio data ch6:16bit generates the split audio data ch6: high 8bit, ch6: low 8bit; make the original audio data ch7: 16bit generate split audio data ch7: high 8bit, ch7: low 8bit; make blank original audio data ch8: 16bit generate split audio data ch8: high 8bit, ch8:low 8bit.

(4) As shown in Figure 4 and Figure 5, the original audio data ch0: 16bit and the split audio data ch6: high 8bit are spliced into the target audio data SD1_0, and the original audio data ch1: 16bit and the split audio data ch6: low 8bit is spliced into target audio data SD2_0, original audio data ch2:16bit and split audio data ch7:high 8bit are spliced into target audio data SD1_1, original audio data ch3:16bit and split audio data ch7:low 8bit are spliced into target Audio data SD2_1, splicing original audio data ch4:16bit and split audio data ch8:high 8bit into target audio data SD1_2, splicing original audio data ch5:16bit and split audio data ch8:low 8bit into target audio data SD2_2.

(5) As shown in Figure 4 and Figure 5, the data bit of a target audio data is changed from 16bit of the original audio data to 24bit, so the number of sampling bits of the first clock BCLK1 can be changed, so that the sampling of the first clock BCLK1 The number of bits is the same as that of a target audio data. In addition, one data bit is transmitted on the rising edge of each cycle of the first bit clock BCLK1.

When WS1=0, the channel of the first I2S bus interface I2S_0 corresponding to the left channel is controlled to transmit the target audio data SD1_0. Specifically, starting from the second first bit clock BCLK1 after the falling edge of the first frame clock WS1, the target audio data SD1_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD1_0 adopts the left sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when transmitting the target audio data SD1_0, the original audio data ch0: 16bit is transmitted sequentially from the highest bit, and then the split audio data ch6: high 16bit is sequentially transmitted from the highest bit.

When WS1=1, the channel of the first I2S bus interface I2S_0 corresponding to the right channel is controlled to transmit the target audio data SD2_0. Specifically, starting from the second first bit clock BCLK1 after the rising edge of the first frame clock WS1, the target audio data SD2_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD2_0 adopts the right sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when transmitting the target audio data SD2_0, the original audio data ch1: 16bit is transmitted sequentially from the highest bit, and then the split audio data ch6: low 16bit is sequentially transmitted from the highest bit.

Similarly, when WS1=0, the channel of the first I2S bus interface I2S_1 corresponding to the left channel is controlled to transmit the target audio data SD1_1. When WS1=1, the channel of the first I2S bus interface I2S_1 corresponding to the right channel is controlled to transmit the target audio data SD2_1.

In addition, when WS1=0, the channel of the first I2S bus interface I2S_2 corresponding to the left channel is controlled to transmit the target audio data SD1_2. When WS1=1, the channel of the first I2S bus interface I2S_2 corresponding to the right channel is controlled to transmit the target audio data SD2_2.

(6) As shown in FIG. 4 to FIG. 6, the timing of controlling the second frame clock WS2 is the same as that of the first frame clock WS1, and the timing of the second bit clock BCLK2 is the same as that of the first bit clock BCLK1.

According to the second frame clock WS2 and the second bit clock BCLK2, control to receive the target audio data SD1_0 and SD2_0 transmitted by the first I2S bus interface I2S_0, control to receive the target audio data SD1_1 and SD2_1 transmitted by the first I2S bus interface I2S_1, and control the reception The target audio data SD1_2 and SD2_2 transmitted by the first I2S bus interface I2S_2.

And according to the above preset coding rules, the preset clock signal YCLK is used to intercept the first 16bit data of the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2, and SD2_2 respectively, that is, to intercept the original audio data ch0:16bit, ch1: 16bit, ch2:16bit, ch3:16bit, ch4:16bit, ch5:16bit, and store the original audio data ch0:16bit and ch1:16bit in the channel stack corresponding to the left channel of the first and second I2S bus interface respectively And in the channel stack corresponding to the right channel, the original audio data ch2:16bit and ch3:16bit are respectively stored in the channel stack corresponding to the left channel and the channel stack corresponding to the right channel of the second I2S bus interface , And store the original audio data ch4:16bit and ch5:16bit respectively in the channel stack corresponding to the left channel and the channel stack corresponding to the right channel of the third second I2S bus interface, so as to restore the original audio data ch0 : 16bit, ch1: 16bit, ch2: 16bit, ch3: 16bit, ch4: 16bit, ch5: 16bit.

Then intercept the last 8bit data in the target audio data SD1_0, SD2_0, SD1_1, and SD2_1 respectively, and splice the last 8bit data in the target audio data SD2_0 after the last 8bit data in the target audio data SD1_0 to restore the original audio data ch6 by splicing: 16bit, and store the restored original audio data ch6:16bit in the channel stack corresponding to the left channel of the fourth second I2S bus interface. Splice the last 8bit data in the target audio data SD2_1 after the last 8bit data in the target audio data SD1_1 to restore the original audio data ch7:16bit by splicing, and store the restored original audio data ch7:16bit in the fourth Two I2S bus interface corresponding to the channel stack of the right channel. Thereby, the original audio data ch6:16bit and ch7:16bit are restored.

After that, the restored original audio data can be output to the power amplifier device in the multi-channel device through these second I2S bus interfaces, so as to drive the speaker to sound through the power amplifier device.

It should be noted that the preset clock signal may be a preset stored clock signal. Also, the period of the preset clock signal may be the same as the period of the bit clock. In actual applications, the frequency of the preset clock signal can be designed according to the actual application environment, which is not repeated here.

It should be noted that since the last 8bit data in the target audio data SD1_2 and SD2_2 is obtained by splitting blank original audio data, it is not carried in the sound source data, so the last 8bit data in the target audio data SD1_2 and SD2_2 can be 8bit data is deleted directly.

It can be seen from the above embodiment that when there are 3 I2S bus interfaces, sound source data with more than 6 channels can be transmitted, so that the original audio data corresponding to all channels in the sound source file can be transmitted to multiple In the channel device, the playback effect of the multi-channel device is further improved.

Of course, the received target audio data SD1_0 to SD2_2 can also be buffered first, and then the preset clock signal YCLK is used for intercepting respectively according to the foregoing embodiment. For specific implementation manners, reference may be made to the above-mentioned embodiments, which will not be repeated here.

In some embodiments, determining the target audio data corresponding to each channel of each first I2S bus interface may also include:

When it is determined that the quantity Q of all original audio data satisfies the formula:, select one original audio data from all the original audio data to split to generate split audio data; where N is a positive even number, and M represents all first I2S buses The total number of channels of the interface;

The original audio data and the split audio data are spliced into one target audio data.

In the following, with reference to FIGS. 5 to 8, taking the original audio data of 16 bits and the first I2S bus interface as an example, the audio processing method provided by the present application will be described through specific embodiments. However, readers should know that the specific process is not limited to this. Among them, the three first I2S bus interfaces are I2S_0, I2S_1, and I2S_2 respectively.

(1) Receive at least 9 channels including right channel, left surround channel, right surround channel, left sky channel, right sky channel, center channel, subwoofer channel and ninth channel Sound source data.

(2) Decode the sound source data to decode the 16bit original audio data ch0: 16bit corresponding to the left channel, the 16bit original audio data ch1: 16bit corresponding to the right channel, and the 16bit original audio data corresponding to the left surround channel. Audio data ch2: 16bit, 16bit original audio data corresponding to the right surround channel ch3: 16bit, 16bit original audio data corresponding to the left sky channel ch4: 16bit, 16bit original audio data corresponding to the right sky channel ch5: 16bit , 16bit original audio data ch6:16bit corresponding to the center channel, 16bit original audio data ch7:16bit corresponding to the subwoofer channel, and 16bit original audio data ch9:16bit corresponding to the ninth channel.

(3) The number of all original audio data is 9, that is, Q=9, and the total number of channels of all the first I2S bus interfaces is 6, that is, M=6. Then N=2. As shown in Figure 8, the 16-bit original audio data ch6:16bit corresponding to the center channel, the 16-bit original audio data ch7:16bit corresponding to the subwoofer channel, and the ninth channel can be directly selected from all the original audio data. The corresponding original audio data ch9:16bit, a total of 3 original audio data are split, so that the original audio data ch6:16bit generates split audio data ch6: high 8bit, ch6: low 8bit; the original audio data ch7: 16bit is generated and split Audio data ch7: high 8bit, ch7: low 8bit; make the original audio data ch9: 16bit generate split audio data ch9: high 8bit, ch9: low 8bit.

(4) As shown in Figure 8 and Figure 5, the original audio data ch0: 16bit and the split audio data ch6: high 8bit are spliced into the target audio data SD1_0, and the original audio data ch1: 16bit and the split audio data ch6: low 8bit is spliced into target audio data SD2_0, original audio data ch2:16bit and split audio data ch7:high 8bit are spliced into target audio data SD1_1, original audio data ch3:16bit and split audio data ch7:low 8bit are spliced into target Audio data SD2_1, splicing original audio data ch4:16bit and split audio data ch9:high 8bit into target audio data SD1_2, splicing original audio data ch5:16bit and split audio data ch9:low 8bit into target audio data SD2_2.

(5) As shown in Figure 8 and Figure 5, the data bit of a target audio data is changed from 16bit of the original audio data to 24bit, so the number of sampling bits of the first clock BCLK1 can be changed to make the first clock BCLK1 sample The number of bits is the same as that of a target audio data. In addition, one data bit is transmitted on the rising edge of each cycle of the first bit clock BCLK1.

(6) As shown in FIGS. 5 to 8, the timing of controlling the second frame clock WS2 is the same as the timing of the first frame clock WS1, and the timing of the second bit clock BCLK2 is the same as the timing of the first bit clock BCLK1.

And according to the above preset coding rules, the first 16bit data in the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2, and SD2_2 are respectively intercepted, that is, the original audio data ch0:16bit, ch1:16bit, ch2:16bit, ch3:16bit, ch4:16bit, ch5:16bit, and store the original audio data ch0:16bit and ch1:16bit respectively in the channel stack corresponding to the left channel of the first and second I2S bus interface and the channel stack corresponding to the right channel In the channel stack, the original audio data ch2:16bit and ch3:16bit are respectively stored in the channel stack corresponding to the left channel and the channel stack corresponding to the right channel of the second I2S bus interface, and the original audio data ch4:16bit and ch5:16bit are respectively stored in the channel stack corresponding to the left channel and the channel stack corresponding to the right channel of the third second I2S bus interface, so as to restore the original audio data ch0:16bit, ch1:16bit , Ch2: 16bit, ch3: 16bit, ch4: 16bit, ch5: 16bit.

Then intercept the last 8bit data in the target audio data SD1_0, SD2_0, SD1_1, and SD2_1 respectively, and splice the last 8bit data in the target audio data SD2_0 after the last 8bit data in the target audio data SD1_0 to restore the original audio data ch6 by splicing: 16bit, and store the restored original audio data ch6:16bit in the channel stack corresponding to the left channel of the fourth second I2S bus interface. Splice the last 8bit data in the target audio data SD2_1 after the last 8bit data in the target audio data SD1_1 to restore the original audio data ch7:16bit by splicing, and store the restored original audio data ch7:16bit in the fourth Two I2S bus interface corresponding to the channel stack of the right channel. And splicing the last 8bit data in the target audio data SD2_2 after the last 8bit data in the target audio data SD1_2 to restore the original audio data ch8:16bit by splicing, and store the restored original audio data ch8:16bit in the fifth In the channel stack corresponding to the left channel of the second I2S bus interface. Thereby, the original audio data ch6:16bit, ch7:16bit, and ch8:16bit are restored.

When it is determined that the quantity Q of all original audio data satisfies the formula:, the original audio data are combined into one target audio data; where N is a positive even number, and M represents the total number of channels of all the first I2S bus interfaces.

Exemplarily, when the number of the first I2S bus interface is 2, and the total number of channels of all the first I2S bus interface is 4, when the number of all original audio data is 8, it can be determined that each target audio data includes 2 Pieces of original audio data, that is, N=4.

Exemplarily, when the number of the first I2S bus interface is 3, the total number of channels of all the first I2S bus interface is 6, and when the number of all original audio data is 12, it can be determined that each target audio data includes 2 Pieces of original audio data, that is, N=4.

Of course, in actual applications, the number of first I2S bus interfaces and the number of all original audio data can be designed and determined according to the actual application environment, which is not limited here.

In the embodiment of the present application, when N=4, two original audio data in the same target audio data can be set as original audio data corresponding to the same type of channel. Exemplarily, these channels include at least: a left channel, a right channel, a left surround channel, a right surround channel, a left sky channel, a right sky channel, a center channel, and a subwoofer channel. Then the left and right channels can be used as the same type of main channel, the left and right surround channels can be used as the same type of surround channels, and the left and right sky channels can be used as the same type of sky Channel, center channel and subwoofer channel can be used as the same type of booster channel. The rest is the same, so I won't repeat it here.

9 to 12, taking the original audio data of 16 bits and the first I2S bus interface as an example, the audio processing method provided by the present application will be described through specific embodiments. However, readers should know that the specific process is not limited to this. Among them, the three first I2S bus interfaces are I2S_0, I2S_1, and I2S_2 respectively. FIG. 10 only uses the transmission process of the target audio data SD1_0 and the target audio data SD2_0 as an example for description.

(1) Receive sound source data with 12 channels. For example, these channels include at least: left channel, right channel, left surround channel, right surround channel, left sky channel, right sky channel, center channel, and subwoofer channel. The remaining channels can be designed and determined according to the actual application environment, which is not limited here.

(2) As shown in Figure 9, the sound source data is decoded using any existing decoding method to decode the original audio data corresponding to the 12 channels: ch0:16bit, ch1:16bit, ch2:16bit, ch3:16bit, ch4:16bit, ch5:16bit, ch6:16bit, ch7:16bit, ch8:16bit, ch9:16bit, ch10:16bit, ch11:16bit. Among them, ch0:16bit and ch1:16bit can be used as the original audio data corresponding to the same type of channel, ch2:16bit and ch3:16bit can be used as the original audio data corresponding to the same type of channel, ch4:16bit and ch5:16bit can be As the original audio data corresponding to the same type of channel, ch6:16bit and ch7:16bit can be used as the original audio data corresponding to the same type of channel, and ch8:16bit and ch9:16bit can be used as the original audio corresponding to the same type of channel Data, ch10:16bit and ch11:16bit can be used as the original audio data corresponding to the same type of channel.

(3) Since the number of first I2S bus interfaces is 3, the total number of channels of all first I2S bus interfaces is 6, that is, M=6. The number of all original audio data is 12, that is, Q=12. Then, N=4 can be used to combine two original audio data into one target audio data. For example, ch0:16bit and ch1:16bit are used as a target audio data SD1_0, ch2:16bit and ch3:16bit are used as a target audio data SD2_0, ch4:16bit and ch5:16bit are used as a target audio data SD1_1, and ch6:16bit And ch7:16bit as a target audio data SD2_1, ch8:16bit and ch9:16bit as a target audio data SD1_2, and ch10:16bit and ch11:16bit as a target audio data SD2_2.

(4) As shown in Figure 9 and Figure 10, the data bit of a target audio data is changed from 16bit of the original audio data to 32bit, so the number of sampling bits of the first bit clock BCLK1 can be changed without changing the first bit clock BCLK1 The sampling frequency is such that the sampling bits of the first clock BCLK1 are the same as the data bits of a target audio data. In addition, one data bit is transmitted on the rising edge of each cycle of the first bit clock BCLK1.

When WS1=0, the channel of the first I2S bus interface I2S_0 corresponding to the left channel is controlled to transmit the target audio data SD1_0. Specifically, starting from the second first bit clock BCLK1 after the falling edge of the first frame clock WS1, the target audio data SD1_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD1_0 adopts the left sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when transmitting the target audio data SD1_0, the original audio data ch0:16bit is transmitted sequentially from the highest bit, and then the original audio data ch1:16bit is sequentially transmitted from the highest bit.

When WS1=1, the channel of the first I2S bus interface I2S_0 corresponding to the right channel is controlled to transmit the target audio data SD2_0. Specifically, starting from the second first bit clock BCLK1 after the falling edge of the first frame clock WS1, the target audio data SD2_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD2_0 adopts the right sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when the target audio data SD2_0 is transmitted, the original audio data ch2:16bit is sequentially transmitted from the highest bit, and then the original audio data ch3:16bit is sequentially transmitted from the highest bit.

(5) As shown in Figure 9 to Figure 12, the first I2S bus interface I2S_0 corresponds to the second frame clock WS2_0 and the second bit clock BCLK2_0, and the first I2S bus interface I2S_1 corresponds to the second frame clock WS2_1 and the second bit clock BCLK2_1, The first I2S bus interface I2S_2 corresponds to the second frame clock WS2_2 and the second bit clock BCLK2_2. The timing of controlling the second frame clock WS2_0 to WS2_2 is the same as the timing of the first frame clock WS1, and the timing of the second bit clock BCLK2_0 to BCLK2_2 is the same as the timing of the first bit clock BCLK1.

According to the second frame clock WS2_0 and the second bit clock BCLK2_0, the target audio data SD1_0 and SD2_0 transmitted by the first I2S bus interface I2S_0 are controlled to be received. According to the second frame clock WS2_1 and the second bit clock BCLK2_1, control to receive the target audio data SD1_1 and SD2_1 transmitted by the first I2S bus interface I2S_1. According to the second frame clock WS2_2 and the second bit clock BCLK2_2, control to receive the target audio data SD1_2 and SD2_2 transmitted by the first I2S bus interface I2S_2.

And according to the above preset coding rules, the preset clock signal YCLK is used to intercept the first 16bit data of the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2, and SD2_2 respectively, that is, to intercept the original audio data ch0:16bit, ch2: 16bit, ch4: 16bit, ch6: 16bit, ch8: 16bit, ch10: 16bit.

And store the original audio data ch0:16bit in the channel stack corresponding to the left channel of the first second I2S bus interface, and store the original audio data ch2:16bit in the corresponding left channel of the second second I2S bus interface In the channel stack, store the original audio data ch4:16bit in the channel stack of the third second I2S bus interface corresponding to the left channel, and store the original audio data ch6:16bit in the fourth second I2S bus interface In the channel stack corresponding to the left channel, store the original audio data ch8:16bit in the channel stack corresponding to the left channel of the fifth second I2S bus interface, and store the original audio data ch10:16bit in the sixth Two I2S bus interface corresponding to the channel stack of the left channel. Thus, the original audio data ch0:16bit, ch2:16bit, ch4:16bit, ch6:16bit, ch8:16bit, and ch10:16bit are restored.

After that, the preset clock signal YCLK is used to intercept the last 16bit data of the target audio data SD1_0, SD2_0, SD1_1, SD2_1, SD1_2, and SD2_2 respectively, that is, to intercept the original audio data ch1:16bit, ch3:16bit, ch5:16bit, ch7: 16bit, ch9: 16bit, ch11: 16bit.

And store the original audio data ch1:16bit in the channel stack corresponding to the right channel of the first second I2S bus interface, and store the original audio data ch3:16bit in the corresponding right channel of the second second I2S bus interface In the channel stack, store the original audio data ch5:16bit in the channel stack of the third second I2S bus interface corresponding to the right channel, and store the original audio data ch7:16bit in the fourth second I2S bus interface In the channel stack corresponding to the right channel, store the original audio data ch9:16bit in the channel stack corresponding to the right channel of the fifth second I2S bus interface, and store the original audio data ch11:16bit in the sixth Two I2S bus interface corresponding to the channel stack of the left channel. Thereby, the original audio data ch1:16bit, ch3:16bit, ch5:16bit, ch7:16bit, ch9:16bit, ch11:16bit are restored.

After that, the restored original audio data ch0:16bit～ch11:16bit can be output to the power amplifier device in the multi-channel device using these second I2S bus interfaces, so as to drive the speaker to sound through the power amplifier device.

It should be noted that, when there are two I2S bus interfaces, the process of transmitting sound source data can refer to the above-mentioned embodiment, which is not repeated here.

In some embodiments, the audio processing method provided may also include the following steps in addition to the above steps (1) to (3):

(4) As shown in Figure 9 and Figure 13a to Figure 13c, the data bit of a target audio data is changed from 16bit of the original audio data to 32bit, so the sampling frequency of the first bit clock BCLK1 can be changed without changing the first bit clock The sampling bits of BCLK1 make the sampling bits of the first clock BCLK1 the same as the data bits of a target audio data. Among them, one data bit is transmitted on the rising and falling edges of each cycle of the first bit clock BCLK1.

When WS1=0, the channel of the first I2S bus interface I2S_0 corresponding to the left channel is controlled to transmit the target audio data SD1_0.

Specifically, starting from the second first bit clock BCLK1 after the falling edge of the first frame clock WS1, the target audio data SD1_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD1_0 adopts the left sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when transmitting the target audio data SD1_0, the original audio data ch0:16bit is transmitted sequentially from the highest bit, and then the original audio data ch1:16bit is sequentially transmitted from the highest bit.

(5) With reference to Figure 9 and Figures 14a to 15, the first I2S bus interface I2S_0 corresponds to the second frame clock WS2_0 and the second bit clock BCLK2_0, and the first I2S bus interface I2S_1 corresponds to the second frame clock WS2_1 and the second frame clock. The bit clock BCLK2_1, the first I2S bus interface I2S_2 corresponds to the second frame clock WS2_2 and the second bit clock BCLK2_2. The timing of controlling the second frame clock WS2_0 to WS2_2 is the same as the timing of the first frame clock WS1, and the timing of the second bit clock BCLK2_0 to BCLK2_2 is the same as the timing of the first bit clock BCLK1.

According to the second frame clock WS2_0 and the second bit clock BCLK2_0, control to receive the target audio data SD1_0 and SD2_0 transmitted by the first I2S bus interface I2S_0. According to the second frame clock WS2_1 and the second bit clock BCLK2_1, control to receive the target audio data SD1_1 and SD2_1 transmitted by the first I2S bus interface I2S_1. According to the second frame clock WS2_2 and the second bit clock BCLK2_2, control to receive the target audio data SD1_2 and SD2_2 transmitted by the first I2S bus interface I2S_2.

It should be noted. The timing of the preset clock signal YCLK may be the same as the timing of the second bit clock.

When determining that the quantity Q of all original audio data satisfies the formula:, add the same amount of blank original audio data to all original audio data, and select one original audio data from all original audio data and the generated blank original audio data. Split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces, and the data bits of the blank original audio data are the same as those of the original audio data;

In specific implementation, in the embodiment of the present application, the original audio data selected for splitting may include: blank original audio data. In this way, when the split data is affected during the transmission process, although the blank original audio data may not be decoded later, it has no effect on the playback effect of the multi-channel device.

Taking the first I2S bus interface as an example, M=4. The audio processing method provided by the embodiments of the present application may include the following steps:

(1) Receive sound source data with left channel, right channel, left surround channel, right surround channel, left sky channel, right sky channel, center channel, and subwoofer channel.

(2) As shown in Figure 16, the sound source data is decoded using any existing decoding method to decode the original 16bit audio data ch0:16bit corresponding to the left channel, and 16bit original audio data corresponding to the right channel ch1: 16bit, 16bit original audio data corresponding to the left surround channel ch2: 16bit, 16bit original audio data corresponding to the right surround channel ch3: 16bit, 16bit original audio data corresponding to the left sky channel ch4: 16bit, right 16bit original audio data ch5:16bit corresponding to the sky channel, 16bit original audio data ch6:16bit corresponding to the center channel, and 16bit original audio data ch7:16bit corresponding to the subwoofer channel.

(3) The number of all original audio data is 8, that is, Q=8, and the total number of channels of all the first I2S bus interfaces is 4, that is, M=4. Then N=4. As shown in Figure 16, add 4 blank original audio data ch01:16bit, ch02:16bit, ch03:16bit, ch04:16bit to all original audio data, so that it can be included in all original audio data and the generated blank original audio data , Select the blank original audio data ch01:16bit, ch02:16bit, ch03:16bit, ch04:16bit, and split the original audio data, and make the blank original audio data ch01:16bit generate split audio data ch01:high 8bit, ch01 :low 8bit; make blank original audio data ch02:16bit generate split audio data ch02:high8bit, ch02:low 8bit; make blank original audio data ch03:16bit generate split audio data ch03:high 8bit, ch03:low 8bit, and Let the blank original audio data ch04:16bit generate split audio data ch04:high 8bit and ch04:low 8bit.

(4) As shown in Figure 16 and Figure 17, the original audio data ch0: 16bit, ch1: 16bit and the split audio data ch01: high 8bit, ch01: low 8bit are spliced into the target audio data SD1_0, and the original audio data ch2: 16bit, ch3: 16bit and split audio data ch02: high 8bit, ch02: low 8bit are spliced into the target audio data SD2_0, and the original audio data ch4: 16bit, ch5: 16bit and the split audio data ch03: high 8bit, ch03: low 8bit is spliced into the target audio data SD1_1, and the original audio data ch6:16bit, ch7:16bit and the split audio data ch04:high 8bit, ch04:low 8bit are spliced into the target audio data SD2_1.

Taking the target audio data SD1_0 as an example, you can splice ch01:high 8bit after the lowest bit of ch0:16bit, and splice the highest bit of ch1:16bit after the lowest bit of ch01:high 8bit, and splice after the lowest bit of ch1:16bit ch01:low The lowest bit of 8bit. Others are the same, and so on, without limitation here.

(5) As shown in Figure 16 and Figure 17, the data bit of a target audio data is changed from 16bit of the original audio data to 48bit. Therefore, the sampling number and sampling frequency of the first clock BCLK1 can be changed to make the target audio data according to The first bit clock BCLK1 is transmitted. In addition, one data bit is transmitted on the rising edge and the falling edge of each cycle of the first bit clock BCLK1.

When WS1=0, the channel of the first I2S bus interface I2S_0 corresponding to the left channel is controlled to transmit the target audio data SD1_0. Specifically, starting from the second first bit clock BCLK1 after the falling edge of the first frame clock WS1, the target audio data SD1_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD1_0 adopts the left sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when the target audio data SD1_0 is transmitted, the original audio data ch0: 16bit is transmitted sequentially from the highest bit, and then the split audio data ch01: high 16bit is transmitted sequentially from the highest bit, and then the original audio data ch01: high 16bit is transmitted sequentially from the highest bit. The audio data ch1: 16bit, and then the split audio data ch01: low 16bit is transmitted sequentially starting from the highest bit.

When WS1=1, the channel of the first I2S bus interface I2S_0 corresponding to the right channel is controlled to transmit the target audio data SD2_0. Specifically, starting from the second first bit clock BCLK1 after the rising edge of the first frame clock WS1, the target audio data SD2_0 is transmitted according to the first bit clock BCLK1, so that the target audio data SD2_0 adopts the right sound of the first I2S bus interface I2S_0 Channel output corresponding to the channel. Among them, when the target audio data SD2_0 is transmitted, the original audio data ch2: 16bit is transmitted sequentially from the highest bit, and then the split audio data ch02: high 16bit is transmitted sequentially from the highest bit, and then the original audio data ch02: high 16bit is transmitted sequentially from the highest bit. Audio data ch3: 16bit, and then sequentially transmit the split audio data ch02: low 16bit from the highest bit.

(6) As shown in FIGS. 16 to 19, the timing of controlling the second frame clock WS2 is the same as that of the first frame clock WS1, and the timing of the second bit clock BCLK2 is the same as that of the first bit clock BCLK1.

And according to the above preset coding rules, the preset clock signal YCLK is used to intercept the first 16 bits of the target audio data SD1_0, SD2_0, SD1_1, and SD2_1 respectively, that is, to intercept the original audio data ch0: 16bit, ch2: 16bit, ch4: 16bit, ch6:16bit, and store the original audio data ch0:16bit in the channel stack corresponding to the left channel of the first second I2S bus interface, and store the original audio data ch2:16bit in the second second I2S bus In the channel stack corresponding to the left channel of the interface, store the original audio data ch4:16bit in the channel stack corresponding to the left channel of the third second I2S bus interface, and store the original audio data ch6:16bit in the fourth In the channel stack corresponding to the left channel of the second I2S bus interface. Thus, the original audio data ch0:16bit, ch2:16bit, ch4:16bit, and ch6:16bit are restored.

After that, the preset clock signal YCLK is used to intercept the next 8bit data of the target audio data SD1_0, SD2_0, SD1_1, SD2_1 respectively, that is, to intercept ch01: high 8bit, ch02: high 8bit, ch04: high 8bit, ch06: high 8bit. , You can delete the data directly.

After that, the preset clock signal YCLK is used to intercept the subsequent 16bit data in the target audio data SD1_0, SD2_0, SD1_1, SD2_1, that is, the original audio data ch1:16bit, ch3:16bit, ch5:16bit, ch7:16bit are respectively intercepted , And store the original audio data ch1:16bit in the channel stack corresponding to the right channel of the first second I2S bus interface, and store the original audio data ch3:16bit in the corresponding right sound of the second second I2S bus interface In the channel stack of the channel, store the original audio data ch5:16bit in the channel stack of the third second I2S bus interface corresponding to the right channel, and store the original audio data ch7:16bit in the fourth second I2S bus interface Corresponding to the channel stack of the right channel. Thereby, the original audio data ch1:16bit, ch3:16bit, ch5:16bit, ch7:16bit are restored.

You can directly delete the deleted data in SD1_0, SD2_0, SD1_1, and SD2_1 afterwards.

Based on the same application concept, an embodiment of the present application also provides an audio processing device, as shown in FIG. 20, including:

At least two first I2S bus interfaces 110;

The receiving circuit 120 is configured to receive sound source data with multiple channels;

The initial decoding circuit 130 is used to decode the sound source data to obtain the original audio data corresponding to each channel;

The re-encoding circuit 140 is electrically connected to at least two first I2S bus interfaces, and is configured to re-encode the original audio data according to a preset encoding rule, and then output it through at least two first I2S bus interfaces; wherein, the total number of channels It is greater than the total number of channels of all the first I2S bus interfaces.

In the embodiment of the present application, as shown in FIG. 20, the audio processing device may further include: a re-decoding circuit 150 electrically connected to at least two first I2S bus interfaces 150. The re-decoding circuit 150 is configured to receive the target audio data transmitted by each first I2S bus interface according to the second frame clock and the second bit clock, and re-decode the received data according to a preset encoding rule to obtain each original audio data; Among them, the timing of the second frame clock is the same as the timing of the first frame clock, and the timing of the second bit clock is the same as the timing of the first bit clock

In the embodiment of the present application, as shown in FIG. 20, the re-decoding circuit 150 transmits the re-decoded original audio data to the multi-channel device 160 through the multiple second I2S bus interfaces 170. In other words, the re-decoding circuit 150 may be electrically connected to the multi-channel device 160 through a plurality of second I2S bus interfaces 170.

The working principle and specific implementation of the audio processing device are the same as the principles and implementations of the audio processing method in the foregoing embodiment. Therefore, the working method of the audio processing device can refer to the specific implementation of the audio processing method in the foregoing embodiment. Implementation, I will not repeat it here.

In the embodiments of the present application, each of the foregoing circuits may adopt a form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Exemplarily, the primary decoding circuit may be a decoder capable of realizing its function. The re-encoding circuit may be an encoder capable of realizing its function. The re-decoding circuit can be a decoder or XMOS chip capable of realizing its function. Further, the above-mentioned first I2S bus interface, receiving circuit, initial decoding circuit and re-encoding circuit may form a main chip.

Based on the same application concept, an embodiment of the present application also provides a multi-channel system, including a multi-channel device and the audio processing device provided in the embodiment of the present application. The problem-solving principle of the multi-channel system is similar to that of the aforementioned audio processing device. Therefore, the implementation of the multi-channel system can refer to the implementation of the aforementioned audio processing device, and the repetition is not repeated here.

In the embodiment of the present application, the multi-channel device may be any product or component with a display function, such as a television, a notebook computer, etc., which is not limited herein.

Based on the same application concept, an embodiment of the application also provides a computer-readable storage medium on which a computer program is stored, and when the program is executed by a processor, it implements any of the audio processing methods provided in the embodiments of the application. step. Specifically, this application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) containing computer-usable program codes.

Based on the same application concept, an embodiment of the present application also provides a computer device, including a memory, a processor, and a computer program stored on the memory and running on the processor. The processor executes the program to implement the Steps of any of the above audio processing methods.

FIG. 21 is a schematic diagram of a display device provided in Embodiment 1 of the present application. With reference to FIG. 21, the present application also provides a display device, which at least includes: a display screen 91 configured to present image data; and a speaker 92 configured to reproduce sound data .

In some implementation examples, the display device may further include: a backlight assembly 94 located below the display screen 91. Usually some optical components are used to supply sufficient brightness and uniformly distributed light sources so that the display screen 91 can display images normally. In some related technologies, the backlight assembly may include an LED light bar or a light panel that automatically emits light.

In some embodiments, the display device may further include: a back plate 95. Usually, the back plate 95 is stamped to form some convex structures, and components such as speakers 92 are fixed on the convex structures by screws or hooks.

In some embodiments, the display device may further include: a rear case 98, which is covered on the back of the display screen 91 to hide the backlight assembly 94, the speaker 92 and other display device components, which has a beautiful effect.

In some embodiments, the display device may further include: a main board 96 and a power supply board 97, which can be arranged as two boards independently, or they can be combined on one board.

In some embodiments, the display device further includes a remote control 93.

FIG. 22 is a block diagram of the hardware configuration of the display device provided in Embodiment 1 of the present application. As shown in 22, the display device 200 may include a tuner and demodulator 220, a communicator 230, a detector 240, an external device interface 250, a controller 210, a memory 290, a user input interface, a video processor 260-1, and audio processing 260-2, display screen 280, audio input interface 272, power supply.

The tuner and demodulator 220, which receives broadcast and television signals through wired or wireless means, can perform modulation and demodulation processing such as amplification, mixing and resonance, and is used to demodulate the television channel selected by the user from multiple wireless or cable broadcast and television signals The audio and video signals carried in the frequency, and additional information (such as EPG data signals).

The tuner and demodulator 220 can be selected by the user and controlled by the controller 210 to respond to the TV channel frequency selected by the user and the TV signal carried by the frequency.

The tuner and demodulator 220 can receive signals in many ways according to different TV signal broadcasting systems, such as terrestrial broadcasting, cable broadcasting, satellite broadcasting, or Internet broadcasting; and according to different modulation types, it can be digital modulation or alternatively. Analog modulation method; and according to different types of received TV signals, analog and digital signals can be demodulated.

In some other exemplary embodiments, the tuner demodulator 220 may also be in an external device, such as an external set-top box. In this way, the set-top box outputs TV audio and video signals through modulation and demodulation, and inputs them to the display device 200 through the input/output interface 250.

The communicator 230 is a component for communicating with external devices or external servers according to various communication protocol types. For example, the communicator 230 may include a WIFI module 231, a Bluetooth communication protocol module 232, a wired Ethernet communication protocol module 233 and other network communication protocol modules or near field communication protocol modules.

The display device 200 may establish a control signal and a data signal connection with an external control device or content providing device through the communicator 230. For example, the communicator may receive the control signal of the remote controller 100 according to the control of the controller.

The detector 240 is a component of the display device 200 for collecting signals from the external environment or interacting with the outside. The detector 240 may include a light receiver 242, a sensor used to collect the intensity of ambient light, which can adaptively display parameter changes by collecting ambient light, etc.; it may also include an image collector 241, such as a camera, a camera, etc., which can be used to collect external Environmental scenes, as well as gestures used to collect user attributes or interact with users, can adaptively change display parameters, and can also recognize user gestures to achieve the function of interaction with users.

In some other exemplary embodiments, the detector 240 may further include a temperature sensor. For example, by sensing the ambient temperature, the display device 200 may adaptively adjust the display color temperature of the image.

In some embodiments, when the temperature is relatively high, the color temperature of the display device 200 can be adjusted to be relatively cool; when the temperature is relatively low, the color temperature of the display device 200 can be adjusted to be relatively warm.

In some other exemplary embodiments, the detector 240 may also include a sound collector, such as a microphone, which may be used to receive the user's voice, including the voice signal of the user's control instruction for controlling the display device 200, or to collect environmental sound for Recognizing the environmental scene type, the display device 200 can adapt to the environmental noise.

The external device interface 250 provides a component for the controller 210 to control data transmission between the display device 200 and other external devices. The external device interface can be connected to external devices such as set-top boxes, game devices, notebook computers, etc. in a wired/wireless manner, and can receive external devices such as video signals (such as moving images), audio signals (such as music), and additional information (such as EPG). ) And other data.

Among them, the external device interface 250 may include: a high-definition multimedia interface (HDMI) terminal 251, a composite video blanking synchronization (CVBS) terminal 252, an analog or digital component terminal 253, a universal serial bus (USB) terminal 254, red, green, and blue ( RGB) terminal (not shown in the figure) and any one or more.

The controller 210 controls the work of the display device 200 and responds to user operations by running various software control programs (such as an operating system and various application programs) stored on the memory 290.

As shown in FIG. 22, the controller 210 includes a random access memory RAM 213, a read only memory ROM 214, a graphics processor 216, a CPU processor 212, a communication interface 218, and a communication bus. Among them, RAM213 and ROM214, graphics processor 216, CPU processor 212, and communication interface 218 are connected by a bus.

ROM213, used to store various system startup instructions. For example, when the power-on signal is received, the power of the display device 200 starts to start, and the CPU processor 212 runs the system start-up instruction in the ROM, and copies the operating system stored in the memory 290 to the RAM 214 to start the start-up operating system. After the operating system is started up, the CPU processor 212 copies various application programs in the memory 290 to the RAM 214, and then starts to run and start various application programs.

The graphics processor 216 is used to generate various graphics objects, such as icons, operation menus, and user input instructions to display graphics. Including an arithmetic unit, which performs operations by receiving various interactive commands input by the user, and displays various objects according to display attributes. As well as including a renderer, various objects obtained based on the arithmetic unit are generated, and the rendering result is displayed on the display screen 280.

The CPU processor 212 is configured to execute operating system and application program instructions stored in the memory 290. And according to receiving various interactive instructions input from the outside, to execute various applications, data and content, so as to finally display and play various audio and video content.

In some exemplary embodiments, the CPU processor 212 may include multiple processors. The multiple processors may include one main processor and multiple or one sub-processors. The main processor is used to perform some operations of the display device 200 in the pre-power-on mode, and/or to display images in the normal mode. Multiple or one sub-processor, used to perform an operation in the standby mode and other states.

The communication interface may include the first interface 218-1 to the nth interface 218-n. These interfaces may be network interfaces connected to external devices via a network.

The controller 210 may control the overall operation of the display device 200. For example, in response to receiving a user command for selecting a UI object to be displayed on the display screen 280, the controller 210 may perform an operation related to the object selected by the user command.

Wherein, the object may be any one of the selectable objects, such as a hyperlink or an icon. Operations related to the selected object, for example: display operations connected to hyperlink pages, documents, images, etc., or perform operations corresponding to the icon. The user command for selecting the UI object may be a command input through various input devices (for example, a mouse, a keyboard, a touch pad, etc.) connected to the display device 200 or a voice command corresponding to the voice spoken by the user.

The memory 290 includes storing various software modules for driving and controlling the display device 200. For example, various software modules stored in the memory 290 include: a basic module, a detection module, a communication module, a display control module, a browser module, and various service modules.

Among them, the basic module is the underlying software module used for signal communication between various hardware in the display device 200 and sending processing and control signals to the upper module. The detection module is a management module used to collect various information from various sensors or user input interfaces, and perform digital-to-analog conversion and analysis management.

For example: the voice recognition module includes a voice analysis module and a voice command database module. The display control module is a module for controlling the display screen 280 to display image content, and can be used to play information such as multimedia image content and UI interfaces. The communication module is a module used for control and data communication with external devices. The browser module is a module used to perform data communication between browsing servers. The service module is a module used to provide various services and various applications.

At the same time, the memory 290 is also used to store and receive external data and user data, images of various items in various user interfaces, and visual effect diagrams of focus objects.

The user input interface 276 is used to send a user's input signal to the controller 210, or to transmit a signal output from the controller to the user. In some embodiments, the control device (for example, a mobile terminal or a remote control) can send input signals input by the user, such as a power switch signal, a channel selection signal, and a volume adjustment signal, to the user input interface, and then the user input interface 276 forwards it to the user input interface. Controller; or, the control device may receive output signals such as audio, video or data output from the user input interface processed by the controller, and display the received output signal or output the received output signal as audio or vibration.

In some embodiments, the user may input a user command on a graphical user interface (GUI) displayed on the display screen 280, and the user input interface receives the user input command through the graphical user interface (GUI). Alternatively, the user can input a user command by inputting a specific voice or gesture, and the user input interface recognizes the voice or gesture through the sensor to receive the user input command.

The video processor 260-1 is used to receive video signals, and perform video data processing such as decompression, decoding, scaling, noise reduction, frame rate conversion, resolution conversion, and image synthesis according to the standard codec protocol of the input signal. The video signal directly displayed or played on the display screen 280.

In some embodiments, the video processor 260-1 includes a demultiplexing module, a video decoding module, an image synthesis module, a frame rate conversion module, a display formatting module, and the like.

Among them, the demultiplexing module is used to demultiplex the input audio and video data stream. For example, if MPEG-2 is input, the demultiplexing module will demultiplex into a video signal and an audio signal.

The video decoding module is used to process the demultiplexed video signal, including decoding and scaling.

An image synthesis module, such as an image synthesizer, is used to superimpose and mix the GUI signal generated by the graphics generator with the zoomed video image according to user input or itself to generate an image signal for display.

Frame rate conversion module, used to convert the frame rate of the input video, such as converting the frame rate of the input 24Hz, 25Hz, 30Hz, 60Hz video to the frame rate of 60Hz, 120Hz or 240Hz, where the input frame rate can be compared with the source The video stream is related, and the output frame rate can be related to the update rate of the display. The input has a usual format, such as frame insertion.

The display formatting module is used to change the signal output by the frame rate conversion module into a signal that conforms to a display format such as a display, such as format conversion of the signal output by the frame rate conversion module to output RGB data signals.

The display screen 280 is used to receive image signals input from the video processor 260-1, to display video content and images, and a menu control interface. The display screen 280 includes a display screen component for presenting a picture and a driving component for driving image display. The displayed video content can be from the video in the broadcast signal received by the tuner and demodulator 220, or from the video content input by the communicator or the external device interface. The display screen 280 simultaneously displays a user manipulation interface UI generated in the display device 200 and used to control the display device 200.

And, depending on the type of the display screen 280, a driving component for driving the display is also included. Alternatively, if the display screen 280 is a projection display, it may also include a projection device and a projection screen.

The audio processor 260-2 is used to receive audio signals, and perform decompression and decoding according to the standard codec protocol of the input signal, as well as audio data processing such as noise reduction, digital-to-analog conversion, and amplification processing, and the result can be in the speaker 272 The audio signal to be played.

The audio output interface 270 is used to receive the audio signal output by the audio processor 260-2 under the control of the controller 210. The audio output interface may include a speaker 272 or output to an external audio output terminal 274 of a generator of an external device, such as : External audio terminal or headphone output terminal, etc.

In some other exemplary embodiments, the video processor 260-1 may include one or more chips. The audio processor 260-2 may also include one or more chips.

And, in some other exemplary embodiments, the video processor 260-1 and the audio processor 260-2 may be separate chips, or they may be integrated with the controller 210 in one or more chips.

The power supply 275 is used to provide power supply support for the display device 200 with power input from an external power supply under the control of the controller 210. The power supply 275 may include a built-in power supply circuit installed inside the display device 200, or may be a power supply installed outside the display device 200, such as a power interface for providing an external power supply in the display device 200.

An embodiment of the present application also provides a display device, including:

The display screen is configured to present image data;

The speaker is configured to reproduce sound data;

In some embodiments, the controller is further configured to determine according to all the original audio data, the total number of channels of all the first I2S bus interfaces, and the communication rules of each channel of the first I2S bus interface The target audio data corresponding to each channel of each of the first I2S bus interface; wherein the data bits of the target audio data are larger than the data bits of the original audio data; the obtained target audio data is passed through the corresponding Channel output of the first I2S bus interface.

In some embodiments, the controller is further configured to, when determining that the quantity Q of all the original audio data satisfies the formula:, combine the original audio data into one target audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces; or,

In some embodiments, the original audio data selected for splitting includes: blank original audio data.

In some embodiments, when it is determined that the quantity Q of all the original audio data satisfies the formula: and, then the same number of blank original audio data is added to all the original audio data, and all the original audio data And the generated blank original audio data, select one original audio data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interfaces, and the blank original The data bits of the audio data are the same as the data bits of the original audio data;

In some embodiments, when it is determined that the quantity Q of all the original audio data satisfies the formula:, then select one original audio data from all the original audio data for splitting to generate split audio data; where N is A positive even number, M represents the total number of channels of all the first I2S bus interfaces;

In some embodiments, the original audio data is a digital signal with K data bits, and one piece of the split audio data is a digital signal with adjacent data bits; where K is a positive integer.

In some embodiments, changing the sampling number of the first bit clock and/or changing the sampling frequency of the first bit clock starts at the second pulse of the first bit clock after the edge change of the first frame clock, The data bits of a single channel are transmitted according to the first bit clock, so that each of the first I2S bus interfaces transmits two channels of target audio data in one cycle of the first frame clock.

In some embodiments, one cycle of the first bit clock transmits two data bits; or, one cycle of the first bit clock transmits one data bit.

For the foregoing specific implementation manner, reference may be made to the introduction of the foregoing embodiment, and no further description is provided here.

Obviously, those skilled in the art can make various changes and modifications to the application without departing from the spirit and scope of the application. In this way, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application also intends to include these modifications and variations.

Claims

A display device, characterized by comprising:

The display screen is configured to present image data;

The speaker is configured to reproduce sound data;

An audio processor, configured to receive sound source data having multiple channels, and decode the sound source data to obtain original audio data corresponding to each of the channels;

A controller, configured to re-encode the original audio data according to a preset encoding rule, and output to the speaker through at least two first I2S bus interfaces;

Wherein, the total number of channels is greater than the total number of channels of all the first I2S bus interfaces.
8. The display device of claim 1, wherein the controller is configured to re-encode the original audio data according to a preset encoding rule, and then output it through at least two first I2S bus interfaces, comprising:

Determine each channel of each first I2S bus interface according to all the original audio data, the total number of channels of all the first I2S bus interfaces, and the communication rules of each channel of the first I2S bus interface Corresponding target audio data; wherein the data bits of the target audio data are greater than the data bits of the original audio data;

The obtained target audio data is output through the corresponding channel of the first I2S bus interface.
3. The display device according to claim 2, wherein the controller is configured to determine the target audio data corresponding to each channel of each of the first I2S bus interface, comprising:

When determining that the quantity Q of all the original audio data satisfies the formula:, combine the original audio data into one target audio data; where N is a positive even number, and M represents the total number of channels of all the first I2S bus interfaces ;or,

When it is determined that the quantity Q of all the original audio data satisfies the formula:, add the same amount of blank original audio data to all the original audio data, and add the same amount of blank original audio data to all the original audio data and the generated blank original audio Select one piece of original audio data from the data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interface, and the data bits of the blank original audio data are the same as those of the The data bits of the original audio data are the same;

Combine pieces of original audio data and pieces of split audio data into one target audio data.
3. The display device of claim 2, wherein the controller is configured to select the original audio data for splitting comprises: blank original audio data.
3. The display device according to claim 2, wherein the controller is configured to determine the target audio data corresponding to each channel of each of the first I2S bus interface, comprising:

When it is determined that the quantity Q of all the original audio data satisfies the formula: and, the same number of blank original audio data is added to all the original audio data, and all the original audio data and the generated blank Select one piece of original audio data from the original audio data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interface, and the data bits of the blank original audio data are The data bits of the original audio data are the same;

Combine pieces of original audio data and pieces of split audio data into one target audio data.
3. The display device according to claim 2, wherein the controller is configured to determine the target audio data corresponding to each channel of each of the first I2S bus interface, comprising:

When it is determined that the quantity Q of all the original audio data satisfies the formula:, select one original audio data from all the original audio data for splitting to generate split audio data; where N is a positive even number, and M represents all The total number of channels of the first I2S bus interface;

Splicing pieces of original audio data and pieces of split audio data into one target audio data.
The display device according to claim 5 or 6, wherein the controller is configured so that the original audio data is a digital signal with K data bits, and one of the split audio data has adjacent data bits. Bit digital signal; among them, K is a positive integer.
7. The display device according to any one of claims 2-6, wherein the controller is configured to output the obtained target audio data through a channel of the corresponding first I2S bus interface, comprising:

Change the number of sampling bits of the first bit clock and/or change the sampling frequency of the first bit clock, starting from the second pulse of the first bit clock after the edge change of the first frame clock, according to the first bit clock The clock transmits data bits of a single channel, so that each of the first I2S bus interfaces transmits target audio data of two channels in one cycle of the first frame clock.
8. The display device of claim 8, wherein the controller is configured to transmit two data bits in one cycle of the first bit clock; or, to transmit one data in one cycle of the first bit clock Bit.
An audio processing device, characterized by comprising:

At least 2 first I2S bus interfaces;

A receiving circuit for receiving sound source data with multiple channels;

A preliminary decoding circuit, which is used to decode the sound source data to obtain original audio data corresponding to each of the channels;

The re-encoding circuit is electrically connected to the at least two first I2S bus interfaces, and is configured to re-encode the original audio data according to a preset encoding rule, and output it through at least two first I2S bus interfaces; The total number of channels is greater than the total number of channels of all the first I2S bus interfaces.
An audio processing method, characterized by comprising:

Receive sound source data with multiple channels;

Decoding the sound source data to obtain original audio data corresponding to each of the channels;

After re-encoding the original audio data according to a preset encoding rule, it is output through at least two first I2S bus interfaces; wherein the total number of channels is greater than the total number of channels of all the first I2S bus interfaces.
11. The audio processing method of claim 11, wherein the re-encoding of the original audio data according to a preset encoding rule and then outputting through at least two first I2S bus interfaces comprises:

Determine each channel of each first I2S bus interface according to all the original audio data, the total number of channels of all the first I2S bus interfaces, and the communication rules of each channel of the first I2S bus interface Corresponding target audio data; wherein the data bits of the target audio data are greater than the data bits of the original audio data;

The obtained target audio data is output through the corresponding channel of the first I2S bus interface.
The audio processing method of claim 12, wherein the determining the target audio data corresponding to each channel of each of the first I2S bus interface comprises:

When determining that the quantity Q of all the original audio data satisfies the formula:, combine the original audio data into one target audio data; where N is a positive even number, and M represents the total number of channels of all the first I2S bus interfaces ;or,

When it is determined that the quantity Q of all the original audio data satisfies the formula:, add the same amount of blank original audio data to all the original audio data, and add the same amount of blank original audio data to all the original audio data and the generated blank original audio Select one piece of original audio data from the data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interface, and the data bits of the blank original audio data are the same as those of the The data bits of the original audio data are the same;

Combine pieces of original audio data and pieces of split audio data into one target audio data.
The audio processing method according to claim 12, wherein the original audio data selected for splitting comprises: blank original audio data.
The audio processing method of claim 12, wherein the determining the target audio data corresponding to each channel of each of the first I2S bus interface comprises:

When it is determined that the quantity Q of all the original audio data satisfies the formula: and, the same number of blank original audio data is added to all the original audio data, and all the original audio data and the generated blank Select one piece of original audio data from the original audio data to split to generate split audio data; where N is a positive even number, M represents the total number of channels of all the first I2S bus interface, and the data bits of the blank original audio data are The data bits of the original audio data are the same;

Combine pieces of original audio data and pieces of split audio data into one target audio data.
The audio processing method of claim 12, wherein the determining the target audio data corresponding to each channel of each of the first I2S bus interface comprises:

When it is determined that the quantity Q of all the original audio data satisfies the formula:, select one original audio data from all the original audio data for splitting to generate split audio data; where N is a positive even number, and M represents all The total number of channels of the first I2S bus interface;

Splicing pieces of original audio data and pieces of split audio data into one target audio data.
The audio processing method according to claim 15 or 16, wherein the original audio data is a digital signal with K data bits, and one of the split audio data is a digital signal with adjacent data bits ; Among them, K is a positive integer.
The audio processing method of claim 15 or 16, wherein the split audio data in the two target audio data corresponding to the same first I2S bus interface belong to the same original audio data.
The audio processing method of claim 15 or 16, wherein the multiple channels include: left channel, right channel, left surround channel, right surround channel, left sky channel, right sky Channel, center channel, subwoofer channel;

The original audio data selected for splitting includes: original audio data corresponding to the center channel and original audio data corresponding to the subwoofer channel.