WO2021004049A1

WO2021004049A1 - Display device, and audio data transmission method and device

Info

Publication number: WO2021004049A1
Application number: PCT/CN2020/070929
Authority: WO
Inventors: 李见; 黄飞
Original assignee: 海信视像科技股份有限公司
Priority date: 2019-07-09
Filing date: 2020-01-08
Publication date: 2021-01-14
Also published as: WO2021004045A1; WO2021004047A1; WO2021004048A1; WO2021004046A1

Abstract

Provided in the embodiments of the present application are a display device and an audio data transmission method and device, which relate to the field of audio data processing. The embodiments of the present application can transmit more channels of data by means of limited I2S channel resources. The method comprises: acquiring m channels of audio data; and sending the m channels of audio data to a data receiving end by means of n I2S channels, wherein m>n. The present application is applied to audio data processing.

Description

Display device, audio data transmission method and device

This patent application requires the application number of 201910614701.7 filed on July 9, 2019; the application number of 201910613160.6 filed on July 9, 2019; the application number of 201910613254.3 filed on July 9, 2019; The application number submitted on July 9, 2019 is 201910615836.5; the application number submitted on July 9, 2019 is 201910616404.6; the application number submitted on August 2, 2019 is 201910710346.3; on July 9, 2019 The priority of the Chinese patent application filed on July 22, 2019 with application number 2019106185413; application number 201910659488.1 filed on July 22, 2019, the full text of which is incorporated herein by reference.

Technical field

This application relates to the field of audio data processing, and in particular to a method and device for transmitting audio data of a display device.

Background technique

At present, the televisions produced by various manufacturers mostly adopt the two-channel stereo standard, that is, the audio data that needs to be played is processed and transmitted to the two speakers of the television for output. Exemplarily, in the related art, a television set usually uses a speaker on the left and right sides to output the audio data of the left channel and the right channel respectively. The audio effect of the TV using this audio playback method is poor. At this time, it is necessary to increase the number of speakers of the TV and increase the playback channels of different channels to achieve a more realistic stereo surround effect.

Take the 7.1-channel standard as an example, in order to achieve a 7.1-channel surround effect. The TV needs to be able to play the front left channel, front right channel, center channel, surround left channel, surround right channel, top left channel, top right channel, and 8 channels of heavy bass.

In the related art, one I2S bus in the I2S standard includes two I2S channels, so one I2S bus can only transmit data of two channels. If 7.1 channel data needs to be played, at least 4 I2S buses are required for data transmission between the master chip and the slave device (for example, between the master decoder chip and the power amplifier chip).

In the current related technology, the TV main control board usually only supports 3 I2S buses or even less, which greatly limits the number of TV channels. If you want to achieve true multi-channel audio playback, you need to increase the number of I2S buses between the master chip and the slave devices. This requires a redesign of the TV main control board, which is costly.

Application content

The embodiments of the present application provide a display device, an audio data transmission method and device, which can utilize limited I2S channel resources to transmit more channel data.

In some embodiments, the present application provides an audio data transmission method, including: obtaining audio data of m channels; using n I2S channels to send m channels of audio data to the data receiving end; where m >n.

In some embodiments, the present application provides another audio data transmission method, including: receiving transmission data sent by n I2S channels; converting the transmission data sent by n I2S channels into audio data of m channels; wherein , M>n.

In some embodiments, an embodiment of the present application provides an audio data transmission device, including: an acquisition unit for acquiring audio data of m channels; a sending unit for using n I2S channels to transfer m channels The audio data is sent to the data receiving end; where m>n.

In some embodiments, the embodiments of the present application provide another audio data transmission device, including: a receiving unit for receiving transmission data sent by n I2S channels; a conversion unit for transferring transmission data sent by n I2S channels , Converted to audio data of m channels; where m>n.

In some embodiments, the embodiments of the present application provide another audio data transmission device, including: a processor, a memory, a bus, and a communication interface; the memory is used to store computer execution instructions, and the processor and the memory are connected through the bus. When the transmission device is running, the processor executes the computer-executable instructions stored in the memory, so that the audio data transmission device executes the audio data transmission method provided in some embodiments.

In some embodiments, the embodiments of the present application provide a computer storage medium, including instructions, which when run on an audio data transmission device, cause the audio data transmission device to execute the audio data transmission method provided in some embodiments. .

In some embodiments, the embodiments of the present application provide a TV. When the TV is running, the TV is made to execute the above-mentioned embodiments and any one of its implementations, and/or in some embodiments and any one of them. An implementation of audio data transmission method.

The display device, audio data transmission method and device provided in the embodiments of the application consider that when using the I2S channel for audio data transmission, it is not necessary to limit one I2S channel to only transmit one channel of audio without following the content of the I2S protocol. Data, but uses the application concept of decoupling the number of I2S channels and the number of channels. Furthermore, this application adopts the method of sending m channels of audio data to the data receiving end by using n I2S channels, which can avoid the inability to transmit due to the limitation of the I2S protocol itself on the number of channels in the transmission process The problem of audio data with more channels than I2S channels.

Description of the drawings

In order to more clearly describe the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art.

FIG. 1 is one of the signal timing diagrams of an I2S channel provided by an embodiment of the application;

FIG. 2 is the second schematic diagram of signal timing of an I2S channel provided by an embodiment of the application;

FIG. 3 is one of the schematic diagrams of the appearance of a television provided by an embodiment of the application;

FIG. 4 is a second schematic diagram of the appearance of a television provided by an embodiment of the application;

FIG. 5 is one of the structural schematic diagrams of a television provided by an embodiment of the application;

FIG. 6 is one of the schematic flowcharts of an audio data transmission method provided by an embodiment of this application;

FIG. 7 is the third schematic diagram of a signal sequence of an I2S channel provided by an embodiment of this application;

FIG. 8 is one of the schematic diagrams of a data transmission structure provided by an embodiment of this application;

9 is a second schematic flowchart of an audio data transmission method provided by an embodiment of this application;

FIG. 10 is the second schematic diagram of a data transmission structure provided by an embodiment of this application;

FIG. 11 is a fourth schematic diagram of signal timing of an I2S channel provided by an embodiment of this application;

FIG. 12 is the third schematic diagram of a data transmission structure provided by an embodiment of this application;

FIG. 13 is the third schematic flowchart of an audio data transmission method provided by an embodiment of this application;

FIG. 14 is a fourth schematic diagram of a data transmission structure provided by an embodiment of this application;

15 is a fifth schematic diagram of a data transmission structure provided by an embodiment of this application;

FIG. 16 is the second structural diagram of a TV set provided by an embodiment of the application;

FIG. 17 is a schematic diagram of a protocol architecture of a device provided by an embodiment of this application;

FIG. 18 is the fourth schematic diagram of an audio data transmission method provided by an embodiment of this application;

19 is the fifth of the sixth schematic diagrams of an audio data transmission method provided by an embodiment of this application;

20 is a sixth schematic diagram of a data transmission structure provided by an embodiment of this application;

21 is a seventh schematic diagram of a data transmission structure provided by an embodiment of this application;

FIG. 22 is one of the schematic structural diagrams of an audio data transmission device provided by an embodiment of this application;

FIG. 23 is the second structural diagram of an audio data transmission device provided by an embodiment of this application;

24 is the third structural diagram of an audio data transmission device provided by an embodiment of this application;

25 is the fourth structural diagram of an audio data transmission device provided by an embodiment of this application;

FIG. 26 is the fifth structural diagram of an audio data transmission device provided by an embodiment of this application;

FIG. 27 is a sixth structural diagram of an audio data transmission device provided by an embodiment of this application;

FIG. 28 is a schematic diagram of a display device provided in Embodiment 1 of the present application;

FIG. 29 is a block diagram of the hardware configuration of the display device provided in Embodiment 1 of the present application.

Detailed ways

The embodiments of the present application will be described in detail below in conjunction with the drawings.

The terms "first" and "second" in the description of the application and the drawings are used to distinguish different objects, rather than to describe the specific order of the objects.

In addition, the terms "including" and "having" and any variations of them mentioned in the description of this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes other steps or units that are not listed, or optionally also Including other steps or units inherent to these processes, methods, products or equipment.

It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" are used as examples, illustrations, or illustrations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferable or advantageous than other embodiments or design solutions. To be precise, words such as "exemplary" or "for example" are used to present related concepts in a specific manner.

The "and/or" mentioned in this application includes using any one of the two methods or using both methods at the same time.

In the description of this application, unless otherwise specified, the meaning of "plurality" means two or more.

First, explain the technical terms involved in the embodiments of this application:

I2S (Inter-IC Sound) bus, also known as integrated circuit audio bus, is a bus standard developed by Philips for audio data transmission between digital audio devices. In the I2S protocol adopted by the I2S bus, one I2S bus can include two I2S channels for data transmission. Among them, when the frame clock signal WS is "0", data of one channel is transmitted, and when WS is "1", data of another channel is transmitted. In the related I2S protocol, the two I2S channels included in one I2S bus are used to transmit data of different channels respectively (where WS=0, it means that the data being transmitted is the data of the left channel; when WS= When 1, it means that the data being transmitted is the data of the right channel).

Among them, one I2S bus mainly includes: MCLK, BCLK, SDATA, WS and other main signals, of which:

BCLK, the serial clock. Corresponding to each bit of digital audio data, BCLK has 1 pulse.

WS, the frame clock. WS is used to switch the left and right channel data. When WS is "1", it means that the data of the left channel is being transmitted, and "0" means that the data of the right channel is being transmitted. The frequency of WS is equal to the sampling frequency of audio data. For example, when the sampling frequency of certain audio data is 48KHz, it means that 48K left channel sub-data and 48K right channel sub-data need to be played every second. Furthermore, the frequency of WS also needs to be 48KHz in order to transmit the audio data normally.

SDATA, namely serial data. It is used to transmit audio data in the way of twos complement.

MCLK, the master clock, is also called the system clock. Used to better synchronize the data sender system and the data receiver system. Under normal circumstances, the frequency of MCLK is 256 times or 384 times the sampling frequency. For example, if the sampling frequency of audio data is 48KHz, MCLK is 48KHz*256=12.288MHz.

With the development of technology, there are multiple data formats when using the I2S bus to transmit data. According to the different positions of SDATA relative to WS and BCLK, it is divided into I2S standard format (the format specified by Philips), left-justified and right-justified.

Exemplarily, as shown in Figure 1, when the I2S bus adopts a 16-bit right-aligned transmission mode, within a sampling period T, when WS changes from "0" to "1", SDATA is used to transmit left sound Channel data, and in the last 16 BCLK cycles included in WS, the 16 bits of data are transmitted sequentially from the high bit to the low bit using SDATA according to the way of collecting the rising edge of BCLK. When the I2S bus adopts the 20bit right-aligned transmission mode, in a sampling period T, after WS changes from "0" to "1", in the last 20 BCLK cycles included in WS, the data collected according to the rising edge of BCLK Way, use SDATA to transmit 20bit data from high to low in sequence. When the I2S bus adopts the 24-bit right-aligned transmission mode, in a sampling period T, after WS changes from "0" to "1", in the last 24 BCLK cycles included in WS, the data collected according to the rising edge of BCLK In this way, 24bit data is transmitted sequentially from the high bit to the low bit using SDATA.

As shown in Figure 1, when the I2S bus adopts a 24-bit left-aligned transmission mode, within a sampling period T, after WS changes from "0" to "1", it starts from the first BCLK cycle after WS changes. According to the way of collecting on the rising edge of BCLK, use SDATA to transmit 24bit data sequentially from the high bit to the low bit.

Another example is shown in Figure 2, which is a schematic diagram of the transmission of the I2S standard format. Among them, at the second BCLK pulse after the change of WS (as shown in the figure, take the second rising edge of BCLK as an example) to start data transmission. Specifically, the figure respectively shows schematic diagrams of the transmission process in 24bit mode, 20bit mode, and 16bit mode.

The embodiments of the present application are applied in a scenario where the aforementioned I2S bus is used for audio data transmission.

The following describes the application principle of this application: At present, the televisions produced by various manufacturers mostly adopt the two-channel stereo standard, that is, the audio data to be played is processed and transmitted to the two speakers of the television for output.

Exemplarily, as shown in FIG. 3, current televisions often use one speaker on the left and right sides to output the audio data of the left channel and the right channel respectively. The audio effect of TV sets using this audio playback method is poor. In related technologies, audio data standards are getting higher and higher, and more audio-visual materials use audio data of 5.1, 7.1 or even higher standards. These high-standard audio data will get multiple channels of data after being decoded. In the related technology, TV sets and currently commonly used audio data standards are getting higher and higher, and more audio data uses 5.1, 7.1 or even higher sound The road standard has only two speakers. At this time, it is necessary to increase the number of speakers of the TV and increase the playback channels of different channels to achieve a more realistic stereo surround effect.

Take the 7.1-channel standard as an example, as shown in Figure 4, in order to achieve a 7.1-channel surround effect. The TV needs to be able to play the front left channel, the front right channel, the center channel, the surround left channel, the surround right channel, the top left channel, the top right channel, and the heavy bass (where the heavy bass is usually set On the back of the TV, not shown in the figure) 8-channel playback.

At present, the conventional TV main control board usually only supports 3 I2S buses or even less, which greatly limits the number of TV channels. If you want to achieve true multi-channel audio playback, you need to increase the number of I2S buses between the master chip and the slave devices. This requires a redesign of the TV main control board, which is costly.

Based on the above technical problems, in the embodiments of the present application, it is thought that if the limited I2S bus resources are used to transmit more channel data, it is possible to achieve multiple channels without substantially changing the structure of the existing TV main control board. Channel stereo playback.

Based on the principle of the above application, an embodiment of the present application provides a data transmission method, which is applied to the main control board of a television. As shown in FIG. 5, it is a schematic structural diagram of a television main control board provided by an embodiment of this application.

Among them, the TV main control board 01 includes a main chip 10 and a slave device 20. Among them, the main chip 10 includes a decoder 101, a digital audio player (digital audio player, DAP) 102, and a re-encoder 103. The slave device 20 includes an audio coprocessor 201 and multiple power amplifier units 202 (exemplarily, as shown in the figure, the power amplifier unit 202 specifically includes a power amplifier unit 202a, a power amplifier unit 202b, a power amplifier unit 202c, a power amplifier unit 202d, and a power amplifier unit 202e five power amplifier units). Among them, the audio coprocessor 201 may specifically be an XMOS chip.

Among them, when the audio data needs to be played, the main chip 10 reads the audio data to be played and uses the decoder 101 to decode it to generate various channels of channel data to be played. Taking 7.1 channels as an example, through the decoding of the decoder 101, the top right channel TopR, the top left channel TopL, the surround left channel SL, the surround right channel SR, the front left channel L, and the front right channel can be obtained. R, Woofer of subwoofer channel, Conter of center channel, original audio data of 8 channels.

After the decoder 101 obtains each channel of original audio data that needs to be played, the digital audio player 102 performs AVI (audio video interleave, audio video interaction), DRC (dynamic range compress, dynamic range compression) and EQ on each channel of original audio data. (Equalizer, equalizer) Parameter setting and other processing to generate processed audio data of 8 channels.

Furthermore, the re-encoder 103 processes the processed 8-channel audio data according to the method provided in the embodiment of this application, using 6 I2S channels (specifically, 3 I2S channels in the figure, so Three I2S channels (including 6 I2S channels) send 8 channels of audio data to the slave device 20 side.

On the side of the slave device 20, after the audio coprocessor 201 receives the data sent by the three I2S channels, it obtains 8-channel data according to the audio data transmission method provided in the embodiment of the present application, and transmits it to each power amplifier unit 202. In order to drive each speaker to play the corresponding channel data.

It should be noted that FIG. 5 only exemplarily shows an application scenario of the audio data transmission method provided by the embodiment of the present application. In practical applications, those skilled in the art can also apply the embodiments of the present application to other scenarios, so as to solve the technical problems that can be solved by the embodiments of the present application and achieve the technical effects achieved by the embodiments of the present application.

Exemplarily, in some application scenarios, the digital audio player 102 may not be provided in the main chip 10, and after the decoder 101 decodes and obtains multi-channel data, it is directly provided by the re-encoder 103 according to the embodiment of the present application. The audio data transmission method re-encodes the channel data, and uses the I2S channel to send the re-encoded encoded data to the slave device 20 side. Alternatively, those skilled in the art may also apply the audio data transmission method provided in the embodiments of the present application to other devices other than the television to solve the same technical problem. In this regard, this application may not be restricted.

In some embodiments, as shown in FIG. 6, an embodiment of the present application provides an audio data transmission method, which specifically includes:

S301: Decode audio data to be processed to generate m channels of original channel data.

Exemplarily, in the main control board shown in FIG. 5, step S301 may be performed by the decoder 101.

S302: Preprocess the m channels of original channel data respectively to generate m channels of audio data.

Among them, the preprocessing of m channels of original channel data specifically includes: respectively modulating parameters such as AVI, DRC, and EQ of the m channels of original channel data to generate m channels of audio data.

Exemplarily, in the main control board shown in FIG. 5, step S302 may be executed by the digital audio player 102.

It should be noted that, in some application scenarios, when the audio data of m channels can be acquired in other ways, the contents of S301 and S302 may not be executed. In this regard, the embodiments of the present application may not be limited.

S303. Acquire audio data of m channels.

For example, in FIG. 5, the re-encoder 103 obtains audio data of m channels.

S304. Use n I2S channels to send audio data of m channels to the data receiving end. Among them, m>n.

In an implementation manner, as shown in FIG. 6, before performing S304, the method further includes: S305, comparing the size of m and n, and if m>n, then perform S304; otherwise, according to the prior art sending Send m channels of audio data in a way. In the embodiments of the present application, it is considered that when a device (such as a television) is playing and transmitting audio data, the number of channels included in different audio data is also different. Therefore, in this embodiment of the present application, before the audio data is sent, S305 can be used to determine whether the audio data needs to be re-encoded according to the content of S304. When re-encoding is not required, S304 is not performed to directly send audio data in the existing manner. Thereby improving the efficiency of audio data transmission.

In the embodiments of this application, it is considered that if the number of I2S channels can be decoupled from the number of channels of audio data to be processed, one I2S channel used in the prior art is not used to transmit only one channel of audio data. However, it is possible to use one I2S channel to transmit more than one channel data for data transmission, that is, use a limited number of I2S channels to transmit audio data with a large number of channels. Therefore, the channel data with a larger number of channels can be transmitted without increasing the number of I2S channels, so as to realize the playback of stereo surround sound.

In an implementation manner, it is considered in the embodiment of this application that currently when using the I2S channel to transmit audio data, it is limited by the data volume of the original audio data itself, and the audio data of one channel in the original audio data cannot be completely Occupy the transmission bit of an I2S channel, which will lead to a waste of transmission resources of the I2S channel.

Exemplarily, in the timing diagram of the I2S channel shown in Figure 7, SDATA only has data transmission in the two BCLK cycles after WS switching (the shaded part in the figure), and other data bits have no data transmission. This leads to a waste of transmission resources of the I2S channel.

Among them, for example, assume that the sampling frequency of the original audio data is 48KHz, and the sampling bit width is 16bit; the WS of the I2S channel used is 48KHz, BCLK=2*48KHz*32bit=3.072MHz. In other words, in a frame clock period, when WS=0, 32bit left channel data can be transmitted; when WS=1, 32bit right channel data can be transmitted. The sampling bit width of the original audio data is only 16 bits, which results in 16 bits of data being wasted in each frame clock cycle.

In view of the above situation, in the embodiments of the present application, it is conceived that the unused data bits can be used to increase the transmission efficiency of the I2S channel, so that more channel data can be transmitted using the limited I2S channel. Furthermore, in an implementation manner, S304 specifically includes:

S304a1, encode m channel sub-data to generate n channels of encoded data.

Wherein, each channel sub-data in the m channel sub-data includes channel data of one of the m channels in the audio sampling period.

S304a2, within the preset frame clock period, use n I2S channels to send n encoded data to the data receiving end through the n I2S channels.

Exemplarily, take 7.1 channel original audio data as an example. As shown in Figure 8, if the original audio data uses 16bit@48KHz (that is, the audio sampling frequency is 48KHz, and the sampling bit width is 16bit). According to the existing transmission method, 5 I2S channels are required for transmission.

In some embodiments, as shown in Figure 8, in one I2S channel of the first I2S channel (that is, WS is one of "0" or "1"), data of the Ch0 channel is transmitted; In the other I2S channel of the I2S channel (that is, when WS is the other value of "0" or "1"), the data of the Ch1 channel is transmitted; and so on, until it is in one I2S channel of the fifth I2S channel , Transmit Ch8 channel data, and the other I2S channel can be idle.

And if the WS of the I2S channel used at this time is 48KHz, BCLK=2*48KHz*32bit=3.072MHz. In other words, in one frame clock cycle, up to 32 bits of left channel data and 32 bits of right channel data can be transmitted.

Therefore, as shown in Figure 8, the channel sub-data of the six channels Ch0, Ch2, Ch3, Ch5, Ch6, and Ch8 in the same audio sampling period can be respectively placed in the six I2S channels included in the three I2S channels. High bit, split the channel sub-data of the remaining channels Ch1, Ch4, Ch7 and fill in the remaining bits of the six I2S channels. So as to achieve the effect of using three I2S channels to transmit 8-channel audio data without changing the clock frequency of the I2S channel.

In this embodiment of the application, S304a1 may specifically include: taking n channel sub-data of m channel sub-data as high-order data of n channels of coded data, and combining the data of the remaining channels in the m channel sub-data. The channel sub-data is supplemented after the n channel sub-data to generate n-channel coded data.

Wherein, supplementing the channel sub-data of the remaining channels in the m channel sub-data after the n channel sub-data specifically includes:

Split the channel sub-data of each channel in the remaining channels into at least one data segment; then, supplement at least one data segment after the n channel sub-data respectively.

In the embodiment of the present application, without increasing the number of I2S channels and without reducing the total amount of data of m channel sub-data, by changing the data structure of m channel sub-data, the m channel sub-data The data is sent out through one frame clock cycle of n I2S channels. In order to play more realistic stereo surround sound.

In an implementation manner, it is considered that in the process of splitting and combining data, it is relatively easy to make calculation errors, which will lead to data loss. For example, in Figure 8, Ch1, Ch4, and Ch7 are split into two 8-bit data segments, and the two 8-bit data segments need to be recombined on the data receiving side. In this process, it is easy to cause data damage. Therefore, in the embodiment of the present application, the n channel sub-data as high-order data of the n channels of coded data specifically include:

Channel sub-data of the n channels with the highest importance among the m channels.

In some embodiments, for example, in the 7.1 channel, the top right channel TopR, the top left channel TopL, the surround left channel SL, the surround right channel SR, the front left channel L, and the front right channel R are included. , Woofer, center channel Conter. Furthermore, the channel sub-data of the most important n channels may include the top right channel TopR, the top left channel TopL, the surround left channel SL, the surround right channel SR, the front left channel L, and the front right channel. Channel R, 6 channels. Furthermore, the sub-bass channel Woofer and the center channel Conter are supplemented with the channel sub-data of the upper 6 channels. The advantage of this is that when the clock signal is disturbed or abnormal, the collected main channel, surround sound, and sky sound will not be lost and wrong. Of course, the way of splitting and the way of accepting combinations are not fixed.

In an implementation manner, considering that in some application scenarios, the remaining bits of the I2S channel are too few, even after the channel sub-data is split, the remaining bits cannot be completely filled. For example, taking 32bit@48KHz 7.1 channel original audio data as an example, if a frame clock cycle is used to transmit at most 3 I2S channels of about 32bit channels for transmission. At this time, the 6 I2S channels included in the 3 I2S channels can only accommodate 6 channel data transmissions, and there are no remaining bits. At this time, in order to transmit m channel sub-data through n I2S channels, the method of increasing the serial clock frequency BCLK of the I2S channel or changing the sampling method of BCLK can be used to expand the frame clock period. The maximum amount of data that can be transferred.

In the embodiment of the present application, as shown in FIG. 9, before executing S304a1, the embodiment of the present application further includes:

S304a3. Increase the frequency of the serial clock of n I2S channels. Or, switch the sampling mode of the serial data of the n-channel I2S channel from the serial clock single-edge collection mode to the serial clock double-edge collection mode.

In some embodiments, as shown in FIG. 10, it is assumed that the original audio data is 12-channel audio data with a sampling frequency of 48KHz and a sampling bit width of 16bit (specifically including Ch0, Ch1, Ch2, Ch3, Ch4, Ch5, Ch6, Ch7, Ch8, Ch9, Ch10, Ch11). If using 3 I2S channels that transmit at most 16bit left and right channels in one frame clock period T for transmission. Then in one frame clock period T, only channel sub-data of exactly 6 channels can be transmitted (as shown in Fig. 10, Ch0, Ch1, Ch4, Ch5, Ch8, Ch10). At this time, in order to ensure that the channel sub-data of the 12 channels can be transmitted at the normal playback rate, the frequency of the serial clock BCLK of the n I2S channels can be increased, or the serial data SDATA of the n I2S channels can be increased The sampling mode is switched from the BCLK single-edge collection mode to the BCLK double-edge collection mode to increase the amount of data transmitted in one frame clock cycle.

In some embodiments, taking FIG. 11 as an example, it is assumed that before the frequency or sampling mode of the serial clock is increased, the sequence of the serial clock is as shown in the figure BCLK_1. The corresponding sampling method of SDATA is sampling on the rising edge of BCLK. At this time, the sequence of serial data is shown in SDATA_1 in the figure. At this time, within a frame clock period T, BCLK_1 has 8 rising edge triggers, corresponding to the transmission of 8bit data of SDATA_1.

Then, if the signal frequency of the serial clock BCLK is doubled, at this time, the sequence of the serial data is shown in SDATA_2 in the figure. At this time, within a frame clock period T, BCLK_2 has 16 rising edge triggers, corresponding to the transmission of SDATA_2 16bit data. It can be seen that in the same time, the amount of data that can be transmitted has doubled.

In addition, you can also increase the amount of transmitted data by changing the sampling method of the serial data SDATA. In some embodiments, as shown in FIG. 11, the frequency of the serial clock BCLK_3 at this time does not change compared to BCLK_1, but the sampling mode of the transmission data SDATA is changed from sampling on the rising edge of BCLK to sampling on both edges of BCLK. At this time, within one frame clock period T, 16bit data of SDATA_3 can also be correspondingly transmitted.

Continuing the example shown in Figure 10, when the frequency of the serial clock BCLK of the n-way I2S channel is doubled, or the sampling mode of the serial data SDATA is switched from the serial clock single-edge collection mode to the double-edge collection mode, At this time, the amount of data that can be transmitted within a period T'of the frame clock WS can be doubled (at this time, the time length of the period T and the period T'in the figure is the same). Take the channel I2S D0 in the figure as an example, before changing the frequency of BCLK or changing the sampling method of SDATA, the channel can transmit channel sub-data of the two channels Ch0 and Ch1 within one frame clock period T; and then, Then the channel sub-data of the four channels Ch0, Ch1, Ch2, and Ch3 can be transmitted.

In an implementation manner, as shown in FIG. 9, before executing S304a1 or executing S304a3, the method includes:

S304a4: Determine whether the data capacity included in the serial data can accommodate m channel sub-data in one frame clock cycle according to the current sampling mode of the serial clock BCLK and the serial data SDATA. If yes, execute S304a1 directly; if not, execute S304a3.

In another implementation manner, as shown in FIG. 9, in this embodiment of the present application, S304 may further include:

S304b, using multiple frame clock cycles of n I2S channels to send m channel sub-data to the data receiving end.

Exemplarily, for example, as shown in FIG. 12, when three I2S channels need to be used to transmit 12 channels of channel data, each I2S channel can be used to send two channels of sound in the first frame clock period T1. Channel data (as shown in the figure, in the T1 period, use the I2S D0 channel to send the channel sub-data of the two channels Ch0 and Ch1, use the I2S D1 channel to send the channel sub-data of the Ch4 and Ch5 channels, use The I2S D2 channel sends the channel sub-data of the two channels Ch8 and Ch9), and then the channel sub-data of the remaining channels is sent in the next frame clock period T2 (as shown in the figure, in the T2 period, the I2S D0 channel is used) Send the channel sub-data of the two channels Ch2 and Ch3, use the I2S D1 channel to send the channel sub-data of the Ch6 and Ch7 channels, and use the I2S D2 channel to send the channel sub-data of the Ch10 and Ch11 channels) .

In some embodiments, the embodiments of the present application also provide a data transmission method, as shown in FIG. 13, which specifically includes:

S401. Acquire audio data of m channels. Among them, 4<m≤8.

Regarding the specific execution steps and effects of S401, refer to the content of S303 in the foregoing embodiment.

S402: Encode the m channel sub-data to generate 4 channels of encoded data.

Regarding the specific execution steps and effects of S402, refer to the content of S304a1 in the foregoing embodiment.

S403: In the preset frame clock period, use 4 I2S channels to send 4 channels of encoded data to the data receiving end through 4 channels of I2S channels.

In some embodiments, the 4 channel sub-data in the m channel sub-data are respectively used as the high-order data of the 4 channels of coded data, and the channel sub-data of the remaining channels in the m channel sub-data are supplemented After 4 channels of sub-data, 4 channels of coded data are generated.

In some embodiments, the channel sub-data of the remaining channels in the m channel sub-data may be sequentially supplemented after different channel sub-data in the 4 channel sub-data.

Exemplarily, as shown in Figure 14, the channel sub-data of the four channels of L, C, Rs (or Rrs), and Lfh (or Lrh) are respectively placed in two I2S channels (in the figure, I2S D0 And the high bits of the four I2S channels of I2S D1). Then, the channel sub-data of the four channels of R, LFE, Ls (or Lrs), and Rfh are sequentially supplemented with the channel sub-data of the four channels of L, C, Rs (or Rrs), and Lfh (or Lrh). After the data.

For other specific execution steps and effects of S403, refer to the content of S304a2 in the foregoing embodiment.

In an implementation manner, after acquiring audio data of m channels in S401, the method further includes:

S404: Use multiple frame clock cycles of the 4 I2S channels to send m channel sub-data to the data receiving end.

Exemplarily, as shown in Figure 15, in the first frame clock cycle T1, through the four I2S channels included in the two I2S channels (in the figure, I2S D0 and I2S D1), L, R, Rs (Or Rrs) and Ls (or Lrs) channel sub-data of four channels are sent out. Then, in the second frame clock period T2, the remaining four channels C, LFR, Rs (or Rrs), and Ls (or Lrs) are sent out.

For other specific execution steps and effects of S404, please refer to the content of S304b in the foregoing embodiment.

The following describes the applications of Embodiment 1 and Embodiment 2 in combination with actual application scenarios:

As shown in Figure 16, when TVs and other devices need to play audio data. First, the first processing chip uses the decoder (Decoder) in it to decode the sound source data (equivalent to step S301 in the first embodiment above), and then uses the digital audio player (DAP) in the second processing chip. ) Preprocessing the decoded audio data of each channel (equivalent to step S302 in the first embodiment above). Wherein, in an implementation manner, the functions of the above-mentioned first processing chip and the second processing chip may also be implemented by one or more DSP chips.

After that, the preprocessed audio data needs to be sent to the power amplifier for playback. In one implementation manner, audio mixing (MIX) technology can be used to mix audio data of multiple channels into data of two channels, and then play it out through a device such as a power amplifier. But this will lose the quality of audio data. In another implementation manner, as shown in the figure, a third processing chip is used to process the audio data according to the above-mentioned first and second embodiments, and then use fewer I2S channels to achieve lossless transmission of audio data.

When the above-mentioned embodiments of this application are applied to televisions and other equipment, the following describes the application of the above-mentioned embodiments in conjunction with the working process of the equipment:

1. When the target audio data needs to be played, the upper layer opens the multi-channel APK application and communicates it to the middleware and Drive layer in a notified manner. Specifically, the protocol architecture of the device is shown in Figure 17.

2. After receiving the upper-level instruction, the middleware opens the relevant code of the multi-channel.

3. The driver layer will enumerate the Audio devices connected to the underlying hardware, such as enumerating to a USB device, and then turn on the USB.

4. Audio device inputs audio files, and the source data is at the bottom layer after the chip decodes the decoder.

5. The driver layer requests the middle layer to enumerate the USB device, whether the data needs to be sent.

6. The middleware requests the upper layer to receive the AUDIO data and whether to send it.

7. The upper layer responds to notify the data to be sent.

8. The response instruction informs the middle layer, and the middle layer sends the processing mode of multi-channel data (Dolby ATMOS, DRC, etc.) to the driver layer to perform data post-processing on the bottom layer.

9. Audio effect post-processing, the driver layer will receive the intermediate layer to compress the data, pack it into a USB data format for processing, and transmit it to the power amplifier through the USB channel after processing.

10. If it is enumerated to the I2S device, after the middle layer receives the sending instruction, the middle layer sends the multi-channel data (Dolby ATMOS, DRC, etc.) processing method and the audio data transmission method provided in the above-mentioned embodiment of this application Give the driver layer to the bottom layer to split and combine the data according to the audio data transmission method provided in the above-mentioned embodiments of the application, and then directly transmit it through I2S.

11. The 16bit 8ch audio data is split and arranged in the Drive layer, and the SW bass and center are split into SwH 8bit, SwL 8Bit, CH8bit, CL8bit.

In the above process, it can be seen that in an implementation manner, in order not to redesign the main control board, the USB interface can be used to realize the transmission of audio data. But this method needs to pack the audio data according to the USB interface protocol and then transmit it. However, this method has a relatively large delay and is not suitable for the transmission process of audio data that is played synchronously. However, the audio data transmission method provided by the embodiment of the present application has beneficial effects such as saving system cost and reducing delay time.

In some embodiments, the embodiments of the present application also provide an audio data transmission method, specifically, as shown in FIG. 18. The method includes:

S501: Receive transmission data sent by n I2S channels.

In an implementation manner, after the audio data transmission method provided in Embodiment 1 or Embodiment 2 is executed first, the content included in S501 is specifically used to execute after S304.

Exemplarily, in the slave device 20 shown in FIG. 5, the audio coprocessor 201 executes the steps of S501 and the following S502.

S502: Convert the transmission data sent by the n channels of I2S channels into m channels of audio data. Among them, m>n.

In some embodiments, in order to enable the audio coprocessor 201 to convert the transmission data sent by n channels of I2S channels into m channels of audio data, before performing S502, the method further includes:

S503: Receive the encoding information sent by the data sending end. In order to separate the audio data of m channels from the transmission data sent by n I2S channels according to the decoding method corresponding to the encoded information.

In an implementation manner, S501 specifically includes: receiving n channels of encoded data sent by n channels of I2S channels within a preset frame clock period. S502 specifically includes: decoding n channels of coded data to generate m channel sub-data.

Among them, in an implementation manner, as shown in FIG. 19, S502 specifically includes:

S502a1. Obtain n channel sub-data in sequence from the high-order data of the n channels of encoded data.

S502a2, from the remaining data of the n channels of coded data, obtain channel sub-data of the m channel sub-data except for the n channel sub-data.

Among them, the n channel sub-data specifically include: channel sub-data of the n channels with the highest importance among the m channels.

In some embodiments, the above S502 can be used as the reverse decoding process of the steps S304a1, S304a2, etc. in the first embodiment, and the technical problems solved and the beneficial effects achieved are the same as those in the first embodiment. In this regard, I will not repeat it.

In another implementation manner, as shown in FIG. 19, S502 specifically includes:

S502b1, receiving transmission data of multiple frame clock cycles sent by n I2S channels;

S502b2. Convert the transmission data sent by n channels of I2S channels into m channels of audio data, which specifically includes:

S502b3. Generate m channel sub-data by using transmission data of multiple frame clock cycles.

In some embodiments, the above S502 can be used as the reverse process of the steps S304a1, S304a2, S304b, etc. in the first embodiment, and the technical problems solved and the beneficial effects achieved are the same as those in the first embodiment. In this regard, I will not repeat it.

In one implementation, considering that when n I2S channels have independent clock signals (including clocks such as BCLK, WS, MCLK, etc.), if the data transmitted by n I2S channels is received, the encoded data of n Decoding to generate m channel sub-data will occupy more system resources, thereby affecting the normal operation of the device.

In the embodiment of the present application, if n I2S channels have independent clock signals, then n channels of encoded data are decoded to generate m channel sub-data, which specifically includes:

The data received from n I2S channels in the audio sampling period is stored in the buffer. After the audio sampling period ends, the encoded data in the buffer is decoded to generate m channel sub-data.

In some embodiments, if n I2S channels use a common clock signal, in order to increase the utilization rate of the CPU, it is used to decode the received data while receiving data from the n I2S channels. Specifically, decoding the received data includes: splitting and combining the received data to generate m channel sub-data.

The following describes the audio data transmission method provided by the above embodiments in combination with examples:

In some embodiments, the internal I2S architecture of different chip solution systems is different. There are four groups of signals MCLK, BCLK, WS, and SDATA in the I2S protocol, and MCLK is the main clock signal. BCLK clock signal, WS channel selection, SDATA is channel data. Different chip architectures have different forms of I2S transmission.

In one approach, n I2S channels may use the same clock signal. At this time, when receiving the transmission data sent by the n-way I2S channel, the form of receiving and dismantling is adopted.

In some embodiments, different chip I2S channel output channels are different, such as MSD858 as an example, the core end will support 2 I2S channel output, but the 2 I2S channels share one MCLK, BCLK, WS, which is so-called Single-channel CLK collection, a single-channel CLK is sent from the movement end to the external audio coprocessor 201, and the audio co-processor 201 collects the aforementioned movement end (specifically, the main chip 10 shown in Figure 5) according to the single-channel CLK. The audio data of m channels sent out in the form of encoding arrangement. Among them, the audio coprocessor 201 may specifically be an XMOS chip.

In some embodiments, taking 16bit@48HKZ---24bit@48HKz as an example, suppose there are 8 channels of audio data to be transmitted in 3 I2S channels. The following describes the working process of the XMOS chip as the audio coprocessor 201:

1. After the data is sent, it reaches the XMOS end, and the XMOS chip starts to rearrange the data after receiving the data.

2. Since the 3 I2S channels are sent to the receiving end at the same time, the XMOS platform driver software is disassembled according to the coding information provided by the movement end.

3. As shown in Figure 20, intercept the 16bit data of the front left and right channels from the 3 I2S channels (ie intercept the first 16bit data of the two I2S channels included in one I2S channel) to restore Ch0, Ch1, Ch2, and Ch3 , Ch4, Ch5 channels correspond to 16bit data respectively. Put them into the 6 channels included in the first 3 I2S channels of the XMOS chip.

4. As shown in Figure 20, combine the last 8bit data received by the two I2S channels in the I2S_0 channel into Ch6 data, and put them into one channel included in the fourth I2S channel of XMOS.

5. As shown in Figure 20, combine the last 8bit data received by the two I2S channels in the I2S_1 channel into the Ch7 data, and put it into the other channel included in the fourth I2S channel of XMOS.

For another example, taking 16bit@48HKZ---16bit@96HKz as an example, suppose there are 12 channels of audio data to be transmitted in 3 I2S channels. The following describes the working process of the XMOS chip as the audio coprocessor 201:

First, in order to increase the sampling frequency to 96KHz, one way is to increase the frequency of BCLK, and the other way is to keep the original sampling frequency unchanged, and use the double-edge sampling of BCLK to collect data. specific:

2. Since the data of the 3 I2S channels are sent to the receiving end at the same time, the XMOS platform driver software is disassembled according to the multi-channel data encoding sequence provided by the movement end.

3. As shown in Figure 21, disassemble the I2S channel data on each channel through the clock waveform provided by the data transmitter. The XMOS end also uses double-edge sampling to extract the I2S_0 data into 4ch16bit data and store them in the output I2S_a and I2S_b respectively.

4. As shown in Figure 21, double-edge sampling of the data on I2S_1 is also performed to extract 4ch 16bit data and put them into the output I2S_c and I2S_d respectively.

5. As shown in Figure 21, double-edge sampling of the data on I2S2 is also performed to extract 4ch 16bit data and put them into the output I2S_e and I2S_f respectively.

XMOS stores the received and split data in the I2S channel for output (specifically including I2S_a, I2S_b, I2S_c, I2S_d, I2S_e, I2S_f in Figure 21), it has a clock signal in itself, and generates a 48KHZ clock signal by itself. Under this clock signal, the multi-channel data is transmitted to the back-end power amplifier chip for sound conversion.

For another example, the internal I2S architecture of different chip scheme systems is different. There are four groups of signals MCLK, BCLK, WS, and SDATA in the I2S protocol, of which MCLK is the main clock signal. BCLK clock signal, WS channel selection, SDATA is channel data. Different chip architectures have different forms of I2S transmission. Take Nova 72671 and its follow-up products as an example below. The movement chip supports 3 channels of I2S output. If 3 channels of I2S share one CLK, there will be an error in the data transmission process. Once the I2S shared CLK error, it will cause 3 channels of I2S data transmission to receive data errors. When abnormal sound occurs, the source of CLK error: software delay, peripheral signal interference, hardware circuit, etc.

For example, when the XMOS chip receives and splits the 24-bit data at the data sending end, if clk jitters abnormally, it will cause data errors. If the CLK is jittered in the lower 16 bits, which causes the number of bits to be read from 0 to 1, and then XMOS splits the 24bit data from 16bit, and the data is abnormal. The data is not the original multi-channel data and there is a total of CLK. At the same time, 3 channels of I2S data are affected, and abnormal noise occurs for multi-channels. Therefore, this kind of architecture has drawbacks, but its advantages are that it saves the cost of the chip.

In some embodiments, the internal structure of the 3-channel I2S chip output by the NT72673 used in this application is that each group of I2S channels has a separate MCLK, WS, BCK, SDATA, but more importantly, it is necessary to ensure the MCLK of the 3-channel I2S channel Synchronize.

(1) One method is to wait for transmission, which is to wait for the 3 I2S channel data to be processed at the same time.

(2) Initialize to send a new sound, collect the first bit of the 3 channels of initialized audio data, and use the first valid signal as the MCLK of the waiting tone.

Since the CLKs of the 3 I2S channels are shared, the CLKs of the 3 I2S channels are used to fetch the sending data respectively. This greatly reduces the data error caused by a clk abnormality.

In the following, in conjunction with examples, the process of storing the received data in the buffer in the embodiment of the present application, and encoding the encoded data in the buffer after the end of the sampling period is introduced:

Take 16bit@48HKZ---24bit@48HKz as an example:

1. The data sending end (which can be a SOC chip specifically) transmits all the 24bit data sent by each channel of the 3 I2S channels to the XMOS chip. The XMOS chip does not receive and disassemble, and it buffers the 24bit data in the buffer.

2. The data sending end provides the XMOS chip with an encoding arrangement of 8ch data at the data sending end into 6ch data. Equivalent to the description in S503, the XMOS chip receives the encoded information sent by the data sender.

3. After the three sets of data are buffered, because there is a clock signal inside the XMOS terminal, the first bit of the three data channels is collected as a valid MCLK signal, and the first 16 bits of the 24bit data are collected. Take Figure 20 as an example, combine the collected 16-bit effective data to get Ch0, Ch1, Ch2, Ch3, Ch4, Ch5, 6-channel audio data.

4. As shown in Figure 20, the first valid data of 24bit of the three I2S channels is collected as a valid MCLK signal, the last 8bit of the 24bit data is collected, and the data is recombined to obtain Ch6, Ch7, 2 channels Audio data.

5. The restored original multi-channel 5.1.2 data is sent to the power amplifier through 4 I2S channels (specifically, I2S_a, I2S_b, I2S_c, I2S_d in the figure) to achieve the purpose of multi-channel sound effects.

Taking 16bit@48HKZ---16bit@96HKz as an example, the sampling frequency is increased to 96KHz by increasing the frequency of BCLK or adopting double-edge sampling. specific:

1. The data sending end (specifically, it can be a SOC chip) transmits all the data sent by each channel of the 3 I2S channels to the XMOS chip. The XMOS chip does not receive and disassemble, but it buffers the data in the buffer.

2. The data sending end provides this encoding arrangement and double-edge sampling to the XMOS chip. Equivalent to the description in S503, the XMOS chip receives the encoded information sent by the data sender.

3. The XMOS chip uses the first valid data of 3 channels of I2S as the reference MCLK, and the sampling frequency is set to 48KHZ.

4. As shown in Figure 21, put the data transmitted from the three I2S channels into the stack at the same time, the sampling frequency is set to 48KHz, and the double-edge sampling method is adopted. Sampling out Ch0, Ch1...Ch11 respectively, the 16bit data corresponding to each channel in a total of 12 channels.

5. This 12ch 16bit data is distributed to 6 I2S channels (specifically, I2S_a, I2S_b, I2S_c, I2S_d in the figure) according to the original data distribution format.

6. The XMOS chip generates a wait tone spontaneously and adjusts the clock synchronization of the 6 I2S channels. After C is synchronized, the XMOS chip sends it to the power amplifier at the same time through 6 I2S channels.

In some embodiments, this application provides an audio data transmission device for executing the audio data transmission methods provided in the first and second embodiments of this application. As shown in FIG. 22, the audio data provided in this embodiment A possible structure diagram of the data transmission device 60. Wherein, the device includes: an acquiring unit 601 and a sending unit 602.

The acquiring unit 601 is configured to acquire audio data of m channels.

The sending unit 602 is configured to use n I2S channels to send m channels of audio data to the data receiving end; where m>n.

In some embodiments, the sending unit 602 specifically includes an encoding subunit 6021 and a sending subunit 6022. among them:

The encoding subunit 6021 is used to encode m channel sub-data to generate n channels of encoded data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels in the Channel data in the audio sampling period;

The sending subunit 6022 is configured to use n I2S channels to send n encoded data to the data receiving end through n I2S channels within a preset frame clock period.

In some embodiments, the sending subunit 6022 is specifically configured to use the n channel sub-data in the m channel sub-data as the high-order data of the n channels of coded data, and combine the remaining m channel sub-data The channel sub-data of the channel is supplemented after the n channel sub-data to generate n-channel coded data.

In some embodiments, the n channel sub-data specifically includes: channel sub-data of the n channels with the highest importance among the m channels.

In some embodiments, the audio data transmission device 60 further includes a sampling frequency adjustment unit 603.

Among them, the sampling frequency adjustment unit 603 is configured to increase the frequency of the serial clock of the n I2S channels before the sending unit 602 uses n I2S channels to send the n channels of encoded data to the data receiving end; or The sampling mode of the serial data of the channel is switched from the serial clock single-edge collection mode to the serial clock double-edge collection mode.

In some embodiments, the sending subunit 6022 is specifically configured to use multiple frame clock cycles of n I2S channels to send m channel sub-data to the data receiving end; wherein, each sound channel in the m channel sub-data The channel data respectively include channel data of one of the m channels in the audio sampling period.

The embodiment of the present application can divide the audio data transmission device 60 into functional modules or functional units according to the above method examples. For example, each functional module or functional unit can be divided corresponding to each function, or two or more functions can be integrated. In a processing module. The above-mentioned integrated modules can be implemented in the form of hardware, or in the form of software functional modules or functional units. Among them, the division of modules or units in the embodiments of the present application is illustrative, and is only a logical function division, and there may be other division methods in actual implementation.

In the case of using an integrated unit, Fig. 23 shows a possible structural schematic diagram of the audio data transmission device involved in the foregoing embodiment. The audio data transmission device 70 includes a processing module 701, a communication module 702, and a storage module 703. The processing module 701 is used to control and manage the actions of the audio data transmission device 70. For example, the processing module 701 is used to support the audio data transmission device 70 to execute the processes S301-S304 in FIG. 6 or FIG. 9. The communication module 702 is used to support the communication between the audio data transmission device 70 and other entities. The storage module 703 is used to store the program code and data of the audio data transmission device.

The processing module 701 may be a processor or a controller, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (digital signal processor, DSP), and an application-specific integrated circuit (application-specific integrated circuit). integrated circuit, ASIC), field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in conjunction with the disclosure of this application. The processor may also be a combination of computing functions, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on. The communication module 702 may be a transceiver, a transceiver circuit, or a communication interface. The storage module 703 may be a memory.

When the processing module 701 is the processor shown in FIG. 24, the communication module 702 is the transceiver shown in FIG. 24, and the storage module 703 is the memory shown in FIG. 24, the audio data transmission device involved in the embodiment of the present application may be the following audio Data transmission device 80.

Referring to FIG. 24, the audio data transmission device 80 includes a processor 801, a transceiver 802, a memory 803, and a bus 804.

Among them, the processor 801, the transceiver 802, and the memory 803 are connected to each other through a bus 804; the bus 804 may be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus Wait. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

The processor 801 may be a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an Application-Specific Integrated Circuit (ASIC), or one or more programs for controlling the execution of the program of this application. integrated circuit.

The memory 803 can be a read-only memory (Read-Only Memory, ROM) or other types of static storage devices that can store static information and instructions, random access memory (Random Access Memory, RAM), or other types that can store information and instructions The dynamic storage device can also be Electrically Erasable Programmable Read-only Memory (EEPROM), CD-ROM (Compact Disc Read-Only Memory, CD-ROM) or other optical disk storage, optical disc storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program codes in the form of instructions or data structures and can be used by a computer Any other media accessed, but not limited to this. The memory can exist independently and is connected to the processor through a bus. The memory can also be integrated with the processor.

The memory 802 is used to store application program codes for executing the solutions of the present application, and the processor 801 controls the execution. The transceiver 802 is used to receive content input from an external device, and the processor 601 is used to execute application program codes stored in the memory 803, so as to implement an audio data transmission method provided in Embodiment 1 and Embodiment 2 of the present application.

In some embodiments, this application provides an audio data transmission device for executing the audio data transmission method provided in the third embodiment of this application. As shown in FIG. 25, this is the audio data transmission device provided in this embodiment of the application. A possible structure diagram of 90. Wherein, the device includes: a receiving unit 901 and a conversion unit 902.

The receiving unit 901 is configured to receive transmission data sent by n I2S channels.

The conversion unit 902 is configured to convert the transmission data sent by n I2S channels into m channels of audio data; where m>n.

In some embodiments, the receiving unit 901 is specifically configured to receive n channels of encoded data sent by n channels of I2S channels within a preset frame clock period.

The conversion unit 902 is specifically configured to decode n channels of coded data to generate m channel sub-data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels Channel data in the audio sampling period.

In some embodiments, the conversion unit 902 is specifically configured to sequentially obtain n channel sub-data from the high-order data of the n-channel coded data; from the remaining data of the n-channel coded data, obtain the m channel sub-data Channel sub data except for n channel sub data.

In some embodiments, the receiving unit 901 is specifically configured to receive transmission data of multiple frame clock cycles sent by n I2S channels.

The conversion unit 902 is specifically configured to generate m channel sub-data by using transmission data of multiple frame clock cycles; wherein, each channel sub-data in the m channel sub-data includes one sound of the m channels. Channel data in the audio sampling period.

In some embodiments, the conversion unit 902 is specifically further configured to store the data received from the n I2S channels in the buffer in the buffer during the audio sampling period if the n I2S channels have independent clock signals. After the end, decode the encoded data in the buffer to generate m channel sub-data.

The embodiment of the present application may divide the audio data transmission device 90 into functional modules or functional units according to the foregoing method examples. For example, each functional module or functional unit may be divided corresponding to each function, or two or more functions may be integrated In a processing module. The above-mentioned integrated modules can be implemented in the form of hardware, or in the form of software functional modules or functional units. Among them, the division of modules or units in the embodiments of the present application is illustrative, and is only a logical function division, and there may be other division methods in actual implementation.

In the case of using an integrated unit, FIG. 26 shows a possible structural schematic diagram of the audio data transmission device involved in the foregoing embodiment. The audio data transmission device 100 includes a processing module 1001, a communication module 1002, and a storage module 1003. The processing module 1001 is used to control and manage the actions of the audio data transmission device 100. For example, the processing module 1001 is used to support the audio data transmission device 100 to execute the processes S501-S503 in FIG. 18 or FIG. 19. The communication module 1002 is used to support communication between the audio data transmission device 100 and other entities. The storage module 1003 is used to store the program code and data of the audio data transmission device.

The processing module 1001 may be a processor or a controller, for example, a central processing unit (CPU), a general-purpose processor, a digital signal processor (digital signal processor, DSP), and an application-specific integrated circuit (application-specific integrated circuit). integrated circuit, ASIC), field programmable gate array (FPGA) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logical blocks, modules and circuits described in conjunction with the disclosure of this application. The processor may also be a combination of computing functions, for example, a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and so on. The communication module 1002 may be a transceiver, a transceiver circuit, or a communication interface. The storage module 1003 may be a memory.

When the processing module 1001 is the processor shown in FIG. 27, the communication module 1002 is the transceiver shown in FIG. 27, and the storage module 1003 is the memory shown in FIG. 27, the audio data transmission device involved in the embodiment of the present application may be the following audio Data transmission device 110.

Referring to FIG. 27, the audio data transmission device 110 includes a processor 1101, a transceiver 1102, a memory 1103, and a bus 1104.

Among them, the processor 1101, the transceiver 1102, and the memory 1103 are connected to each other through a bus 1104; the bus 1104 may be a peripheral component interconnect standard (PCI) bus or an extended industry standard architecture (EISA) bus Wait. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

The processor 1101 may be a general-purpose central processing unit (Central Processing Unit, CPU), a microprocessor, an Application-Specific Integrated Circuit (ASIC), or one or more for controlling the execution of the program of this application integrated circuit.

The memory 1103 may be a read-only memory (Read-Only Memory, ROM) or other types of static storage devices that can store static information and instructions, random access memory (Random Access Memory, RAM), or other types that can store information and instructions The dynamic storage device can also be electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-only Memory, EEPROM), CD-ROM (Compact Disc Read-Only Memory, CD-ROM) or other optical storage (Including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or can be used to carry or store desired program codes in the form of instructions or data structures and can be used by a computer Any other media accessed, but not limited to this. The memory can exist independently and is connected to the processor through a bus. The memory can also be integrated with the processor.

Among them, the memory 1103 is used to store application program codes for executing the solutions of the present application, and the processor 1101 controls the execution. The transceiver 1102 is used to receive content input from an external device, and the processor 1101 is used to execute application program codes stored in the memory 1103, so as to implement the audio data transmission method provided in the third embodiment of the present application.

In some embodiments, an embodiment of the present application further provides a television, including the audio data transmission device provided in the above-mentioned embodiment.

FIG. 28 is a schematic diagram of a display device provided in Embodiment 1 of the present application. Referring to FIG. 28, the present application also provides a display device, which at least includes: a display screen 91 configured to present image data; and a speaker 92 configured to reproduce sound data .

In some implementation examples, the display device may further include: a backlight assembly 94 located below the display screen 91. Usually some optical components are used to supply sufficient brightness and uniformly distributed light sources so that the display screen 91 can display images normally. In some related technologies, the backlight assembly may include an LED light bar or a light panel that automatically emits light.

In some embodiments, the display device may further include: a back plate 95. Usually, the back plate 95 is stamped to form some convex structures, and components such as speakers 92 are fixed on the convex structures by screws or hooks.

In some embodiments, the display device may further include: a rear case 98, which is covered on the back of the display screen 91 to hide the backlight assembly 94, the speaker 92 and other display device components, which has a beautiful effect.

In some embodiments, the display device may further include: a main board 96 and a power supply board 97, which can be arranged as two boards independently, or they can be combined on one board.

In some embodiments, the display device further includes a remote control 93.

FIG. 29 is a block diagram of the hardware configuration of the display device provided in Embodiment 1 of the present application. As shown in 29, the display device 200 may include a tuner and demodulator 220, a communicator 230, a detector 240, an external device interface 250, a controller 210, a memory 290, a user input interface, a video processor 260-1, and audio processing 260-2, display screen 280, audio input interface 272, power supply.

The tuner and demodulator 220, which receives broadcast and television signals through wired or wireless means, can perform modulation and demodulation processing such as amplification, mixing and resonance, and is used to demodulate the television channel selected by the user from multiple wireless or cable broadcast and television signals The audio and video signals carried in the frequency, and additional information (such as EPG data signals).

The tuner and demodulator 220 can be selected by the user and controlled by the controller 210 to respond to the TV channel frequency selected by the user and the TV signal carried by the frequency.

The tuner and demodulator 220 can receive signals in many ways according to different TV signal broadcasting systems, such as terrestrial broadcasting, cable broadcasting, satellite broadcasting, or Internet broadcasting; and according to different modulation types, it can be digital modulation or alternatively. Analog modulation method; and according to different types of received TV signals, analog and digital signals can be demodulated.

In some other exemplary embodiments, the tuner demodulator 220 may also be in an external device, such as an external set-top box. In this way, the set-top box outputs TV audio and video signals through modulation and demodulation, and inputs them to the display device 200 through the input/output interface 250.

The communicator 230 is a component for communicating with external devices or external servers according to various communication protocol types. For example, the communicator 230 may include a WIFI module 231, a Bluetooth communication protocol module 232, a wired Ethernet communication protocol module 233 and other network communication protocol modules or near field communication protocol modules.

The display device 200 may establish a control signal and a data signal connection with an external control device or content providing device through the communicator 230. For example, the communicator may receive the control signal of the remote controller 100 according to the control of the controller.

The detector 240 is a component of the display device 200 for collecting signals from the external environment or interacting with the outside. The detector 240 may include a light receiver 242, a sensor used to collect the intensity of ambient light, which can adaptively display parameter changes by collecting ambient light, etc.; it may also include an image collector 241, such as a camera, a camera, etc., which can be used to collect external Environmental scenes, as well as gestures used to collect user attributes or interact with users, can adaptively change display parameters, and can also recognize user gestures to achieve the function of interaction with users.

In some other exemplary embodiments, the detector 240 may further include a temperature sensor. For example, by sensing the ambient temperature, the display device 200 may adaptively adjust the display color temperature of the image.

In some embodiments, when the temperature is relatively high, the color temperature of the display device 200 can be adjusted to be relatively cool; when the temperature is relatively low, the color temperature of the display device 200 can be adjusted to be relatively warm.

In some other exemplary embodiments, the detector 240 may also include a sound collector, such as a microphone, which may be used to receive the user's voice, including the voice signal of the user's control instruction for controlling the display device 200, or to collect environmental sound for Recognizing the environmental scene type, the display device 200 can adapt to the environmental noise.

The external device interface 250 provides a component for the controller 210 to control data transmission between the display device 200 and other external devices. The external device interface can be connected to external devices such as set-top boxes, game devices, notebook computers, etc. in a wired/wireless manner, and can receive external devices such as video signals (such as moving images), audio signals (such as music), and additional information (such as EPG). ) And other data.

Among them, the external device interface 250 may include: a high-definition multimedia interface (HDMI) terminal 251, a composite video blanking synchronization (CVBS) terminal 252, an analog or digital component terminal 253, a universal serial bus (USB) terminal 254, red, green, and blue ( RGB) terminal (not shown in the figure) and any one or more.

The controller 210 controls the work of the display device 200 and responds to user operations by running various software control programs (such as an operating system and various application programs) stored on the memory 290.

As shown in FIG. 29, the controller 210 includes a random access memory RAM 213, a read only memory ROM 214, a graphics processor 216, a CPU processor 212, a communication interface 218, and a communication bus. Among them, RAM213 and ROM214, graphics processor 216, CPU processor 212, and communication interface 218 are connected by a bus.

ROM213, used to store various system startup instructions. For example, when the power-on signal is received, the power of the display device 200 starts to start, and the CPU processor 212 runs the system start-up instruction in the ROM, and copies the operating system stored in the memory 290 to the RAM 214 to start the start-up operating system. After the operating system is started up, the CPU processor 212 copies various application programs in the memory 290 to the RAM 214, and then starts to run and start various application programs.

The graphics processor 216 is used to generate various graphics objects, such as icons, operation menus, and user input instructions to display graphics. Including an arithmetic unit, which performs operations by receiving various interactive commands input by the user, and displays various objects according to display attributes. As well as including a renderer, various objects obtained based on the arithmetic unit are generated, and the rendering result is displayed on the display screen 280.

The CPU processor 212 is configured to execute operating system and application program instructions stored in the memory 290. And according to receiving various interactive instructions input from the outside, to execute various applications, data and content, so as to finally display and play various audio and video content.

In some exemplary embodiments, the CPU processor 212 may include multiple processors. The multiple processors may include one main processor and multiple or one sub-processors. The main processor is used to perform some operations of the display device 200 in the pre-power-on mode, and/or to display images in the normal mode. Multiple or one sub-processor, used to perform an operation in the standby mode and other states.

The communication interface may include the first interface 218-1 to the nth interface 218-n. These interfaces may be network interfaces connected to external devices via a network.

The controller 210 may control the overall operation of the display device 200. For example, in response to receiving a user command for selecting a UI object to be displayed on the display screen 280, the controller 210 may perform an operation related to the object selected by the user command.

Wherein, the object may be any one of the selectable objects, such as a hyperlink or an icon. Operations related to the selected object, for example: display operations connected to hyperlink pages, documents, images, etc., or perform operations corresponding to the icon. The user command for selecting the UI object may be a command input through various input devices (for example, a mouse, a keyboard, a touch pad, etc.) connected to the display device 200 or a voice command corresponding to the voice spoken by the user.

The memory 290 includes storing various software modules for driving and controlling the display device 200. For example, various software modules stored in the memory 290 include: a basic module, a detection module, a communication module, a display control module, a browser module, and various service modules.

Among them, the basic module is the underlying software module used for signal communication between various hardware in the display device 200 and sending processing and control signals to the upper module. The detection module is a management module used to collect various information from various sensors or user input interfaces, and perform digital-to-analog conversion and analysis management.

For example: the voice recognition module includes a voice analysis module and a voice command database module. The display control module is a module for controlling the display screen 280 to display image content, and can be used to play information such as multimedia image content and UI interfaces. The communication module is a module used for control and data communication with external devices. The browser module is a module used to perform data communication between browsing servers. The service module is a module used to provide various services and various applications.

At the same time, the memory 290 is also used to store and receive external data and user data, images of various items in various user interfaces, and visual effect diagrams of focus objects.

The user input interface 276 is used to send a user's input signal to the controller 210, or to transmit a signal output from the controller to the user. In some embodiments, the control device (for example, a mobile terminal or a remote control) can send input signals input by the user, such as a power switch signal, a channel selection signal, and a volume adjustment signal, to the user input interface, and then the user input interface 276 forwards it to the user input interface. Controller; or, the control device may receive output signals such as audio, video or data output from the user input interface processed by the controller, and display the received output signal or output the received output signal as audio or vibration.

In some embodiments, the user may input a user command on a graphical user interface (GUI) displayed on the display screen 280, and the user input interface receives the user input command through the graphical user interface (GUI). Alternatively, the user can input a user command by inputting a specific sound or gesture, and the user input interface recognizes the sound or gesture through the sensor to receive the user input command.

The video processor 260-1 is used to receive video signals, and perform video data processing such as decompression, decoding, scaling, noise reduction, frame rate conversion, resolution conversion, and image synthesis according to the standard codec protocol of the input signal. The video signal directly displayed or played on the display screen 280.

In some embodiments, the video processor 260-1 includes a demultiplexing module, a video decoding module, an image synthesis module, a frame rate conversion module, a display formatting module, and the like.

Among them, the demultiplexing module is used to demultiplex the input audio and video data stream. For example, if MPEG-2 is input, the demultiplexing module will demultiplex into a video signal and an audio signal.

The video decoding module is used to process the demultiplexed video signal, including decoding and scaling.

An image synthesis module, such as an image synthesizer, is used to superimpose and mix the GUI signal generated by the graphics generator with the zoomed video image according to user input or itself to generate a displayable image signal.

Frame rate conversion module, used to convert the frame rate of the input video, such as converting the frame rate of the input 24Hz, 25Hz, 30Hz, 60Hz video to the frame rate of 60Hz, 120Hz or 240Hz, where the input frame rate can be compared with the source The video stream is related, and the output frame rate can be related to the update rate of the display. The input has a usual format, such as frame insertion.

The display formatting module is used to change the signal output by the frame rate conversion module into a signal that conforms to a display format such as a display, such as format conversion of the signal output by the frame rate conversion module to output RGB data signals.

The display screen 280 is used to receive image signals input from the video processor 260-1, to display video content and images, and a menu control interface. The display screen 280 includes a display screen component for presenting a picture and a driving component for driving image display. The displayed video content can be from the video in the broadcast signal received by the tuner and demodulator 220, or from the video content input by the communicator or the external device interface. The display screen 280 simultaneously displays a user manipulation interface UI generated in the display device 200 and used to control the display device 200.

And, depending on the type of the display screen 280, a driving component for driving the display is also included. Alternatively, if the display screen 280 is a projection display, it may also include a projection device and a projection screen.

The audio processor 260-2 is used to receive audio signals, and perform decompression and decoding according to the standard codec protocol of the input signal, as well as audio data processing such as noise reduction, digital-to-analog conversion, and amplification processing, and the result can be in the speaker 272 The audio signal to be played.

The audio output interface 270 is used to receive the audio signal output by the audio processor 260-2 under the control of the controller 210. The audio output interface may include a speaker 272 or output to an external audio output terminal 274 of a generator of an external device, such as : External audio terminal or headphone output terminal, etc.

In some other exemplary embodiments, the video processor 260-1 may include one or more chips. The audio processor 260-2 may also include one or more chips.

And, in some other exemplary embodiments, the video processor 260-1 and the audio processor 260-2 may be separate chips, or they may be integrated with the controller 210 in one or more chips.

The power supply 275 is used to provide power supply support for the display device 200 with power input from an external power supply under the control of the controller 210. The power supply 275 may include a built-in power supply circuit installed inside the display device 200, or may be a power supply installed outside the display device 200, such as a power interface for providing an external power supply in the display device 200.

In some embodiments, the present application provides a display device, including:

The display screen is configured to present an image screen;

The speaker is configured to reproduce sound;

The controller is configured to obtain audio data of m channels and send the audio data of m channels, where m>n.

In some embodiments, the controller is further configured to encode m channels of channel sub-data to generate n channels of encoded data; wherein each channel sub-data in the m channels of channel sub-data includes Channel data of one of the m channels in the audio sampling period.

In some embodiments, the controller is further configured to use n channel sub-data in the m channels of channel sub-data as high-order data of the n channels of encoded data, and set the m channel sub-data to The channel sub-data of the remaining channels is supplemented after the n-channel sub-data to generate the n-channel coded data.

In some embodiments, the display device further includes n I2S channels, and the controller is further configured to increase the frequency of the serial clock of the n I2S channels.

In some embodiments, the controller is further configured to switch the sampling mode of the serial data of the n I2S channels from the serial clock single-edge collection mode to the serial clock double-edge collection mode.

In some embodiments, the controller is further configured to use multiple frame clock cycles of n I2S channels to send m channel sub-data; wherein, each sound channel in the m channel sub-data The channel data respectively include channel data of one of the m channels in the audio sampling period.

For the specific content, please refer to the introduction of the foregoing embodiment, and the description will not be expanded here.

The display screen is configured to present an image screen;

The speaker is configured to reproduce sound;

The controller is configured to receive transmission data sent by n I2S channels;

Convert the transmission data sent by the n-channel I2S channel into m-channel audio data; where m>n.

In some embodiments, the display device includes n I2S channels,

The controller is configured to receive n channels of coded data sent by n channels of I2S channels within a preset frame clock period;

Decode n channels of coded data to generate m channels of channel sub-data; wherein, each channel sub-data in the m channels of channel sub-data includes one of the m channels in the audio sampling period Channel data within.

In some embodiments, the controller is configured to sequentially obtain n channel sub-data from the high-order data of the n channels of encoded data;

From the remaining data of the n channels of coded data, obtain channel sub-data of the m channel sub-data except for the n channel sub-data.

In some embodiments, the controller is configured to receive transmission data of multiple frame clock cycles sent by the n I2S channels;

The conversion of the transmission data sent by the n I2S channels into m channels of audio data specifically includes:

Using the transmission data of the multiple frame clock periods to generate m channel sub-data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels. Channel data in the audio sampling period.

In some embodiments, the controller is configured to store the data received from the n I2S channels in the audio sampling period in a buffer, and after the audio sampling period ends, the buffer is The encoded data in is decoded to generate m channel sub-data.

In some embodiments, the m channel sub-data is transmitted to the speaker.

For the specific data receiving process, please refer to the specific introduction of the above-mentioned embodiment, and the description is not repeated here.

It should be understood that, in the various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, rather than corresponding to the embodiments of the present application. The implementation process constitutes any limitation.

A person of ordinary skill in the art may be aware that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed by hardware or software depends on the specific application and design constraint conditions of the technical solution. Professionals and technicians can use different methods for each specific application to implement the described functions, but such implementation should not be considered beyond the scope of this application.

Those skilled in the art can clearly understand that, for the convenience and conciseness of description, the specific working process of the above-described system, device, and unit can refer to the corresponding process in the foregoing method embodiment, which will not be repeated here.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solutions of the embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it may be implemented in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website, computer, server, or data center. Transmission to another website, computer, server, or data center via wired (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer, or may include one or more data storage devices such as servers and data centers that can be integrated with the medium. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, and a magnetic tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)).

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in this application. Should be covered within the scope of protection of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

An audio data transmission method, characterized by comprising:

Acquire audio data of m channels;

Use n I2S channels to send the m-channel audio data to the data receiving end; where m>n.
The audio data transmission method according to claim 1, wherein said using n I2S channels to send the m channels of audio data to the data receiving end specifically comprises:

The m channel sub-data are encoded to generate n-channel coded data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels in the audio sampling period Channel data within;

In a preset frame clock period, the n I2S channels are used to send the n encoded data to the data receiving end through the n I2S channels.
The audio data transmission method according to claim 2, wherein the encoding of m channel sub-data to generate n channels of encoded data specifically includes:

Take the n channel sub-data of the m channel sub-data as high-order data of the n-channel coded data respectively, and supplement the channel sub-data of the remaining channels in the m channel sub-data After the n channel sub-data, the n channels of coded data are generated.
The audio data transmission method according to claim 2, characterized in that, before said using said n channels of I2S to send said n channels of encoded data to a data receiving end, said method further comprises:

Increasing the frequency of the serial clock of the n I2S channels;

Alternatively, before using the n I2S channels to send the n encoded data to the data receiving end, the method further includes:

The sampling mode of the serial data of the n I2S channels is switched from the serial clock single-edge collection mode to the serial clock double-edge collection mode.
The audio data transmission method according to claim 2, wherein said using n I2S channels to send the m channels of audio data to the data receiving end specifically comprises:

Using multiple frame clock cycles of n I2S channels to send m channel sub-data to the data receiving end; wherein, each channel sub-data in the m channel sub-data includes the m channel sub-data, respectively The channel data of one channel in the audio sampling period.
An audio data transmission method, characterized in that:

Receive transmission data sent by n I2S channels;

Convert the transmission data sent by the n-channel I2S channel into m-channel audio data; where m>n.
The audio data transmission method according to claim 6, wherein said receiving transmission data sent by n I2S channels specifically comprises:

Receive n-channel coded data sent by n-channel I2S channel within the preset frame clock period;

The conversion of the transmission data sent by the n I2S channels into m channels of audio data specifically includes:

Decode n channels of coded data to generate m channel sub-data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels in the audio sampling period Channel data within.
The audio data transmission method according to claim 7, wherein said decoding n channels of coded data to generate m channel sub-data specifically comprises:

Sequentially acquiring n channel sub-data from the high-bit data of the n channels of encoded data;

From the remaining data of the n channels of coded data, obtain channel sub-data of the m channel sub-data except for the n channel sub-data.
The audio data transmission method according to claim 6, wherein said receiving transmission data sent by n I2S channels specifically comprises:

Receiving transmission data of multiple frame clock cycles sent by the n I2S channels;

The conversion of the transmission data sent by the n I2S channels into m channels of audio data specifically includes:

Using the transmission data of the multiple frame clock periods to generate m channel sub-data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels. Channel data in the audio sampling period.
The audio data transmission method according to claim 7, wherein if the n I2S channels have independent clock signals, decoding the n channels of coded data to generate m channel sub-data, which specifically includes:

The data received from the n I2S channels during the audio sampling period is stored in a buffer, and after the audio sampling period is over, the encoded data in the buffer is decoded to generate m channels. data.
An audio data transmission device, which is characterized by comprising a processor, a memory, a bus, and a communication interface; wherein the memory is used to store computer execution instructions, and the processor and the memory are connected through the bus. When the data transmission device is running, the processor executes the computer-executable instructions, so that the audio data transmission device executes the audio data transmission method provided in any one of claims 1-5.
An audio data transmission device, which is characterized by comprising a processor, a memory, a bus, and a communication interface; wherein the memory is used to store computer execution instructions, and the processor and the memory are connected through the bus. When the data transmission device is running, the processor executes the computer-executed instruction, so that the audio data transmission device executes the audio data transmission method provided in any one of claims 6-10.
A display device, characterized by comprising:

This application provides a display device, including:

The display screen is configured to present an image screen;

The speaker is configured to reproduce sound;

The controller is configured to obtain audio data of m channels and send the audio data of m channels, where m>n.
The display device according to claim 13, wherein the controller is further configured to encode m channels of channel sub-data to generate n channels of encoded data; wherein, among the m channels of channel sub-data Each channel sub-data includes channel data of one of the m channels in an audio sampling period.
The display device according to claim 14, wherein the controller is further configured to use n channel sub-data in the m channels of channel sub-data as high-order data of the n channels of coded data, and The channel sub-data of the remaining channels in the m-channel sub-data is supplemented after the n-channel sub-data to generate the n-channel coded data.
The display device of claim 15, wherein the display device further comprises n I2S channels, and the controller is further configured to increase the frequency of the serial clock of the n I2S channels.
A display device, characterized by comprising:

This application provides a display device, including:

The display screen is configured to present an image screen;

The speaker is configured to reproduce sound;

The controller is configured to receive transmission data sent by n I2S channels;

Convert the transmission data sent by the n-channel I2S channel into m-channel audio data; where m>n.
18. The display device according to claim 17, wherein the controller is configured to receive n channels of coded data sent by n channels of I2S channels within a preset frame clock period;

Decode n channels of coded data to generate m channels of channel sub-data; wherein, each channel sub-data in the m channels of channel sub-data includes one of the m channels in the audio sampling period Channel data within.
The display device according to claim 18, wherein the controller is configured to sequentially obtain n channel sub-data from the high-order data of the n channels of encoded data;

From the remaining data of the n channels of coded data, obtain channel sub-data of the m channel sub-data except for the n channel sub-data.
The display device according to claim 19, wherein: the controller is configured to receive transmission data of multiple frame clock cycles sent by the n I2S channels;

The conversion of the transmission data sent by the n I2S channels into m channels of audio data specifically includes:

Using the transmission data of the multiple frame clock periods to generate m channel sub-data; wherein, each channel sub-data in the m channel sub-data includes one of the m channels. Channel data in the audio sampling period.