CN112202439B

CN112202439B - Capacitor isolation circuit, interface module, chip and system

Info

Publication number: CN112202439B
Application number: CN202011041301.0A
Authority: CN
Inventors: 白谱伟; 李浩杰; 任红强
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2021-09-07
Anticipated expiration: 2040-03-31
Also published as: CN113472338A; WO2021196958A1; CN112202439A

Abstract

The application discloses electric capacity isolating circuit, interface module, chip and system relates to electronic equipment technical field. The first end of a first switch circuit of the capacitive isolation circuit is connected with a first pull-up circuit, the first end is also connected with a first host, and the second end of the first switch circuit is connected with an interface; the interface is connected with a second host; the control end of the first switch circuit is connected with a power supply; the control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply; the voltage difference between the first end and the second end of the first switch circuit is a preset voltage value, and the preset voltage value is used for ensuring the level states of the first end and the second end to be consistent; when the voltage difference between the control end and the first end of the first switch circuit is greater than the voltage threshold, the first end and the second end are conducted; when the voltage difference between the control end and the first end of the second switch circuit is larger than the voltage threshold value, the first end and the second end are conducted. The load capacitance of the transmission link can be reduced by using the circuit so as to guarantee the signal transmission quality.

Description

Capacitor isolation circuit, interface module, chip and system

The application provides divisional application to Chinese patent application with the application number of 202010244788.6, the application date of 2020, 03 and 31, and the invention name of 'a capacitive isolation circuit, an interface module, a chip and a system'.

Technical Field

The application relates to the technical field of electronic equipment, in particular to a capacitive isolation circuit, an interface module, a chip and a system.

Background

For the electronic equipment using the high-speed signal, the load capacitance of the high-speed signal transmission link can reduce the rising edge of the high-speed signal, and when the load capacitance is too large, the problems of insufficient signal level, too large rising edge time and the like can be caused, so that the electronic equipment can not normally receive the signal.

Therefore, to ensure compatibility of electronic devices, the high-speed signal protocol specification usually has a definite constraint requirement on the load capacitance of the transmission link. However, when long signal transmission link systems are encountered, the constraints of the physical conditions can make it difficult for the load capacitance to meet the constraints. Taking an HDMI (High Definition Multimedia Interface) Interface of a television device as an example, a link load capacitance specification of a CEC (Consumer Electronics Control) signal transmitted through the HDMI Interface is required to be within 200pF, so as to ensure device compatibility. For a hardware architecture of a television device with a long HDMI channel, the link load capacitor of the CEC signal cannot meet the specification requirement of the link load capacitor, and thus the television device cannot receive signals normally.

Therefore, how to reduce the load capacitance of the signal transmission link is an urgent problem to be solved at present.

Disclosure of Invention

In order to solve the technical problem, the application provides a capacitive isolation circuit, an interface module, a chip and a system, which can reduce the load capacitance of a transmission link to ensure the signal transmission quality.

In a first aspect, an embodiment of the present application provides a capacitive isolation circuit, which can reduce a load capacitance of a link in use to ensure transmission quality of a signal, and is suitable for a scenario where a signal transmission distance is long, and a load capacitance requirement cannot be met or a signal driving force cannot be met. The capacitive isolation circuit includes: a first switch circuit, a second switch circuit and a first pull-up circuit; the first end of the first switch circuit is connected with the first pull-up circuit, and the first end of the first switch circuit is also used for connecting a first host; the second end of the first switch circuit is used for connecting the interface; the interface is used for connecting a second host; the control end of the first switch circuit is connected with a power supply; the control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply; the voltage difference between the first end and the second end of the first switch circuit is a preset voltage value, and the preset voltage value is used for ensuring that the level states of the first end and the second end of the first switch circuit are consistent; when the voltage difference between the control end and the first end of the first switch circuit is greater than the voltage threshold, the first end and the second end of the first switch circuit are conducted; when the voltage difference between the control end and the first end of the second switch circuit is greater than the voltage threshold, the first end and the second end of the second switch circuit are conducted.

The value of the preset voltage value is determined by the principle that the voltages of the first end and the second end of the first switch circuit can be determined to be at the same level, namely, at the same high level or at the same low level, so that the determination interval of the value of the preset voltage value relative to the level is smaller. This electric capacity buffer circuit through using two switch circuit, can shorten load link length, reduces load electric capacity, and then ensures the transmission quality of signal.

With reference to the first aspect, in a first possible implementation manner, the first pull-up circuit includes: a first pull-up resistor. The first end of the first switch circuit is connected with the power supply through a first pull-up resistor. The first pull-up circuit can function as a signal enhancement.

With reference to the first aspect and any one of the foregoing implementation manners, in a second possible implementation manner, the first switch circuit is a first NMOS transistor, a first end of the first switch circuit is a source electrode of the first NMOS transistor, a second end of the first switch circuit is a drain electrode of the first NMOS transistor, and a control end of the first switch circuit is a gate electrode of the first NMOS transistor.

The function of the first switch circuit is realized by using the first NMOS tube, the circuit structure is simple, the hardware cost is low, and a complex signal processing chip is not required to be added, so that the signal response speed is high, the power consumption is low, and the software development investment is not required to be increased.

With reference to the first aspect and any one of the foregoing implementation manners, in a third possible implementation manner, the second switch circuit is a second NMOS transistor, a first end of the second switch circuit is a source of the second NMOS transistor, a second end of the second switch circuit is a drain of the second NMOS transistor, and a control end of the second switch circuit is a gate of the second NMOS transistor.

The function of the second switch circuit is realized by using the second NMOS tube, the circuit structure is simple, the hardware cost is low, and no complex signal processing chip is required to be added, so that the signal response speed is high, the power consumption is low, and the software development investment is not required to be increased.

With reference to the first aspect and any one of the foregoing implementation manners, in a fourth possible implementation manner, the first switch circuit includes a first switch and a first diode; the anode of the first diode is connected with the first end of the first switch, and the cathode of the first diode is connected with the second end of the first switch.

The function of the first switch circuit is realized by using the first switch and the first diode, the circuit structure is simple, the hardware cost is low, and a complex signal processing chip is not required to be added, so that the signal response speed is high, the power consumption is low, and the software development investment is not required to be increased.

With reference to the first aspect and any one of the foregoing implementation manners, in a fifth possible implementation manner, the second switch circuit includes a second switch and a second diode; the anode of the second diode is connected with the first end of the second switch, and the cathode of the second diode is connected with the second end of the second switch.

The function of the first switch circuit is realized by using the second switch and the second diode, the circuit structure is simple, the hardware cost is low, and no complex signal processing chip is required to be added, so that the signal response speed is high, the power consumption is low, and the software development investment is not required to be increased.

With reference to the first aspect and any one of the foregoing implementation manners, in a sixth possible implementation manner, the capacitive isolation circuit further includes: a protection circuit. The control end of the second switch circuit is grounded through the protection circuit. The protection circuit is used for filtering interference signals.

With reference to the first aspect and any one of the foregoing implementation manners, in a seventh possible implementation manner, the protection circuit includes: and a ground resistor. The control end of the second switch circuit is grounded through a grounding resistor.

The grounding resistor is used as a protection circuit, the circuit structure is simple, and interference signals can be filtered

With reference to the first aspect and any one of the foregoing implementation manners, in an eighth possible implementation manner, the capacitive isolation circuit further includes: a current limiting resistor. The control end of the first switch circuit is connected with a power supply through a current-limiting resistor. The current limiting resistor is used for preventing the current from being overlarge, and further protecting the circuit.

With reference to the first aspect and any one of the foregoing implementation manners, in a ninth possible implementation manner, the capacitive isolation circuit further includes: a second pull-up circuit. The second end of the first switch circuit is connected with the second pull-up circuit.

The second pull-up circuit can enhance the transmission signal at the second end side of the first switch circuit so as to improve the signal transmission quality.

With reference to the first aspect and any one of the foregoing implementation manners, in a tenth possible implementation manner, the second pull-up circuit includes: a second pull-up resistor. The second end of the first switch circuit is connected with the power supply through a second pull-up resistor to play a role in signal enhancement.

In a second aspect, the present application further provides a docking station, including the capacitive isolation circuit provided in any one of the above possible implementation manners, further including: an interface. The interface is used for connecting the second host and sending the signal sent by the second host to the first host through the capacitive isolation circuit.

The docking station can shorten the length of a load link, reduce load capacitance and guarantee the transmission quality of signals, and a capacitance isolation circuit in the docking station is simple in structure, low in hardware cost, high in signal response speed, low in power consumption and free of software development investment, and a complex signal processing chip is not required to be added.

With reference to the second aspect, in a first possible implementation manner, the interface is a high definition multimedia interface HDMI interface.

In one application scenario of the docking station, the docking station may be a Dock box, and is used for implementing signal transmission between the television host and the television box. At this time, the interface of the docking station may include an HDMI interface, the docking station is connected to the tv box through an HDMI cable, the HDMI cable may transmit CEC signals, and at this time, the capacitive isolation circuit of the docking station 400 is used to reduce link load capacitance during transmission of CEC signals and ensure transmission quality of signals between the tv host and the tv box.

In a third aspect, the present application further provides a capacitive isolation chip, which specifically includes: the first input/output IO port, the second IO port and the third IO port. The first IO port is used for connecting a first host; the second IO port is used for being connected with a second host through an interface; the voltage difference between the first IO port and the second IO port is a preset voltage value, and the preset voltage value is used for enabling the level states between the first IO port and the second IO port to be consistent. When the voltage difference between the first IO port and the third IO port is larger than the voltage threshold, the first IO port and the second IO port are conducted, so that signals are transmitted between the first host and the second host.

The capacitance isolation circuit of the capacitance isolation chip can be any one of the possible implementation modes, so that the length of a signal link can be shortened, the load capacitance is reduced, and meanwhile, the pull-up circuit of the capacitance isolation circuit can also play a role in signal enhancement, so that the transmission quality of signals can be guaranteed. In addition, the capacitive isolation chip is simple in structure and low in hardware cost, compared with a complex signal processing chip, the capacitive isolation chip is high in signal response speed and low in power consumption, and software development investment does not need to be increased.

In a fourth aspect, the present application further provides a playing system, where the playing system includes the docking station provided in any one of the above implementation manners, and further includes: a first host. The first host is connected with the docking station through a transmission cable; the docking station is used for transmitting the signal transmitted by the second host to the first host. The first host is used for playing the content.

With reference to the fourth aspect, in a first possible implementation manner, the first host is a television host, and the second host is a video source host. At this time, the docking station (i.e. Dock box) is used for sending the content sent by the video source host to the television host so as to enable the television host to play the content.

The docking station of the playing system comprises a capacitance isolating circuit, the length of a load link behind the capacitance isolating circuit is the length of a link between a second host and a second end of a first switch circuit of the capacitance isolating circuit, and the length of a link between the first host and a first end of the first switch circuit is not included, so that the length of the load link can be shortened, the load capacitance is reduced, meanwhile, the transmission quality of signals can be guaranteed, and further, the content sent by a video source host can be normally played by a television host of the playing system.

The scheme provided by the application has at least the following advantages:

the capacitive isolation circuit includes a first switch circuit, a second switch circuit, and a first pull-up circuit. The first end of the first switch circuit is connected with the first pull-up circuit, and the first end of the first switch circuit is also connected with the first host. The second end of the first switch circuit is connected with an interface, the interface is connected with the second host, and the control end of the first switch circuit is connected with the power supply. The control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply. The voltage difference between the first end and the second end of the first switch circuit is a preset voltage value, and the value of the preset voltage value is determined to be the same level, namely the same high level or the same low level.

When the second host inputs a high level to the second end of the first switch circuit, the first end of the first switch circuit is also at the high level at the moment, and the first pull-up circuit has an enhancement effect on the signal of the first end of the first switch circuit, so that the high-level signal can be normally transmitted to the first host.

When the second host inputs a low level to the second end of the first switch circuit, the voltage of the first end of the first switch circuit is equal to a preset voltage value, the control end of the first switch circuit is connected with the power supply and is a high level, the voltage difference between the control end and the first end of the first switch circuit is greater than a voltage threshold value, the first end and the second end of the first switch circuit are conducted, so that the potential of the first end of the first switch circuit is reduced to the low level, and the low level is transmitted to the first host.

When the first host sends a high level to the first end of the first switch circuit, the control end of the first switch circuit is connected with the power supply and is at the high level, and because the voltage difference between the control end and the first end of the first switch circuit is smaller than the voltage threshold, the first end and the second end of the first switch circuit are disconnected at the moment, and the second end of the first switch circuit is also at the high level, the high level is transmitted to the second host at the moment.

When the first host sends a low level to the first end of the first switch circuit, the control end of the first switch circuit is connected with the power supply and is at a high level, and because the voltage difference between the control end and the first end of the first switch circuit is greater than the voltage threshold, the first end and the second end of the first switch circuit are conducted at the moment, so that the second end of the first switch circuit is at a low level, and the low level is transmitted to the second host at the moment.

For a system applying the capacitive isolation circuit, when the load capacitance of a transmission link is tested, the anode of the tester is connected with the control end of the second switch circuit and is at a high level, and the cathode of the tester is connected with the second end of the first switch circuit through an interface and is at a low level. When the first host is the tested device and is not powered on, the power supply is not powered on at the moment, and the first end, the second end and the control end of the first switch circuit are all at low level. And the control end of the second switch circuit is connected with the anode of the tester, so that the voltage difference between the control end of the second switch circuit and the first end is greater than the voltage threshold, the first end and the second end of the second switch circuit are conducted at the moment, the control end of the first switch circuit and the first end have the same potential, and the first end and the second end of the first switch circuit are disconnected. The load link length at this time is the link length between the tester and the second end of the first switch circuit, and does not include the link length between the first host and the first end of the first switch circuit. In practical application, the length of the load link is the link length between the second host and the second end of the first switch circuit, and the shortened link length is the link length between the first host and the first end of the first switch circuit, so that the length of the load link is shortened, and the load capacitance can be reduced.

In summary, by using the capacitive isolation circuit provided by the embodiment of the present application, through using two switch circuits, the length of the load link can be shortened, the load capacitance can be reduced, and the transmission quality of signals can be further ensured.

Drawings

FIG. 1 is a schematic diagram of an application scenario;

FIG. 2 is a schematic diagram of a CEC signal conversion chip;

FIG. 3 is a schematic diagram of a CEC control chip;

fig. 4A is a schematic diagram of a capacitive isolation circuit according to an embodiment of the present disclosure;

fig. 4B is a schematic diagram of an application scenario provided in the embodiment of the present application;

fig. 5 is a schematic diagram of an operating principle corresponding to fig. 3 provided in an embodiment of the present application;

fig. 6 is a schematic view of another operating principle corresponding to fig. 3 provided in an embodiment of the present application;

fig. 7 is a schematic view of another operation principle corresponding to fig. 3 provided in an embodiment of the present application;

fig. 8 is a schematic view of another working principle corresponding to fig. 3 according to an embodiment of the present application;

FIG. 9 is a schematic diagram illustrating the operation of the circuit of FIG. 3 during a load capacitance test;

FIG. 10 is a schematic diagram of another capacitive isolation circuit provided in an embodiment of the present application;

fig. 11 is a schematic diagram of an operation principle corresponding to fig. 10 according to an embodiment of the present application;

FIG. 12 is a schematic diagram illustrating another operating principle corresponding to FIG. 10 according to an embodiment of the present disclosure;

FIG. 13 is a schematic diagram illustrating yet another operating principle corresponding to FIG. 10 according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram illustrating a further operation principle corresponding to FIG. 10 according to an embodiment of the present disclosure;

FIG. 15 is a schematic diagram illustrating the operation of the circuit shown in FIG. 10 during a load capacitance test;

FIG. 16 is a schematic diagram of another capacitive isolation circuit provided in an embodiment of the present application;

FIG. 17 is a schematic diagram of another capacitive isolation circuit according to an embodiment of the present application;

FIG. 18 is a schematic diagram of another capacitive isolation circuit provided in an embodiment of the present application;

fig. 19 is a schematic view of a docking station according to an embodiment of the present application;

fig. 20 is a schematic diagram of a capacitive isolation chip according to an embodiment of the present disclosure;

fig. 21 is a schematic diagram of another capacitive isolation chip provided in an embodiment of the present application;

fig. 22 is a schematic diagram of a packaged capacitive isolation chip according to an embodiment of the present application;

fig. 23 is a schematic diagram of a playing system according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions provided by the embodiments of the present application more clearly understood by those skilled in the art, the following first describes the influence of the load capacitance of the transmission link on the high-speed signal transmission process with reference to a specific application scenario.

Taking an application scenario as television equipment as an example, refer to fig. 1, which is a schematic diagram of an application scenario provided in an embodiment of the present application.

Take the case that the playback system includes a tv host 101, a Dock box 102, and a tv box 103.

The host 101 is connected to the Dock box 102 through a cable, and the Dock box 102 is mainly convenient for a user to operate, and an interface on the host 101 is transferred to the Dock box 102. The Dock box 102 is connected to the tv box 103 via an HDMI cable, and transmits information transmitted from the tv box 103 to the tv host 101.

However, the tv box transmits signals to the tv device through the HDMI interface to enable the tv device to play, and the link load capacitance of the CEC signal transmitted through the HDMI interface is required to be within 200pF to ensure device compatibility. For the television equipment with a long HDMI channel, the link load capacitor of the CEC signal is difficult to meet the specification requirement of the link load capacitor, and the television equipment cannot normally receive the signal.

The following is a detailed description of the principle of a playback system comprising a tv host, a Dock box and a tv box to make the link load capacitance meet the specification requirements.

A first possible implementation is first described below.

Referring to fig. 2, a schematic diagram of the CEC signal conversion chip is shown.

A System-on-a-chip (SOC) of the main board of the tv host 101 is connected to a Dock box 102 through a connection cable, the tv host 101 and the Dock box 102 form a receiving device, the Dock box 102 is connected to an HDMI cable through an HDMI interface, and the other end of the HDMI cable is connected to a tv box 103 serving as a transmitting device.

In this implementation, a CEC conversion IC (Integrated Circuit) is used at the Dock box 102 to convert a CEC signal into an I2C (Inter-Integrated Circuit) signal, and the Dock box 102 transmits the converted signal to the motherboard SOC of the tv host 101, thereby implementing the function of the CEC signal. Since the CEC signal is not transmitted between the tv host 101 and the Dock box 102, the transmission link length of the CEC signal is shortened, and the purpose of reducing the load capacitance is achieved.

However, this implementation requires the main board SOC of the tv host 101 to poll the CEC signal conversion chip in the Dock box 102 to monitor whether a new command is input. This may result in that neither the CEC conversion chip nor the I2C of the motherboard SOC can be powered down in the standby state, increasing standby power consumption. Moreover, because a CEC conversion chip and peripheral devices are added, corresponding software needs to be developed, hardware cost and software development investment are large, and in addition, due to the existence of a signal conversion process, functional response is slow.

A second possible implementation is described below.

Referring to fig. 3, a schematic diagram of the CEC control chip is shown.

The tv host 101 is connected to the Dock box 102 through a connection cable, and this implementation uses a CEC control IC at the Dock box 102, through which CEC signals are directly processed and communicated with the tv box 103, thus shortening the link length of CEC.

However, the implementation mode has large investment in hardware design and software design and high cost. And the CEC control IC is required to be in an operating state in a standby state, adding extra power consumption.

The above description is only given by taking a television device as an example, and it can be understood that, for other electronic devices using high-speed signals, the problem that the load capacitance of the high-speed signal transmission link cannot meet the requirement due to the overlong high-speed signal transmission link also exists, and therefore, the description of each application scenario is omitted here.

In order to solve the above technical problem, embodiments of the present application provide a capacitive isolation circuit including a first switch circuit, a second switch circuit, and a first pull-up circuit. The first end of the first switch circuit is connected with the first pull-up circuit, and the first end of the first switch circuit is also connected with the first host. The second end of the first switch circuit is connected with an interface which can be connected with a second host, and the control end of the first switch circuit is connected with a power supply. The control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply. The voltage between the first end and the second end of the first switch circuit is a preset voltage value, and the value of the preset voltage value is determined according to the principle that the voltages of the first end and the second end of the first switch circuit can be determined to be at the same level, namely, at the same high level or at the same low level.

When the second host inputs a high level to the second end of the first switch circuit, the first end of the first switch circuit is also at the high level at the moment, and the first pull-up circuit has an enhancement effect on the signal at the first end of the first switch circuit at the moment, so that the high-level signal can be normally transmitted to the first host.

When the second host inputs a low level to the second end of the first switch circuit, the voltage of the first end of the first switch circuit is equal to a preset voltage value, the control end of the first switch circuit is connected with the power supply and is a high level, so that the voltage difference between the control end and the first end of the first switch circuit is greater than a voltage threshold, the first end and the second end of the first switch circuit are conducted, the potential of the first end of the first switch circuit is reduced to the low level, and the low level is transmitted to the first host.

For a system applying the capacitive isolation circuit, when the load capacitance of a transmission link is tested, the anode of the tester is connected with the control end of the second switch circuit and is at a high level, and the cathode of the tester is connected with the second end of the first switch circuit through an interface and is at a low level. When the first host is the tested device and is not powered on, the power supply is not powered on. At this time, the first end, the second end and the control end of the first switch circuit are all at low level. Because the control end of the second switch circuit is at a high level, the voltage difference between the control end and the first end of the second switch circuit is greater than a voltage threshold value, and the first end and the second end of the second switch circuit are conducted at the moment, the control end and the first end of the first switch circuit are enabled to have the same potential, and the first end and the second end of the first switch circuit are disconnected. At this time, the load link length is the link length from the tester to the first switch circuit, and the link length from the first host to the first end of the first switch circuit is not included, so that the load link length is shortened, and the load capacitance can be reduced.

In summary, the capacitive isolation circuit provided by the embodiment of the present application can shorten the length of a load link, reduce the load capacitance, and simultaneously ensure the transmission quality of signals, and has the advantages of simple circuit structure, low hardware cost, and no need of adding a complex signal processing chip, so that the signal response speed is high, the power consumption is low, and no need of adding software development investment is required.

The technical solution in the present application will be specifically described below with reference to the drawings in the embodiments of the present application.

The first circuit embodiment is as follows:

the embodiment of the application provides a capacitance isolating circuit, which can reduce the load capacitance of a link when in use so as to ensure the transmission quality of signals, and is suitable for a scene that the signal transmission distance is long, and the load capacitance requirement cannot be met or the signal driving force cannot be met. The following detailed description is made with reference to the accompanying drawings.

Referring to fig. 4A, the figure is a schematic diagram of a capacitive isolation circuit according to an embodiment of the present application.

The capacitive isolation circuit includes: a first switch circuit 201, a second switch circuit 202, and a first pull-up circuit 203.

The first terminal of the first switch circuit 201 is connected to the first pull-up circuit 203, and the first terminal of the first switch circuit 201 is further connected to the first host 205.

The second end of the first switch circuit 201 is connected to the interface 204, and the interface 204 is used for connecting to the second host 206.

In the embodiment of the present application, the type of the interface 204 is not specifically limited, and the type of data transmitted between the first host 205 and the second host 206 and the type of the cable used are not specifically limited.

The following examples are given.

Referring to fig. 4B, the figure is a schematic diagram of an application scenario provided in the embodiment of the present application.

Taking the application of the capacitive isolation circuit to a television playing system as an example, the playing system comprises a television host 101, a Dock box 102 and a television box 103.

Wherein the first host 205 may correspond to the tv host 101 and the second host 206 may correspond to the tv box 103. The capacitive isolation circuit 102a and the HDMI interface provided in the embodiment of the present application may be located in the Dock box 102. In this case, the interface 204 is an HDMI interface, and is connected to the tv box 103 via an HDMI cable, and a CEC signal is transmitted within the HDMI cable.

At this time, the capacitive isolation circuit is used to reduce a link load capacitance at the time of CEC signal transmission and to ensure the transmission quality of signals between the tv host 101 and the tv box 103.

It can be understood that the above is only one application scenario of the capacitive isolation circuit, and the capacitive isolation circuit can also be used in other systems with longer height signal transmission links, and details are not repeated in the embodiments of the present application.

With continued reference to fig. 3, the control terminal of the first switch circuit 201 is connected to the power supply 207.

The control terminal of the second switch circuit 202 of the capacitive isolation circuit is grounded, the first terminal of the second switch circuit 202 is connected to the first terminal of the first switch circuit 201, and the second terminal of the second switch circuit 202 is connected to the power supply 207.

It will be appreciated that the connected power supply 207 of the capacitive isolation circuit may be implemented by a power supply on the first host 205, i.e. powered by the power supply of the first host.

The voltage difference between the first terminal and the second terminal of the first switch circuit 201 is a preset voltage value, so that the level states of the first terminal and the second terminal of the first switch circuit 201 are consistent, that is, the value of the preset voltage value is determined by the principle that the voltages of the first terminal and the second terminal of the first switch circuit 201 are determined to be the same level, that is, the same level is a high level or the same level is a low level. The preset voltage value is not specifically limited in the embodiment of the present application.

In practical applications, the voltage difference between the first terminal and the second terminal of the first switch circuit 201 can be clamped to a preset voltage value by a voltage clamping manner. The preset voltage value may be set to a smaller voltage value with respect to the range of the high and low levels, for example, a signal with a voltage less than 2.5V is uniformly recognized as a low level, and a signal with a voltage greater than 2.5V is uniformly recognized as a high level. Assuming that the voltage of the first terminal of the first switch circuit 201 is 3.3V, 3.3V is greater than 2.5V, and thus is recognized as a high level. Further, since the voltage drop between the first terminal of the first switch circuit 201 and the second terminal of the first switch circuit 201 is clamped to the preset voltage value, for example, the value range of the preset voltage value may be set to any voltage value within (0, 0.8V), and assuming that the preset voltage value is set to 0.1V, under the switch conducting condition, since the voltage of the first terminal of the first switch circuit 201 is 3.3V, the voltage of the second terminal of the first switch circuit 201 is clamped to 3.2V, and since 3.2V is higher than 2.5V, the second terminal of the first switch circuit 201 may also be identified as a high level, that is, the voltages of the first terminal and the second terminal of the first switch circuit 201 are determined as the same level.

When the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit 201 are turned on.

When the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the voltage threshold, the first terminal and the second terminal of the second switch circuit 202 are turned on.

The voltage threshold is related to a specific implementation manner of the switch circuit, and this is not particularly limited in the embodiment of the present application.

For convenience of explanation, the operation principle of the capacitive isolation circuit will be specifically described below by taking "1" as the high level and "0" as the low level.

Referring to fig. 5, this figure is a schematic diagram of an operation principle corresponding to fig. 4 provided in an embodiment of the present application.

The first terminal, the second terminal, and the control terminal of the first switch circuit 201 correspond to the B terminal, the C terminal, and the a terminal, respectively. The first terminal, the second terminal, and the control terminal of the second switch circuit 202 correspond to the terminal B ', the terminal C ', and the terminal a ', respectively.

When the second host 206 transmits "1" to the first host 205, the second host 206 inputs "1" to the second terminal of the first switch circuit 201, the terminal C is at a high level, and the terminal B is also at a high level because the terminal B is connected to the pull-up circuit 203. The control terminal of the first switch circuit 201 is connected to the power supply and is also at a high level. At this time, the voltage difference between the terminals a and B is smaller than the preset threshold, so the first terminal and the second terminal of the first switch circuit 201 are disconnected.

At this time, the first pull-up circuit 203 has an enhancing effect on the signal of the first terminal of the first switch circuit 201, and the first host 205 may normally receive the signal "1".

The connection cable between the interface 204 and the second host 206 may be an HDMI cable, or may be a cable used in other scenarios where load capacitance of a link needs to be reduced, which is not specifically limited herein.

Referring to fig. 6, this figure is a schematic diagram of another operation principle corresponding to fig. 4 provided in an embodiment of the present application.

When the second host 206 sends "0" to the first host 205, the second host 206 inputs "0" to the second terminal of the first switch circuit 201, at this time, the potential of the first terminal of the first switch circuit 201 is equal to the preset voltage value, and the control terminal of the first switch circuit 201 is connected to the power supply and is at a high level, because the preset voltage value is low, the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold value, the first terminal and the second terminal of the first switch circuit 201 are conducted, at this time, the voltage of the first switch circuit 201 is reduced to "0" from the preset voltage value, and then "0" is transmitted to the first host 205.

Referring to fig. 7, this figure is a schematic diagram of another operation principle corresponding to fig. 4 provided in an embodiment of the present application.

When the first host 205 sends "1" to the second host 206, the first host 205 sends "1" to the first terminal of the first switch circuit 201, the control terminal of the first switch circuit 201 is connected to the power source at a high level, and the first terminal and the second terminal of the first switch circuit 201 are disconnected at this time because the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is smaller than the voltage threshold.

And since the voltage difference between the two terminals B, C is a predetermined voltage value, the second terminal of the first switch circuit 201 is also at a high level, and the second host 206 can normally receive "1".

Referring to fig. 8, a schematic diagram of still another operation principle provided by the embodiment of the present application is shown.

When the first host 205 sends "0" to the second host 206, the first host 205 sends "0" to the first terminal of the first switch circuit 201, the first terminal of the first switch circuit 201 is at a low level, the control terminal of the first switch circuit 201 is connected to the power source at a high level, and since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first terminal and the second terminal of the first switch circuit 201 are connected at this time. Since the first terminal of the first switch circuit 201 is at a low level, the second terminal of the first switch circuit 201 is at a low level, and the second host 206 can normally receive "0" at this time.

Referring to fig. 9, the schematic diagram of the operation principle of the circuit shown in fig. 4 when the load capacitance test is performed is shown.

RLC tester 208 may be used to test the load capacitance of the signal link to determine whether the capacitive load circuit meets certification requirements, as described below with power supply 207 unpowered.

The first host 205 is a device under test, and is externally connected with a test fixture through the interface 204, the positive pole (in the figure, the positive pole) of the RLC tester 208 is connected with the ground of the first host 205 through the interface 204, and the negative pole (in the figure, the negative pole) of the RLC tester 208 is connected with a signal link under test. The RLC tester 208 determines the load capacitance by sending a voltage sine wave with a dc bias on the positive pole and measuring the voltage and current sine waves received on the negative pole.

At this time, the second terminal of the first switch circuit 201 is connected to the negative electrode of the RLC tester 208 through the interface 204, and the potential is "0", and since the voltage difference between the two terminals B, C is a preset voltage value, the potential of the first terminal of the first switch circuit 201 is also "0". Since the power source 207 is not powered on, the control terminal of the first switch circuit 201 is in a floating state.

The control terminal of the second switch circuit 202 is connected to the positive electrode of the RLC tester 208, i.e., the control terminal of the second switch circuit 202 is connected to the positive electrode of the RLC tester 208, and the potential of the control terminal of the second switch circuit 202 is "1" by the sine wave output from the RLC tester 208. At this time, the potential of the first terminal (B') of the second switch circuit 202 and the potential of the first terminal (B) of the first switch circuit 201 are both "0", so that the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the preset threshold, and the first terminal and the second terminal of the second switch circuit 202 are turned on. Further, the control terminal and the first terminal of the first switch circuit 201 are made to have the same potential, and thus the first terminal and the second terminal of the first switch circuit 201 are disconnected.

The length of the signal link to be tested at this time is the length of the link from the RLC tester 208 to the first switch circuit 201, and the length of the link from the first host to the first end of the first switch circuit is not included, so that the length of the signal link is shortened, and the load capacitance can be reduced.

It is understood that the principle of testing the load capacitance is similar when the power supply 207 is powered on, and the embodiments of the present application are not described herein again.

In summary, with the capacitive isolation circuit provided in the embodiment of the present application, by using the two switch circuits, the length of the signal link can be shortened, and then the load capacitance is reduced, and meanwhile, the pull-up circuit can also play a role in signal enhancement, so that the transmission quality of signals can be ensured. In addition, compared with the implementation modes corresponding to fig. 2 and fig. 3, the circuit provided by the embodiment of the application has a simple structure and low hardware cost, and does not need to add a complex signal processing chip, so that the signal response speed is high, the power consumption is low, and the software development investment is not needed to be increased.

The working principle of the capacitive isolation circuit is described below with reference to a specific circuit implementation.

The second circuit embodiment:

referring to fig. 10, a schematic diagram of another capacitive isolation circuit provided in the embodiment of the present application is shown.

Referring also to fig. 4, a specific implementation of the first switch circuit 201, the second switch circuit 202, and the first pull-up circuit 203 is shown in fig. 10.

The first switch circuit 201 of the embodiment of the present application includes a first NMOS (Negative-Metal-Oxide-Semiconductor) transistor Q1. The first terminal of the first switch circuit 201 is a source of a first NMOS transistor Q1 (denoted by letter S in the figure), the second terminal of the first switch circuit 201 is a drain of a first NMOS transistor Q1 (denoted by letter D in the figure), and the control terminal of the first switch circuit 201 is a gate of a first NMOS transistor Q1 (denoted by letter G in the figure).

D1 may be a body diode of the first NMOS transistor Q1, or an external diode; d2 may be a body diode of the second NMOS transistor Q2, or an external diode. The following description will be given by taking D1 as the body diode of the first NMOS transistor Q1 and D2 as the body diode of the second NMOS transistor Q2 as an example.

The second switch circuit 202 of the embodiment of the present application includes a second NMOS transistor Q2. The first terminal of the second switch circuit 202 is a source of the second NMOS transistor Q2 (denoted by letter S '), the second terminal of the second switch circuit 202 is a drain of the second NMOS transistor Q2 (denoted by letter D '), and the control terminal of the second switch circuit 202 is a gate of the second NMOS transistor Q2 (denoted by letter G ').

The first pull-up circuit 203 includes a first pull-up resistor R1, and the first terminal of the first switch circuit 201 is connected to the power source 207 through a first pull-up resistor R1, and the first pull-up circuit can perform a signal enhancement function.

Further, the capacitive isolation circuit further includes a protection circuit, and the control terminal of the second switch circuit 202 is grounded through the protection circuit. The protection circuit is used for filtering interference signals.

In the implementation shown in fig. 10, the protection circuit includes a ground resistor R2, i.e., the control terminal of the second switch circuit 202 is grounded through a ground resistor R2.

Furthermore, the capacitive isolation circuit further comprises a current limiting circuit R3, and a current limiting resistor R3 is used for protecting the circuit. The control terminal of the first switch circuit 201 is connected to the power supply 207 through a current limiting resistor R3.

In practical applications, the power supply connected to the first terminal of the first switch circuit 201 through the first pull-up circuit 203 and the power supply connected to the control terminal of the first switch circuit 201 through the current-limiting resistor R3 may be the same power supply.

It is understood that, in practical applications, the specific specifications of the first NMOS transistor Q1 and the second NMOS transistor Q2 may be the same, and the selection should satisfy the following conditions:

1. the turn-on threshold voltage Vth of the two NMOS transistors should be less than the voltage of the power supply 207, so that the first NMOS transistor Q1 can turn on when transmitting "0".

2. When the load capacitance test is performed, the minimum voltage applied to the gate of the second NMOS transistor Q2 by the positive electrode of the RLC tester 208 used is Vmin, and the turn-on threshold voltage Vth of the NMOS transistor further needs to satisfy Vth < Vmin, so that the second NMOS transistor Q2 can be turned on in the load capacitance test state.

3. The breakover threshold voltage Vth of the NMOS tube also needs to satisfy that Vth is more than V_S’D’So that the first NMOS transistor Q1 can be turned off during the load capacitance testAnd (7) breaking.

4. Due to the action of the body diode (also called parasitic diode, anode is connected with the source electrode of the NMOS tube, and cathode is connected with the drain electrode of the NMOS tube) of the NMOS tube, the voltage between the source electrode and the drain electrode should satisfy V_SDU (where U is the voltage drop of the body diode), and V_SDI.e. the preset voltage value, is a smaller voltage value.

In practice, the capacitive isolation circuit and the interface 204 may be packaged together as a unitary device. For example, referring to fig. 4 and 10 together, when the present application is applied to a television playback system, 300 comprising capacitive isolation circuit and interface 204 may be Dock box 102 of fig. 4. At this time, the first host 205 corresponds to the tv host 101, the second host 206 corresponds to the tv box 103 (also referred to as a video source host), the interface 204 may be an HDMI interface, and the interface 204 and the second host 206 are connected by an HDMI cable. If there are multiple HDMI ports in the Dock box 102, the CEC signal of each HDMI port can be connected as 1-way signal before entering the capacitive isolation circuit

At this time, the voltage value of the power supply 207 may be 3.3V, and when a load capacitance test is performed on the television playing system, the minimum voltage Vmin applied to the gate of the second NMOS transistor Q2 by the positive electrode of the RLC tester is 0.84V, and the turn-on threshold voltage Vth is less than 0.84V.

The operation principle of the capacitive isolation circuit according to the embodiment of the present application is described in detail below.

Referring to fig. 11, a schematic diagram of an operation principle corresponding to fig. 10 is provided for the embodiment of the present application.

When the second host 206 sends "1" to the first host 205, the drain of the first NMOS transistor Q1 is at "1", and at this time, the source of the first NMOS transistor Q1 is pulled up to the power source 207 through the first pull-up resistor, so the voltage is at "1", and the gate of the Q1 is pulled up to the power source 207 through the current-limiting resistor R3, so the gate of the Q1 is at "1".

At this time, for Q1, the voltage V between the gate and the source_GS< Vth, therefore Q1 is off.

Referring to fig. 12, this figure is a schematic diagram of another operation principle corresponding to fig. 10 provided in the embodiment of the present application.

When the second host 206 sends "0" to the first host 205, the second host 206 inputs "0" to the second terminal of the first NMOS transistor Q1, and the voltage difference V between the source and drain of Q1 is due to the body diode of the first NMOS transistor Q1_SDLower (less than 0.1V), the source potential of Q1 decreases and approaches the drain.

The gate of the first NMOS transistor Q1 is pulled up to a high level through the current limiting resistor R3, and the voltage V between the gate and the source of the first NMOS transistor Q1_GSAt most Vth, the first NMOS transistor Q1 is turned on, and the potential of the first NMOS transistor is "0" at this time, so as to transmit "0" to the first host 205.

Referring to fig. 13, this figure is a schematic diagram of another operation principle corresponding to fig. 10 provided in an embodiment of the present application.

When the first host 205 sends "1" to the second host 206, the source of the first NMOS transistor Q1 is at "1", and the gate of the first NMOS transistor Q1 is pulled up to the power source 207 through the current limiting resistor R3, at "1". At this time, the voltage V between the gate and the source of the first NMOS transistor Q1_GS< Vth, the first NMOS transistor Q1 is turned off, and the drain voltage of the first NMOS transistor Q1 is close to the source voltage due to the body diode, so the drain level is "1", and the second host 206 can normally receive "1".

Referring to fig. 14, a schematic diagram of a further operation principle corresponding to fig. 10 according to an embodiment of the present application is shown.

When the first host 205 sends "0" to the second host 206, the source of the first NMOS transistor Q1 is at "0", and the gate of the first NMOS transistor Q1 is pulled up to the power source 207 through the current limiting resistor R3, at "1". At this time, the voltage V between the gate and the source of the first NMOS transistor Q1_GSVth, the first NMOS transistor Q1 is closed, the drain potential of the first NMOS transistor Q1 is "0", and the second host 206 can normally receive "0".

Referring to fig. 15, the schematic diagram of the operation of the circuit shown in fig. 10 during the load capacitance test is shown.

The first host 205 is a device under test, the positive pole (positive pole in the figure) of the RLC tester 208 is connected to the common ground through the interface 204, and the negative pole (negative pole in the figure) of the RLC tester 208 is connected to a signal link under test.

The drain potential of the first NMOS transistor Q1 is the same as the negative pole of the RLC tester 208, and is "0". Due to the action of the body diode, the source and drain potentials of the first NMOS transistor Q1 are equal to "0".

At this time, the gate potential of the second NMOS transistor Q2 is "1" as the positive electrode of the RLC tester 208, and the voltage V between the gate and the source of the second NMOS transistor Q2 is set to be "1"_G’S’Vth, the second NMOS transistor Q2 is turned on.

The drain potential of the second NMOS transistor Q2 is "0" as the source, and the drain potential of the first NMOS transistor Q1 is "0" as the drain potential of the second NMOS transistor Q2. Therefore, the voltage V between the gate and the source of the first NMOS transistor Q1_GS<Vth, at which time the first NMOS transistor Q1 turns off.

Referring to fig. 15, the load link length is the link length from the RLC tester 208 to the drain of the first NMOS transistor Q1, but the link length from the first host 205 to the source of the first NMOS transistor Q1 is not included, so that the signal link length is shortened, and the load capacitance can be reduced.

In order to show the beneficial effects of the present application in more detail, the load capacitance test is performed on the capacitive isolation circuit shown in fig. 10. Specifically, the voltage of the power supply 207 is 3.3V, the first pull-up resistor R1 is 4.7 kilo-ohms, the ground resistor R2 is 22 ohms, the current-limiting resistor R3 is 1 kilo-ohms, and the interface is an HDMI interface, so as to perform a load capacitance test on a CEC signal link in the HDMI. For comparison, the load capacitance test is also performed in a direct connection mode in which the first host is directly connected with the second host through the HDMI cable, and the obtained test data is shown in the following table by taking the first host as the device to be tested.

Table 1: comparison of load capacitance test data between the scheme of the application and the direct-through scheme

From the above test data it can be determined that: for each tested HDMI interface, when the tested equipment is powered on and not powered on, the load capacitance measurement result of the scheme is obviously smaller than that of the through scheme.

Therefore, the capacitive isolation circuit provided by the embodiment of the application can shorten the length of a signal link, and further reduce the load capacitance. In addition, compared with the corresponding implementation modes of fig. 1 and fig. 2, the circuit structure is simple, the hardware cost is low, and no complex signal processing chip is required to be added, so that the signal response speed is high, the power consumption is low, and no software development investment is required to be added.

In the above embodiment, the first switch circuit and the second switch circuit are both an NMOS transistor as an example. Another implementation of the first switching circuit and the second switching circuit is described below.

The third circuit embodiment:

referring to fig. 16, a schematic diagram of another capacitive isolation circuit provided in the embodiment of the present application is shown.

The first switch circuit 201 of the capacitive isolation circuit provided by the embodiment of the present application includes a first switch S1 and a first diode D1.

The anode of the first diode D1 is connected to the first terminal of the first switch S1, and the cathode of the first diode D1 is connected to the second terminal of the first switch S1.

When the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first switch S1 is closed, turning on the first terminal and the second terminal of the first switch circuit 201.

The second switch circuit 202 of the capacitive isolation circuit includes a second switch S2 and a second diode D2.

An anode of the second diode D2 is connected to the first terminal of the second switch S2, and a cathode of the second diode D2 is connected to the second terminal of the second switch S2.

When the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the voltage threshold, the second switch S2 is closed, turning on the first terminal and the second terminal of the second switch circuit 202.

The operation principle of the capacitive isolation circuit is explained in detail below.

When the second host 206 sends "1" to the first host 205, the level of the second terminal of the first switch circuit 201 is "1", and since the voltage difference between the first terminal and the second terminal of the first switch circuit 201 is a preset voltage value, the level of the first terminal of the first switch circuit 201 is "1". The control terminal of the first switch circuit 201 is pulled up to the power supply through the current limiting resistor R3, and the level is "1". Since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is smaller than the voltage threshold at this time, the first switch S1 is turned off at this time. The first pull-up circuit 203 has an enhancing effect on the first terminal signal of the first switch circuit 201, and thus the first host 205 may normally receive "1".

When the second host 206 sends "0" to the first host 205, the level of the second terminal of the first switch circuit 201 is "0", and therefore the voltage of the first terminal of the first switch circuit is equal to the predetermined voltage value, i.e. the voltage of the first terminal is a smaller voltage value and is at a low level. The control terminal of the first switch circuit 201 is pulled up to the power supply through the current limiting resistor R3, so that the level of the control terminal is "1", the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first switch S1 is turned on, and the potential of the first terminal of the first switch circuit 201 is reduced to "0", so that the first host 205 normally receives "0".

When the first host 205 sends "1" to the second host 206, the levels of the first terminal and the control terminal of the first switch circuit 201 are both "1", and since the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is smaller than the voltage threshold, the first switch S1 is turned off. At this time, the level of the second terminal of the first switch circuit 201 is also "1", so that the second host 206 can normally receive "1".

When the first host 205 sends "0" to the second host 206, the first terminal of the first switch circuit 201 is at "0" level, and the control terminal of the first switch circuit 201 is pulled up to the power supply 207 by the current limiting resistor R3, at "1" level. Because the voltage difference between the control terminal and the first terminal of the first switch circuit 201 is greater than the voltage threshold, the first switch is closed at this time, so that the level of the second terminal of the first switch circuit 201 is "0", and thus the second host can normally receive "0".

For the system applying the capacitive isolation circuit, when the load capacitance of the transmission link is tested, the first host 205 is used as the device to be tested and is not powered on, and the power supply 207 is not powered on. The positive pole of the tester is connected to the control terminal of the second switch circuit 202 through the interface 204, and the level of the control terminal of the second switch circuit 202 is "1" at this time. The negative pole of the tester is connected to the second end of the first switch circuit 201 through the interface 204, and the level is "0". At this time, the levels of the first terminal, the second terminal, and the control terminal of the first switch circuit 201 are all "0". At this time, the voltage difference between the control terminal and the first terminal of the second switch circuit 202 is greater than the voltage threshold, and the second switch S2 is closed, so that the control terminal and the first terminal of the first switch circuit 201 have the same potential, and the first switch of the first switch circuit 201 is turned off. At this time, the load link length is the link length from the tester to the second end of the first switch circuit, and the link length from the first host to the first end of the first switch circuit is not included, so that the load link length is shortened, and the load capacitance can be reduced.

In summary, the capacitive isolation circuit provided by the embodiment of the application can shorten the length of a load link and reduce the load capacitance, and meanwhile, the first pull-up circuit can guarantee the transmission quality of signals, and has the advantages of simple circuit structure, low hardware cost, no need of adding a complex signal processing chip, high signal response speed, low power consumption, and no need of adding software development investment.

The third circuit embodiment:

in the above circuit embodiment, the first pull-up circuit is connected to the first end of the first switch circuit, and is configured to enhance transmission of the signal to the first host and the signal sent by the first host to ensure transmission quality of the signal. However, in practical applications, for an application scenario where a signal transmission link is long, there may be a problem of insufficient transmission signal level, and to solve the technical problem, an embodiment of the present application further provides another capacitive isolation circuit, which is specifically described below with reference to the accompanying drawings.

Referring to fig. 17, a schematic diagram of another capacitive isolation circuit provided in an embodiment of the present application is shown.

The capacitive isolation circuit provided by the embodiment of the application is different from the circuit shown in fig. 3 in that: a second pull-up circuit 208 is also included.

The second pull-up circuit 208 is connected to the second end of the first switch circuit 201, and is used for enhancing the transmission signal at the second end side of the first switch circuit 201 to improve the signal transmission quality.

Further, in a specific application, the second pull-up circuit 201 may be implemented by a resistor, which is described below with reference to the drawings.

Referring to fig. 18, a schematic diagram of another capacitive isolation circuit provided in the embodiment of the present application is shown.

Fig. 18 is based on the implementation shown in fig. 10, and a second pull-up resistor R4 is added to the second terminal of the first switch circuit 201. The second end of the first switch circuit 201 is connected to the power supply 207 through the second pull-up resistor R4, so that signal enhancement on the second end side of the first switch circuit 201 is realized, and the quality of signal transmission is further ensured.

It can be understood that the first switch circuit and the second switch circuit in the capacitive isolation circuit are not limited to the implementation manners of the above circuit embodiments, and may also be other implementation manners meeting logic control, and the embodiments of the present application are not described herein again.

Docking station embodiment:

based on the capacitive isolation circuit provided by each circuit embodiment, the embodiment of the present application further provides a docking station, which is specifically described below with reference to the accompanying drawings.

Reference is made to fig. 19, which is a schematic diagram of a docking station according to an embodiment of the present application.

Docking station 400 includes capacitive isolation circuitry and interface 204.

The capacitive isolation circuit includes a first switch circuit 201, a second switch circuit 202, and a first pull-up circuit 203. For the specific implementation manner and the operation principle of the capacitive isolation circuit, reference may be made to the relevant description in the above embodiments, and details of the embodiments of the present application are not repeated herein.

One end of the docking station 400 is connected to the first host 205 through a cable, and the other end is connected to the second host through the interface 204, so that the signal sent by the second host 206 is sent to the first host 205 through the capacitive isolation circuit for playing.

It is understood that when the docking station 400 is connected to the first host 205, the connection may be achieved through a cable carried by the host, and at this time, the cable of the host may be detachable or not detachable. The docking station 400 may also be connected to the host through its own cable, which may be detachable or not, and this is not particularly limited in this embodiment of the application.

In addition, in practical applications, the docking station 400 may have a plurality of interfaces 204, and each interface 204 is capable of transmitting signals, that is, the docking station 400 may be connected to a plurality of hosts through the plurality of interfaces 204, respectively, and the number of the interfaces 204 is not specifically limited in this embodiment of the application. The signals transmitted by each channel interface 204 may be connected as 1 channel signal before entering the second end of the first switch circuit 201 for transmission to the first host.

In one practical application scenario of the docking station 400, the docking station 400 may be a Dock box 102 in the scenario shown in fig. 3, and is used for signal transmission between a tv host and a tv box. At this time, the interface 204 of the docking station 400 may include an HDMI interface, the docking station 400 is connected to the tv box through an HDMI cable, the HDMI cable may transmit a CEC signal, and at this time, the capacitive isolation circuit of the docking station 400 is configured to reduce a link load capacitance during transmission of the CEC signal and ensure transmission quality of the signal between the tv host and the tv box.

It is understood that, in practical applications, for better compatibility, the docking station 400 may further have different kinds of interfaces 204 to implement connection with different kinds of second hosts or match different kinds of transmission signals, and the specific kind of the interfaces 204 may be determined according to requirements of practical application scenarios, and the embodiments of the present application are not described herein one by one.

It will be appreciated that in practice, the docking station 400 itself may have no power supply, and the power supply 207 may be provided by the first host, i.e. the docking station 400 is connected to the first host 205 and then powered by the power supply on the first host 205.

In summary, the capacitive isolation circuit of the docking station includes a first switch circuit, a second switch circuit, and a first pull-up circuit. The first end of the first switch circuit is connected with the first pull-up circuit, and the first end of the first switch circuit is also connected with the first host. The second end of the first switch circuit is connected with an interface, the interface is connected with the second host, and the control end of the first switch circuit is connected with the power supply. The control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply. The voltage difference between the first end and the second end of the first switch circuit is a preset voltage value, and the value of the preset voltage value is determined to be the same level, namely the same high level or the same low level. . When the second host inputs a high level to the second end of the first switch circuit, the first end of the first switch circuit is also at the high level at the moment, and the first pull-up circuit has an enhancement effect on the signal at the first end of the first switch circuit at the moment, so that the high-level signal can be normally transmitted to the first host.

For a system applying the capacitive isolation circuit, when the load capacitance of a transmission link is tested, the anode of the tester is connected with the control end of the second switch circuit and is at a high level, and the cathode of the tester is connected with the second end of the first switch circuit through an interface and is at a low level. When the first host is the tested device and is not powered on, the power supply is not powered on at the moment, and the first end, the second end and the control end of the first switch circuit are all at low level. And the control end of the second switch circuit is connected with the anode of the tester, so that the voltage difference between the control end of the second switch circuit and the first end is greater than the voltage threshold, the first end and the second end of the second switch circuit are conducted at the moment, the control end of the first switch circuit and the first end have the same potential, and the first end and the second end of the first switch circuit are disconnected. The load link length at this time is the link length between the tester and the second end of the first switch circuit, and does not include the link length between the first host and the first end of the first switch circuit. Therefore, in practical application, the load link length can be approximate to the link length from the second host to the docking station, the shortened load link length can be approximate to the link length from the first host to the docking station, and the load capacitance can be reduced due to the fact that the load link length is greatly shortened.

Therefore, by using the docking station provided by the embodiment of the application, the length of a load link can be shortened, the load capacitance is reduced, the transmission quality of signals is guaranteed, the capacitance isolation circuit in the docking station is simple in structure, the hardware cost is low, a complex signal processing chip is not required to be added, the signal response speed is high, the power consumption is low, and the software development investment is not required to be increased.

Chip embodiment

Based on the capacitive isolation circuit described in the above embodiments, the embodiments of the present application further provide a capacitive isolation chip, which is specifically described below with reference to the accompanying drawings.

Referring to fig. 20, the figure is a schematic diagram of a capacitive isolation chip according to an embodiment of the present disclosure.

The capacitive isolation chip 300 includes: a first input output IO port IO1, a second IO port IO2, and a third IO port IO 3.

The first IO port is connected to a first host 205, and the second IO port is used to connect to a second host 206 through an interface 204.

The voltage between the first IO port and the second IO port is a preset voltage value, and the value of the preset voltage value is determined according to the principle that the voltages of the first IO port and the second IO port can be determined to be at the same level, namely, at the same high level or at the same low level.

When the voltage difference between the first IO port and the third IO port is greater than the voltage threshold, the first IO port and the second IO port are turned on, so that signals are transmitted between the first host 205 and the second host 206.

The following description is made in conjunction with specific implementations.

Referring to fig. 21, a schematic diagram of another capacitive isolation chip provided in the embodiment of the present application is shown.

The implementation of the circuit isolation chip 500 corresponds to the capacitive isolation circuit shown in fig. 10.

The first IO port, i.e. IO1, is connected to the first host 205, and the first IO port is connected to the source of the first NMOS transistor Q1, the first pull-up resistor R1, and the source of the second NMOS transistor Q2 inside the capacitive isolation chip 500.

The second IO port, i.e., IO2, is connected to the second host 206, and the second IO port is connected to the drain of the first NMOS transistor Q1 inside the capacitive isolation chip 500.

The third IO port, i.e. IO3, may be used as a power port VCC of the capacitive isolation chip 500 for connecting the power supply 207. The third IO port is connected to the source of the first NMOS transistor Q1 through a first pull-up resistor R1 inside the capacitive isolation chip 500, and is connected to the gate of the first NMOS transistor Q1 through a current limiting resistor R3.

In addition, the capacitive isolation chip 500 further includes a ground port GND connected to the gate of the second NMOS transistor Q1 through a ground resistor inside the capacitive isolation chip 500.

Referring to fig. 22, the figure is a schematic diagram of a packaged capacitive isolation chip according to an embodiment of the present application.

The packaged capacitive isolation chip has four interfaces, namely a first IO port IO1, a second IO port IO2, a third IO port IO3 (simultaneously, a power supply port VCC) and a ground port GND.

It can be understood that the above is only one implementation manner of the capacitive isolation chip, and the capacitive isolation chips corresponding to the capacitive isolation circuits shown in fig. 16 and fig. 18 are similar, and the embodiments of the present application are not described in detail herein.

The capacitive isolation chip provided by the embodiment of the application can be applied to the scenes that the signal transmission distance is long, and the load capacitance requirement cannot be met or the signal driving force cannot be met. In one possible application scenario, the capacitive isolation chip may be applied to a Dock box as shown in fig. 4, for reducing the link load capacitance between the tv host and the tv box.

In summary, the capacitive isolation circuit of the capacitive isolation chip can shorten the length of a signal link by using two switch circuits, so as to reduce the load capacitance, and meanwhile, the pull-up circuit can also play a role in signal enhancement, so that the transmission quality of signals can be guaranteed. In addition, the capacitive isolation chip is simple in structure and low in hardware cost, compared with a complex signal processing chip, the capacitive isolation chip is high in signal response speed and low in power consumption, and software development investment does not need to be increased.

The embodiment of the playing system comprises:

the embodiment of the present application further provides a playing system, which is specifically described below with reference to the accompanying drawings.

Referring to fig. 23, this figure is a schematic view of a video playing system according to an embodiment of the present application.

The playback system 600 includes a docking station 400 and a first host 205.

The first host 205 is connected to the docking station 400 through a transmission cable, the transmission cable and the first host 205 may be detachably connected or may not be detachably connected, and the transmission cable and the docking station 400 may be detachably connected or may not be detachably connected, which is not specifically limited in this embodiment of the application.

The docking station 400 transmits a signal transmitted by the second host 206 to the first host 205 to cause the first host 205 to play the corresponding content.

The following description will specifically take a television broadcasting system as an example.

For a television playing system, a television host is connected with a video source host through an HDMI cable, and when an HDMI link is long, a link load capacitor of a CEC signal transmitted on the HDMI link cannot meet the standard requirement of the link load capacitor, so that the television host cannot normally receive the signal.

With continued reference to the scenario shown in fig. 4, when the playing system provided in the embodiment of the present application is applied, the first host is a television host, and the second host is a video source host, that is, a television box. The docking station 400 (i.e., Dock box) is now used to send the content sent by the video source host to the tv host for playing by the tv host.

The application provides an inside electric capacity buffer circuit that includes of docking station, based on the explanation of above embodiment, utilize this electric capacity buffer circuit back load link length to be the link length between second host computer to electric capacity buffer circuit's the first switch circuit second end, link length between the first host computer to first switch circuit's the first end has not been included, consequently, load link length can be shortened, reduce load capacitance, simultaneously can ensure the transmission quality of signal, and then ensured that the TV host computer of play system can normally play the content that the video source host computer sent.

It should be understood that in the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" for describing an association relationship of associated objects, indicating that there may be three relationships, e.g., "a and/or B" may indicate: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application in any way. Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application. Those skilled in the art can now make numerous possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the claimed embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still fall within the protection scope of the technical solution of the present application without departing from the content of the technical solution of the present application.

Claims

1. A capacitive isolation circuit, comprising: a first switch circuit, a second switch circuit and a first pull-up circuit;

the first end of the first switch circuit is connected with the first pull-up circuit, and the first end of the first switch circuit is also used for connecting a first host;

the second end of the first switch circuit is used for connecting an interface; the interface is used for connecting a second host;

the control end of the first switch circuit is connected with a power supply;

the control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply;

the voltage difference between the first end and the second end of the first switch circuit is a preset voltage value, and the preset voltage value is used for ensuring that the level states of the first end and the second end of the first switch circuit are consistent, so that the voltages of the first end and the second end of the first switch circuit are judged to be the same level;

when the voltage difference between the control end and the first end of the first switch circuit is greater than the voltage threshold, the first end and the second end of the first switch circuit are conducted; and when the voltage difference between the control end and the first end of the second switch circuit is greater than the voltage threshold, the first end and the second end of the second switch circuit are conducted.

2. The circuit of claim 1, wherein the first pull-up circuit comprises: a first pull-up resistor;

the first end of the first switch circuit is connected with the power supply through the first pull-up resistor.

3. The circuit of claim 1, wherein the first switch circuit is a first NMOS transistor, the first terminal of the first switch circuit is a source of the first NMOS transistor, the second terminal of the first switch circuit is a drain of the first NMOS transistor, and the control terminal of the first switch circuit is a gate of the first NMOS transistor.

4. The circuit of claim 1, wherein the second switch circuit is a second NMOS transistor, the first terminal of the second switch circuit is a source of the second NMOS transistor, the second terminal of the second switch circuit is a drain of the second NMOS transistor, and the control terminal of the second switch circuit is a gate of the second NMOS transistor.

5. The circuit of claim 1, wherein the first switching circuit comprises a first switch and a first diode;

the anode of the first diode is connected with the first end of the first switch, and the cathode of the first diode is connected with the second end of the first switch.

6. The circuit of claim 1, wherein the second switching circuit comprises a second switch and a second diode;

the anode of the second diode is connected with the first end of the second switch, and the cathode of the second diode is connected with the second end of the second switch.

7. The circuit of any of claims 1-6, further comprising: a protection circuit;

the control end of the second switch circuit is grounded through the protection circuit;

the protection circuit is used for filtering interference signals.

8. The circuit of claim 7, wherein the protection circuit comprises: a ground resistor;

and the control end of the second switch circuit is grounded through the grounding resistor.

9. The circuit of any of claims 1-6, further comprising: a current limiting resistor;

and the control end of the first switch circuit is connected with the power supply through the current-limiting resistor.

10. The circuit of any of claims 1-6, further comprising: a second pull-up circuit;

and the second end of the first switch circuit is connected with the second pull-up circuit.

11. The circuit of claim 10, wherein the second pull-up circuit comprises: a second pull-up resistor;

the second end of the first switch circuit is connected with the power supply through the second pull-up resistor.

12. A docking station comprising the capacitive isolation circuit of any of claims 1-11, further comprising: an interface;

the interface is used for connecting a second host and sending a signal sent by the second host to the first host through the capacitive isolation circuit.

13. The docking station of claim 12, wherein the interface is a High Definition Multimedia Interface (HDMI) interface.

14. A capacitive isolation chip, comprising: the first switch circuit, the second switch circuit, the first pull-up circuit, the first input/output IO port, the second IO port and the third IO port; the first end of the first switch circuit is connected with the first pull-up circuit, and the first end of the first switch circuit is also used for connecting a first host; the second end of the first switch circuit is used for connecting an interface; the interface is used for connecting a second host; the control end of the first switch circuit is connected with a power supply; the control end of the second switch circuit is grounded, the first end of the second switch circuit is connected with the first end of the first switch circuit, and the second end of the second switch circuit is connected with the power supply; the voltage difference between the first end and the second end of the first switch circuit is a preset voltage value, and the preset voltage value is used for ensuring that the level states of the first end and the second end of the first switch circuit are consistent, so that the voltages of the first end and the second end of the first switch circuit are judged to be the same level; when the voltage difference between the control end and the first end of the first switch circuit is greater than the voltage threshold, the first end and the second end of the first switch circuit are conducted; when the voltage difference between the control end and the first end of the second switch circuit is greater than the voltage threshold, the first end and the second end of the second switch circuit are conducted;

a first end of the first switch circuit is connected with the first IO port, and a second end of the first switch circuit is connected with the second IO port; the control end of the first switch circuit is connected with the third IO port;

the first IO port is used for connecting a first host;

the second IO port is used for connecting a second host through an interface;

the voltage difference between the first IO port and the second IO port is a preset voltage value, and the preset voltage value is used for enabling the level states between the first IO port and the second IO port to be consistent;

when the voltage difference between the first IO port and the third IO port is larger than a voltage threshold, the first IO port and the second IO port are conducted, so that signals are transmitted between the first host and the second host.

15. A playback system comprising the docking station of claim 12 or 13, and further comprising: a first host;

the first host is connected with the docking station through a transmission cable;

the docking station is used for sending the signal sent by the second host to the first host;

and the first host is used for playing the content corresponding to the signal sent by the second host.