CN104202631A - MHL-USB (mobile high-definition link and universal serial bus) joint circuit and portable electronic device - Google Patents
MHL-USB (mobile high-definition link and universal serial bus) joint circuit and portable electronic device Download PDFInfo
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Abstract
The invention provides an MHL-USB (mobile high-definition link and universal serial bus) joint circuit and a portable electronic device. The MHL-USB joint circuit comprises a micro USB interface, a USB transceiver and a MHL transmitter. The micro USB interface comprises a first data terminal and a second data terminal. The USB transceiver comprises a first current source, transistors M1 and M5, a first resistor, transistors M2 and M6 and a second resistor; the first current source is connected to a power supply and a first node; the transistors M1 and M5 and the first resistor are serially connected to the first node and a ground terminal in order; the transistors M2 and M6 and the second resistor are serially connected to the first node and the ground terminal in order; gates of the transistors M1 and M2 are connected with a pair of high-speed differential data signals; a first connecting terminal of the transistor M5 is connected with the first data terminal; a first connecting terminal of the transistor M6 is connected with the second data terminal; gates of the transistors M5 and M6 are connected with an enable signal. The MHL transmitter comprises a second current source, a transistor M9 and a transistor M10; the second current source is connected to a second node and the ground terminal; the transistor M9 is serially connected to the first data terminal and the second node in order; the transistor M10 is serially connected to the second data terminal and the second node in order; gates of the transistors M9 and M10 are connected with pair of MHL differential data signals. Compared with the prior art, the MHL-USB joint circuit and the portable electronic device have the advantages that the MHL transmitter is allowed to multiplex the micro USB interface.
Description
[technical field]
The present invention relates to circuit design field, particularly a kind of MHL and USB joint circuit, portable electric appts.
[background technology]
MHL (Mobile High-Definition Link, mobile terminal high-definition audio and video standard interface) is a kind of audio-visual standard interface that connects portable consumer electronic device.MHL is only used a bars cable, by MHL/HDMI (High Definition Multimedia Interface, HDMI (High Definition Multimedia Interface)) interface, just can be presented in HDTV (High-Definition Television).It has used existing Micro USB interface, just can the media content of mobile phone, digital camera, digital camera and portable media player is directly transferred on TV and not damage the high-resolution effect of film.
MHL is to realize by increasing MHL transmitting chip and analog switch by the scheme of Micro USB interface output high-definition multimedia content.This scheme has reused Micro USB connector, and can normally use USB function.Existing MHL scheme need to by one independently analog switch chip maybe this analog switch is integrated in MHL emitter chip, this scheme has increased the cost that system realizes.
Therefore, be necessary to provide a kind of improved technical scheme to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of MHL and USB joint circuit, portable electric appts, it not only can realize the multiplexing micro USB interface of MHL reflector, but also the cost of can reduction system realizing.
In order to address the above problem, according to an aspect of the present invention, the invention provides a kind of MHL and USB joint circuit, it comprises: micro USB interface, USB transceiver and MHL reflector.Described micro USB interface comprises the first data terminal D+ and the second data terminal D-.Described USB transceiver comprises USB high speed output unit, and described USB high speed output unit comprises: the first current source, and it is connected between power end and first node, and the sense of current of the first current source is for to flow to first node by power end, be series at successively transistor M1, M3, M5 and the first resistance between first node and earth terminal, be series at successively transistor M2, M4, M6 and the second resistance between first node and earth terminal, the grid of the grid of transistor M1 and transistor M2 is connected with a pair of high-speed-differential data-signal that described USB transceiver produces respectively, the first link of transistor M5 is connected with described the first data terminal D+, the second link of transistor M5 is connected with the first resistance, the first link of transistor M6 is connected with described the second data terminal D-, the second link of transistor M6 is connected with the second resistance, after being connected, the grid of the grid of transistor M3 and transistor M4 is connected with USB high-speed control signal, after being connected, the grid of the grid of transistor M5 and transistor M6 is connected with enable signal.Described MHL reflector comprises MHL output unit, and described MHL output unit comprises: the second current source, and it is connected between Section Point and earth terminal, and the sense of current of this second current source is for to flow to earth terminal by Section Point; Be series at successively transistor M7 and M9 between the first data terminal D+ and Section Point: be series at successively transistor M8 and M10 between the second data terminal D-and Section Point; The grid of the grid of transistor M9 and transistor M10 is connected with a pair of MHL differential data signals that MHL reflector produces respectively, after the grid of the grid of transistor M7 and transistor M8 is connected, is connected with MHL emissioning controling signal.
Further, the first link of transistor M1 is connected with first node, the second link of transistor M1 is connected with the first link of transistor M3, the second link of transistor M3 is connected with the first link of transistor M5, and the second link of transistor M5 is connected with earth terminal GND by the first resistance; The first link of transistor M2 is connected with first node, the second link of transistor M2 is connected with the first link of transistor M4, the second link of transistor M4 is connected with the first link of M6, and the second link of transistor M6 is connected with earth terminal GND by the second resistance; The first link of transistor M7 is connected with the first data terminal D+, and the second link of transistor M7 is connected with the first link of transistor M9, and the second link of transistor M9 is connected with Section Point; The first link of transistor M8 is connected with the second data terminal D-, and the second link of transistor M8 is connected with the first link of transistor M10, and the second link of transistor M10 is connected with Section Point.
Further, at described MHL and USB joint circuit during in USB high speed operation pattern, MHL emissioning controling signal is the first logic level, to control M7 and M8 cut-off, USB high-speed control signal is that the second logic level is controlled M3 and M4 conducting, to open described USB high speed output unit, after MHL and USB joint circuit and the outside USB device of inserting described micro USB interface complete and shake hands, when enable signal is the second logic level, make M5 and M6 conducting, make the work of described USB high speed output unit, described MHL and USB joint circuit are when the USB of non-high speed mode of operation, USB high-speed control signal is that the first logic level is to control M3 and M4 cut-off, and EN signal is the first logic level, make M5 and M6 cut-off, to close USB high speed output unit, MHL emissioning controling signal is the first logic level, to control M7 and M8 cut-off, at described MHL and USB joint circuit during in MHL mode of operation, USB high-speed control signal is the first logic level, to control M3 and M4 cut-off, and enable signal is the first logic level, make M5 and M6 cut-off, to close USB high speed output unit, MHL emissioning controling signal is that the second logic level is controlled M7 and M8 conducting, to open described MHL output unit.
According to an aspect of the present invention, the invention provides another kind of MHL and USB joint circuit, it comprises: micro USB interface, USB transceiver and MHL reflector.Described micro USB interface comprises the first data terminal D+ and the second data terminal D-.Described USB transceiver comprises USB high speed output unit, and described USB high speed output unit comprises: the first current source, and it is connected between power end and first node, and the sense of current of the first current source is for to flow to first node by power end; Be series at successively transistor M1, M5 and the first resistance between first node and earth terminal; Be series at successively transistor M2, M6 and the second resistance between first node and earth terminal; The grid of the grid of transistor M1 and transistor M2 is connected with a pair of high-speed-differential data-signal that described USB transceiver produces respectively, the first link of transistor M5 is connected with described the first data terminal D+, the second link of transistor M5 is connected with the first resistance, the first link of transistor M6 is connected with described the second data terminal D-, the second link of transistor M6 is connected with the second resistance, after the grid of the grid of transistor M5 and transistor M6 is connected, is connected with enable signal.Described MHL reflector comprises MHL output unit, and described MHL output unit comprises: the second current source, and it is connected between Section Point and earth terminal, and the sense of current of this second current source is for to flow to earth terminal by Section Point; Be series at successively the transistor M9 between the first data terminal D+ and Section Point: be series at successively the transistor M10 between the second data terminal D-and Section Point; The grid of the grid of transistor M9 and transistor M10 is connected with a pair of MHL differential data signals that MHL reflector produces respectively.
Further, the first link of transistor M1 is connected with first node, and the second link of transistor M1 is connected with the first link of transistor M5, and the second link of transistor M5 is connected with earth terminal GND; The first link of transistor M2 is connected with first node, and the second link of transistor M2 is connected with the first link of transistor M6, and the second link of transistor M6 is connected with earth terminal GND.
Further, at described MHL and USB joint circuit during in USB high speed operation pattern, MHL differential data signals is locked into the first logic level, control M9 and M10 cut-off, thereby close described MHL output unit, after MHL and USB joint circuit and the outside USB device of inserting described micro USB interface complete and shake hands, when enable signal is the second logic level, make M5 and M6 conducting, make the work of described USB high speed output unit; Described MHL and USB joint circuit are when the USB of non-high speed mode of operation, MHL differential data signals is locked into the first logic level, control M9 and M10 cut-off, thereby close described MHL output unit, USB high-speed-differential data-signal is all locked as the first logic level, controls M1 and M2 cut-off, and enable signal is the first logic level, control M5 and M6 cut-off, close UBS high speed output unit; At described MHL and USB joint circuit, during in MHL mode of operation, USB high-speed-differential data-signal is all locked as the first logic level, controls M1 and M2 cut-off, and enable signal is the first logic level, controls M5 and M6 cut-off, closes UBS high speed output unit.
Further, the a pair of high-speed-differential data-signal that described USB transceiver produces and USB high-speed control signal are connected with the grid of transistor M2 with the grid of transistor M1 through logical circuit, when described USB high-speed control signal is the second logic level, the conducting of transistor M1 and M2 or cut-off are determined by described a pair of high-speed-differential data-signal, when described USB high-speed control signal is the first logic level, transistor M1 and M2 end.
Further, the a pair of MHL differential data signals that MHL reflector produces and MHL emissioning controling signal are connected with the grid of transistor M10 with the grid of transistor M9 through logical circuit, when described MHL emissioning controling signal is the second logic level, the conducting of transistor M9 and M10 or cut-off are determined by described a pair of MHL differential data signals, when described USB high-speed control signal is the first logic level, transistor M9 and M10 end.
Further, described transistor is nmos pass transistor, and described the first link is drain electrode, and described the second link is source electrode, and described the first logic level is low level, and described the second logic level is high level; Or described transistor is PMOS transistor, described the first link is source electrode, and described the second link is drain electrode, and described the first logic level is high level, and described the second logic level is low level.
Further, so MHL and USB joint circuit are formed on same wafer.
According to another aspect of the present invention, the invention provides a kind of portable electric appts, it comprises MHL and USB joint circuit, and described MHL and USB joint circuit comprise: micro USB interface, USB transceiver and MHL reflector.Described micro USB interface comprises the first data terminal D+ and the second data terminal D-.Described USB transceiver comprises USB high speed output unit, and described USB high speed output unit comprises: the first current source, and it is connected between power end and first node, and the sense of current of the first current source is for to flow to first node by power end, be series at successively transistor M1, M3, M5 and the first resistance between first node and earth terminal, be series at successively transistor M2, M4, M6 and the second resistance between first node and earth terminal, the grid of the grid of transistor M1 and transistor M2 is connected with a pair of high-speed-differential data-signal that described USB transceiver produces respectively, the first link of transistor M5 is connected with described the first data terminal D+, the second link of transistor M5 is connected with the first resistance, the first link of transistor M6 is connected with described the second data terminal D-, the second link of transistor M6 is connected with the second resistance, after being connected, the grid of the grid of transistor M3 and transistor M4 is connected with USB high-speed control signal, after being connected, the grid of the grid of transistor M5 and transistor M6 is connected with enable signal.Described MHL reflector comprises MHL output unit, and described MHL output unit comprises: the second current source, and it is connected between Section Point and earth terminal, and the sense of current of this second current source is for to flow to earth terminal by Section Point; Be series at successively transistor M7 and M9 between the first data terminal D+ and Section Point: be series at successively transistor M8 and M10 between the second data terminal D-and Section Point; The grid of the grid of transistor M9 and transistor M10 is connected with a pair of MHL differential data signals that MHL reflector produces respectively, after the grid of the grid of transistor M7 and transistor M8 is connected, is connected with MHL emissioning controling signal.
Compared with prior art, in the present invention, MHL reflector and USB transceiver are integrated in same chip, by the MOS switch of controlling in this chip, realize the multiplexing micro USB interface of MHL reflector, thus the cost that reduction system realizes.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1 is the circuit diagram of the present invention's portable electric appts in one embodiment;
Fig. 2 is the present invention MHL in one embodiment and the circuit diagram of USB joint circuit;
Fig. 3 is MHL output unit and the USB high speed output unit circuit diagram in one embodiment in the present invention;
Fig. 4 is MHL output unit and the USB high speed output unit circuit diagram in another embodiment in the present invention;
Fig. 5 is MHL output unit and the circuit diagram of USB high speed output unit in the 3rd embodiment in the present invention;
Fig. 6 is MHL output unit and the circuit diagram of USB high speed output unit in the 4th embodiment in the present invention;
Fig. 7 is MHL output unit and the circuit diagram of USB high speed output unit in the 5th embodiment in the present invention.
[embodiment]
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Due to existing MHL scheme need to by one independently analog switch chip maybe this analog switch is integrated in MHL emitter chip, then on pcb board, by wiring, be connected with USB transponder chip (or thering is other chip that is integrated with USB function), this scheme has increased the design difficulty of analog switch chip or MHL transceiver, therefore the present invention is integrated in the transceiver of MHL reflector and USB in same chip, by the MOS switch of controlling in this chip, realize the multiplexing micro USB interface of MHL reflector, thereby when simplifying circuit design, also reduced the cost that system realizes.
Please refer to shown in Fig. 1, it is the circuit diagram of the present invention's portable electric appts 1 in one embodiment.Described portable electric appts 1 can be smart mobile phone, can be also panel computer, also can notebook computer etc. other electronic equipments.In described portable electric appts 1, include micro USB (Universal Serial Bus) interface 110, MHL and USB joint circuit 10 and microprocessor 20.
Described micro usb 1 10 comprises five terminals, is respectively power supply terminal VDD, the first data terminal D+, the second data terminal D-, detection terminal ID and earth terminal GND.
Described MHL and USB joint circuit 10 and the first data terminal D+, the second data terminal D-is connected with detection terminal ID.Described USB joint circuit 10 has determined whether that by the level signal on judgement detection terminal ID equipment inserts micro usb 1 10, insertion be USB device, or MHL equipment.Concrete, the detection terminal ID of described micro usb 1 10 is connected to supply voltage VCC by resistance R 10 (not shown), such as 1.8V, is not having equipment to insert micro usb 1 10, and described detection terminal ID is pulled to supply voltage VCC.The terminal corresponding with described detection terminal ID of USB device is directly grounded, and therefore, if USB device is inserted, the level on so described detection terminal ID will be pulled down to ground level.The terminal corresponding with described detection terminal ID of MHL equipment is by resistance R 20 (not shown) ground connection, if there is MHL equipment to insert, the level on described detection terminal ID is by a scheduled voltage between VCC and GND.Therefore, the level situation based on described detection terminal ID, the equipment that can determine whether inserts micro usb 1 10, and further determines that what insert is USB device, or MHL equipment.
When described MHL and USB joint circuit 10 are determined with MHL equipment and insert, it informs microprocessor 20 by this situation, by the microprocessor 20 described MHL of indication and USB joint circuit 10, enters MHL mode of operation.When described MHL and USB joint circuit 10 are determined with USB device and insert, it informs microprocessor 20 by this situation, by the microprocessor 20 described MHL of indication and USB joint circuit 10, enters USB mode of operation.In a preferred embodiment, described MHL and USB joint circuit 10 acquiescences are operated in USB mode of operation, when having MHL equipment to insert, by the microprocessor 20 described MHL of indication and USB joint circuit 10, from USB mode of operation, enter MHL mode of operation.Wherein USB mode of operation specifically also includes USB high speed operation pattern, and USB full speed operation pattern and USB local-speed mode of operation, according to the type of inserting the USB device of micro USB interface, are selected suitable USB mode of operation.
Certainly, in some embodiments, described microprocessor 20 also directly the level signal based on described detection terminal ID determined whether that equipment inserts micro usb 1 10, insertion be USB device, or MHL equipment, and then carry out corresponding operation.
Described MHL and USB joint circuit 10, for can support USB transmission-receiving function, also can be supported MHL sending function.Preferably, described MHL and USB joint circuit 10 are chip piece, except reducing hardware or line expense, have greatly improved the quality of signal transmission.The output signal of MHL reflector can share a pad (PAD), pressure welding line or package pins (pin) with the respective signal of USB2.0, reduced total chip package testing cost and the parasitic load effect of system, and the quality that has improved system signal transmission.The most key is, this scheme of the present invention no longer needs to be arranged at the analog switch between USB transceiver and MHL reflector and micro usb 1 10, when simplifying circuit design, also reduced like this cost that system realizes, can also eliminate the noise jamming to USB transmission bandwidth and MHL transport tape broadband of being brought by the setting of analog switch simultaneously.
Fig. 2 is the present invention MHL in one embodiment and the circuit diagram of USB joint circuit.Described MHL and USB joint circuit include USB transceiver 12 and MHL reflector 13.Wherein, described USB transceiver 12 comprises USB transmitting-receiving control unit and USB high speed output unit.Need to know, for clear, the little module of other property related to the present invention that USB transceiver 12 comprises, such as USB, output unit, USB receive relevant circuit and are not drawn in figure at full speed.Described USB transmitting-receiving control unit forms USB output data according to usb protocol, receives the USB input data that transmit.Described USB high speed output unit will be gone out from the transfer of data of USB transmitting-receiving control unit.Described MHL reflector 13 comprises MHL emission controlling unit and MHL output unit.Described MHL emission controlling unit forms MHL output data according to MHL agreement.Described MHL output unit will be gone out from the transfer of data of MHL emission controlling unit.
Please refer to shown in Fig. 3, it is MHL output unit and USB high speed output unit circuit diagram in one embodiment in the present invention.In this example, described MHL output unit is marked as 132, and described USB high speed output unit is marked as 122.
Described USB high speed output unit 122 comprises the first current source I1, nmos pass transistor M1, M2, M3, M4, M5, M6, the first resistance R 1 and the second resistance R 2.Wherein, the input of the first current source I1 is connected with power end VDD, and its output is connected with first node O1, and the sense of current of this first current source I1 is for to flow to first node O1 by power end VDD; Nmos pass transistor M1, M3, M5 and the first resistance R 1 are series between first node O1 and earth terminal GND successively.Be specially, the drain electrode of M1 is connected with first node O1, and the source electrode of M1 is connected with the drain electrode of M3, and the source electrode of M3 is connected with the drain electrode of M5, and the source electrode of M5 is connected with earth terminal GND by the first resistance R 1.Nmos pass transistor M2, M4, M6 and the second resistance R 2 are series between first node O1 and earth terminal GND successively.Be specially, the drain electrode of M2 is connected with first node O1, and the source electrode of M2 is connected with the drain electrode of M4, and the source electrode of M4 is connected with the drain electrode of M6, and the source electrode of M6 is connected with earth terminal GND by the second resistance R 2; The grid of nmos pass transistor M1 and the grid of M2 are respectively as the first data input pin and second data input pin of described USB high speed output unit 122, it (is differential signal usb_hs_data+ and usb_hs_data-that this first data input pin and the second data input pin are respectively used to receive a pair of USB high-speed-differential data-signal that described USB transceiver 12 produces, the amplitude of these two signals equates, single spin-echo).The drain electrode of nmos pass transistor M5 is connected as the first data output end of described USB high speed output unit 122 and the first data terminal D+ of described usb 1 10, and the drain electrode of nmos pass transistor M6 is connected as the second data output end of described USB high speed output unit 122 and the second data terminal D-of described usb 1 10.After the grid of nmos pass transistor M3 is connected with the grid of M4 as the control end of described USB high speed output unit 122, this control end receives USB high-speed control signal USB_HS_CTL, and based on this USB_HS_CTL signal controlling M3 and M4 conducting simultaneously or cut-off, thereby control, open or close USB high speed output unit 122.After the grid of nmos pass transistor M5 is connected with the grid of M6 as the Enable Pin EN of described USB high speed output unit 122, the enable signal that this Enable Pin EN receives based on it is controlled M5 and M6 conducting simultaneously or cut-off, after opening at USB high speed output unit 122, enable or disable USB high speed output unit 122.
Described MHL output unit 132 comprises the second current source I2, nmos pass transistor M7, M8, M9 and M10.Wherein, the input of the second current source I2 is connected with Section Point O2, and its output is connected with earth terminal GND, and the sense of current of this second current source I2 is for to flow to earth terminal GND by Section Point O2; Nmos pass transistor M7 and M9 are series between the first data terminal D+ and Section Point O2 successively.Be specially, the drain electrode of M7 is connected with the first data terminal D+ as the first data output end of MHL output unit 132, and the source electrode of M7 is connected with the drain electrode of M9, and the source electrode of M9 is connected with Section Point O2; Nmos pass transistor M8 and M10 are series between the second data terminal D-and Section Point O2 successively, be specially, the drain electrode of M8 is connected with the second data terminal D-as the second data output end of MHL output unit 132, and the source electrode of M8 is connected with the drain electrode of M10, and the source electrode of M10 is connected with Section Point O2; The grid of nmos pass transistor M9 and the grid of M10 are respectively as the first data input pin and second data input pin of MHL output unit 132, it (is differential signal MHL_data+ and MHL_data-that this first data input pin and the second data input pin are respectively used to receive a pair of MHL differential data signals that MHL reflector 13 produces, the amplitude of these two signals equates, single spin-echo); After the grid of nmos pass transistor M7 is connected with the grid of M8 as the control end of MHL output unit 132, this control end receives MHL emissioning controling signal MHL_TX_CTL, and based on this MHL_TX_CTL signal controlling M7 and M8 conducting simultaneously or cut-off, thereby control the unlatching of MHL output unit 132 or close.
For the ease of understanding, below based on Fig. 3, specifically introduce operation principle of the present invention.Wherein, comprise that the portable set of the MHL output unit 132 shown in Fig. 3 and USB high speed output unit 122 is called as main equipment, the equipment being connected with main equipment by described usb 1 10 is called ancillary equipment.
When ancillary equipment is USB device, and when micro usb 1 10 in main equipment is connected, described MHL controlled by the microprocessor 20 of main equipment and USB joint circuit enters USB mode of operation, now, MHL_TX_CTL signal is that the first logic level (it is low level) is ended to control M7 and M8, thereby closes described MHL output unit 132 (closing MHL reflector 130).Further, if ancillary equipment is for supporting the USB device of fast mode, the CPU of main equipment controls described MHL and USB joint circuit enters USB high speed operation pattern, now, controlling USB_HS_CTL signal is the second logic level (it is high level), to control M3 and M4 conducting, thereby open described USB high speed output unit 122 (opening the USB fast mode of USB transceiver 12), to realize shaking hands of main equipment and ancillary equipment.Shaking hands when successful, EN signal just can become the second logic level (it is high level), make M5 and M6 conducting, like this, the first resistance R 1 and the second resistance R 2 are communicated with the first data output end and second data output end of described USB high speed output unit 122 respectively, described USB high speed output unit 122 is started working, thereby make the USB in main equipment enter USB high-speed transfer pattern (now, the first data terminal D+ and the second data terminal D-are respectively as the first data output interface USB_DP and the second data output interface USB_DPUSB_DM of described USB high speed output unit 122).When shaking hands failure, EN signal is the first logic level (it is low level), makes M5 and M6 cut-off, and described USB high speed output unit 122 is not worked.If ancillary equipment is while not supporting the USB device of fast mode, making USB_HS_CTL signal is the first logic level (it is low level), to control M3 and M4 cut-off, and EN signal is the first logic level (it is low level), make M5 and M6 cut-off, thereby close (or not starting) USB high speed output unit 122, now, main equipment need to start the USB pattern matching with ancillary equipment, such as, when ancillary equipment is low speed USB device, main equipment need to start USB local-speed mode of operation, when the full speed USB device of ancillary equipment, main equipment need to start USB full speed operation pattern, thereby realize the smooth transmission of data-signal.
When ancillary equipment is MHL equipment, and when micro usb 1 10 in main equipment is connected, the CPU of main equipment controls described MHL and USB joint circuit enters MHL mode of operation, now, USB_HS_CTL signal is the first logic level (it is low level), and to control M3 and M4 cut-off, and EN signal is the first logic level (it is low level), make M5 and M6 cut-off, thereby close (or not starting) USB high speed output unit 122; MHL_TX_CTL signal is the second logic level (it is high level), to control M7 and M8 conducting, thereby open described MHL output unit 132 (opening MHL reflector 13), make micro usb 1 10 as the output interface of MHL reflector 13 (now, the first data terminal D+ and the second data terminal D-are respectively as the first data output interface MHL_DP and the second data output interface MHL_DPUSB_DM of described MHL output unit 132), thus make the ancillary equipment of 10 pairs of HDMI interfaces of the multiplexing micro usb 1 of MHL reflector 13 carry out MHL transfer of data.
That is to say, in Fig. 3, be high level at USB_HS_CTL signal, and EN signal is high level, when MHL_TX_CTL signal is low level, realizes USB2.0 fast mode function; At USB_HS_CTL signal, be low level, EN signal is low level, when MHL_TX_CTL signal is high level, realizes MHL function; When other pattern of USB2.0, USB_HS_CTL signal, EN signal and MHL_TX_CTL signal are all low level.
In summary, the present invention integrates the reflector of MHL 13 and USB transceiver 12, by internal chip enable signal, control conducting and/or the cut-off that is arranged at a plurality of MOS transistor in MHL output unit 132 and USB high speed output unit 122, to control the unlatching of MHL output unit 132 and USB high speed output unit 122 or to close, thereby distinguish the different application (realizing the micro usb 1 10 of MHL reflector 13 multiplexing USB transceivers 12) of MHL or USB, thereby reduced extra analog switch chip (or no longer needing analog switch chip to be integrated in MHL emitter chip), design difficulty and the chip cost of MHL reflector have been reduced, and reduced the line of PCB, and then reduced the cost of realizing of system.In addition, the present invention has also greatly improved the quality of signal transmission, such as, the output signal of the reflector 13 of MHL can share a pad (PAD), pressure welding line or package pins (pin) with the fast mode output signal of USB2.0, thereby not only reduced total chip package testing cost and the parasitic load effect of system, and improved the quality of system signal transmission.
It should be noted that, the nmos pass transistor M1-M10 in Fig. 3 can replace with PMOS transistor in whole or in part, replaces with after PMOS transistor, and the level of the control signal that its grid is corresponding also will change accordingly.Please refer to shown in Fig. 4, it is MHL output unit and USB high speed output unit circuit diagram in another embodiment.In this example, described MHL output unit is marked as 232, and described USB high speed output unit is marked as 222.The operation principle of Fig. 4 is identical with Fig. 3, its difference is, by the nmos pass transistor M1-M10 in Fig. 4, all replaces with PMOS transistor M1 '-M10 ', the first logic level of corresponding USB_HS_CTL signal becomes high level, and the second logic level becomes low level; The first logic level of EN signal becomes high level, and the second logic level becomes low level; The first logic level of MHL_TX_CTL becomes high level, and the second logic level becomes low level.
Please refer to shown in Fig. 5, it is MHL output unit and the circuit diagram of USB high speed output unit in the 3rd embodiment.In this example, described MHL output unit is marked as 332, and described USB high speed output unit is marked as 322.The difference of Fig. 5 and Fig. 3 is, has omitted M3 and M4, and M7 and M8.Owing to having omitted M3 and M4, and M7 and M8.When 322 work of USB high speed output unit, MHL_data-and MHL_data+ are locked into low level, make M9 and M10 always in cut-off state, be equivalent to MHL output unit 332 in off position, to avoid 332 pairs of USB high speed output units 322 of MHL output unit to impact.Same, when 332 work of MHL output unit, usb_hs_data+ and usb_hs_data-are locked into low level, EN is locked into low level, M1, M2, M5, M6 end, be equivalent to USB high speed output unit 322 in off position, to avoid 322 pairs of MHL output units 332 of USB high speed output unit to impact.
The function identical with Fig. 3 (realizing the micro USB interface of MHL reflector 13 multiplexing USB transceivers 12) that embodiment shown in Fig. 5 realizes, but it needs MOS transistor still less than Fig. 3, thus simplify circuit design, reduction system realizes cost.
It should be noted that, nmos pass transistor M1, M2, M5, M6, M9 and the M10 in Fig. 5 can replace with PMOS transistor in whole or in part, replaces with after PMOS transistor, and the level of the control signal that its grid is corresponding also will change accordingly.Please refer to shown in Fig. 6, it is MHL output unit of the present invention and the circuit diagram of USB high speed output unit in the 4th embodiment.In this example, described MHL output unit is marked as 432, and described USB high speed output unit is marked as 422.The operation principle of Fig. 6 is identical with Fig. 5, its difference is, by nmos pass transistor M1, M2, M5, M6, M9 and M10 in Fig. 5, all replace with PMOS transistor M1 ', M2 ', M5 ', M6 ', M9 ' and M10 ', accordingly, when USB device that ancillary equipment is fast mode and when microUSB interface in main equipment is connected, the grid of M9 ' and the grid of M10 ' are all that it is high level, to control M9 ' and M10 ' cut-off; When USB device that ancillary equipment is non-fast mode, the grid of M1 ' and the grid of M2 ' are all high level, to control M1 ' and M2 ' cut-off.When ancillary equipment is MHL equipment and when micro usb 1 10 in main equipment is connected, the grid of M1 ' and the grid of M2 ' are all high level, to control M1 ' and M2 ' cut-off; EN signal is high level, M5 ' and M6 ' cut-off.
In addition, can only omit M3 and M4 in other embodiments, or M7 and M8.
Please refer to shown in Fig. 7, it is MHL output unit and the circuit diagram of USB high speed output unit in the 5th embodiment.In this example, described MHL output unit is marked as 532, and described USB high speed output unit is marked as 522.The difference of Fig. 7 and Fig. 3 is, M3 and M4 have been omitted, increase logical circuit 540 simultaneously, described USB high-speed-differential data-signal usb_hs_data+ and usb_hs_data-, and USB high-speed control signal USB_HS_CTL is connected to respectively an input of described logical circuit 540, two outputs of described logical circuit 540 are connected with the grid of M1 and M2 respectively.When USB_HS_CTL signal is the second logic level (it is high level), usb_hs_data+ and usb_hs_data-are connected to the grid of M1 and M1, when USB_HS_CTL signal is the first logic level (it is low level), usb_hs_data+ and usb_hs_data-can not be connected to the grid of M1 and M2, now M1 and M2 cut-off.USB_HS_CTL signal has been realized the control to USB high speed output unit by logical circuit 540 like this.
Need to be appreciated that, it can be to be directly connected that the grid of described M1 and M2 is connected with usb_hs_data-with usb_hs_data+, as shown in Figure 3, can be to be also indirectly connected, and as shown in Figure 7, through logical circuit 540, connects.
Same principle, a kind of change as MHL output unit of the present invention and USB high speed output unit becomes, also can omit transistor M7 and M8, and MHL_TX_CTL, MHL_data-and MHL_data+ are connected to a logical circuit, the company of a logical circuit output connects the grid of M9 and M10, and MHL_data-and MHL_data+ belong to the grid that is indirectly connected to M9 and M10 by logical circuit like this.Can realize same effect.
Another kind as MHL output unit of the present invention and USB high speed output unit changes, described enable signal EN can be connected to USB_HS_CTL the grid of M5 and M6 after logical operation again, and described like this enable signal EN can both control M5 and M6 conducting and cut-off with USB_HS_CTL.
Another kind as MHL output unit of the present invention and USB high speed output unit changes, and each transistor in described USB high speed output unit can adopt CMOS transistor, and each transistor in described MHL output unit can adopt CMOS transistor.
In summary, the present invention integrates the reflector of MHL 13 and USB transceiver 12, by internal chip enable signal, control conducting and/or the cut-off that is arranged at a plurality of MOS transistor in MHL output unit 132 and USB high speed output unit 122, to control the unlatching of MHL output unit 132 and USB high speed output unit 122 or to close, thereby distinguish the different application (realizing the micro usb 1 10 of MHL reflector 13 multiplexing USB transceivers 12) of MHL or USB, thereby reduced extra analog switch chip (or no longer needing analog switch chip to be integrated in MHL emitter chip), design difficulty and the chip cost of MHL reflector have been reduced, and reduced the line of PCB, and then reduced the cost of realizing of system.In addition, the present invention has also greatly improved the quality of signal transmission, such as, the output signal of the reflector 130 of MHL can share a pad (PAD), pressure welding line or package pins (pin) with the fast mode output signal of USB2.0, thereby not only reduced total chip package testing cost and the parasitic load effect of system, and improved the quality of system signal transmission.
In the present invention, " connection ", be connected, word that the expression such as " companys ", " connecing " is electrical connected, if no special instructions, represent direct or indirect electric connection, such as connected after a resistance, a logical circuit or a functional circuit, etc." row " in the present invention or " OK " are all sensu lato implications, and it both can refer to a row of level in array, also can refer to a vertical row.
It is pointed out that being familiar with any change that person skilled in art does the specific embodiment of the present invention does not all depart from the scope of claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (11)
1. MHL and a USB joint circuit, is characterized in that, it comprises: micro USB interface, USB transceiver and MHL reflector,
Described micro USB interface comprises the first data terminal D+ and the second data terminal D-;
Described USB transceiver comprises USB high speed output unit, and described USB high speed output unit comprises:
The first current source, it is connected between power end and first node, and the sense of current of the first current source is for to flow to first node by power end;
Be series at successively transistor M1, M3, M5 and the first resistance between first node and earth terminal;
Be series at successively transistor M2, M4, M6 and the second resistance between first node and earth terminal;
The grid of the grid of transistor M1 and transistor M2 is connected with a pair of high-speed-differential data-signal that described USB transceiver produces respectively, the first link of transistor M5 is connected with described the first data terminal D+, the second link of transistor M5 is connected with the first resistance, the first link of transistor M6 is connected with described the second data terminal D-, the second link of transistor M6 is connected with the second resistance, after being connected, the grid of the grid of transistor M3 and transistor M4 is connected with USB high-speed control signal, after being connected, the grid of the grid of transistor M5 and transistor M6 is connected with enable signal,
Described MHL reflector comprises MHL output unit, and described MHL output unit comprises:
The second current source, it is connected between Section Point and earth terminal, and the sense of current of this second current source is for to flow to earth terminal by Section Point;
Be series at successively transistor M7 and M9 between the first data terminal D+ and Section Point:
Be series at successively transistor M8 and M10 between the second data terminal D-and Section Point;
The grid of the grid of transistor M9 and transistor M10 is connected with a pair of MHL differential data signals that MHL reflector produces respectively, after the grid of the grid of transistor M7 and transistor M8 is connected, is connected with MHL emissioning controling signal.
2. MHL according to claim 1 and USB joint circuit, is characterized in that,
The first link of transistor M1 is connected with first node, the second link of transistor M1 is connected with the first link of transistor M3, the second link of transistor M3 is connected with the first link of transistor M5, and the second link of transistor M5 is connected with earth terminal GND by the first resistance;
The first link of transistor M2 is connected with first node, the second link of transistor M2 is connected with the first link of transistor M4, the second link of transistor M4 is connected with the first link of M6, and the second link of transistor M6 is connected with earth terminal GND by the second resistance;
The first link of transistor M7 is connected with the first data terminal D+, and the second link of transistor M7 is connected with the first link of transistor M9, and the second link of transistor M9 is connected with Section Point;
The first link of transistor M8 is connected with the second data terminal D-, and the second link of transistor M8 is connected with the first link of transistor M10, and the second link of transistor M10 is connected with Section Point.
3. MHL according to claim 2 and USB joint circuit, is characterized in that,
At described MHL and USB joint circuit during in USB high speed operation pattern, MHL emissioning controling signal is the first logic level, to control M7 and M8 cut-off, USB high-speed control signal is that the second logic level is controlled M3 and M4 conducting, to open described USB high speed output unit, after MHL and USB joint circuit and the outside USB device of inserting described micro USB interface complete and shake hands, when enable signal is the second logic level, make M5 and M6 conducting, make the work of described USB high speed output unit;
Described MHL and USB joint circuit are when the USB of non-high speed mode of operation, USB high-speed control signal is that the first logic level is to control M3 and M4 cut-off, and EN signal is the first logic level, make M5 and M6 cut-off, to close USB high speed output unit, MHL emissioning controling signal is the first logic level, to control M7 and M8 cut-off
At described MHL and USB joint circuit, during in MHL mode of operation, USB high-speed control signal is the first logic level, and to control M3 and M4 cut-off, and enable signal is the first logic level, makes M5 and M6 cut-off, to close USB high speed output unit; MHL emissioning controling signal is that the second logic level is controlled M7 and M8 conducting, to open described MHL output unit.
4. MHL and a USB joint circuit, is characterized in that, it comprises: micro USB interface, USB transceiver and MHL reflector,
Described micro USB interface comprises the first data terminal D+ and the second data terminal D-;
Described USB transceiver comprises USB high speed output unit, and described USB high speed output unit comprises:
The first current source, it is connected between power end and first node, and the sense of current of the first current source is for to flow to first node by power end;
Be series at successively transistor M1, M5 and the first resistance between first node and earth terminal;
Be series at successively transistor M2, M6 and the second resistance between first node and earth terminal;
The grid of the grid of transistor M1 and transistor M2 is connected with a pair of high-speed-differential data-signal that described USB transceiver produces respectively, the first link of transistor M5 is connected with described the first data terminal D+, the second link of transistor M5 is connected with the first resistance, the first link of transistor M6 is connected with described the second data terminal D-, the second link of transistor M6 is connected with the second resistance, after being connected, the grid of the grid of transistor M5 and transistor M6 is connected with enable signal
Described MHL reflector comprises MHL output unit, and described MHL output unit comprises:
The second current source, it is connected between Section Point and earth terminal, and the sense of current of this second current source is for to flow to earth terminal by Section Point;
Be series at successively the transistor M9 between the first data terminal D+ and Section Point:
Be series at successively the transistor M10 between the second data terminal D-and Section Point;
The grid of the grid of transistor M9 and transistor M10 is connected with a pair of MHL differential data signals that MHL reflector produces respectively.
5. MHL according to claim 4 and USB joint circuit, is characterized in that,
The first link of transistor M1 is connected with first node, and the second link of transistor M1 is connected with the first link of transistor M5, and the second link of transistor M5 is connected with earth terminal GND;
The first link of transistor M2 is connected with first node, and the second link of transistor M2 is connected with the first link of transistor M6, and the second link of transistor M6 is connected with earth terminal GND.
6. MHL according to claim 5 and USB joint circuit, is characterized in that,
At described MHL and USB joint circuit during in USB high speed operation pattern, MHL differential data signals is locked into the first logic level, control M9 and M10 cut-off, thereby close described MHL output unit, after MHL and USB joint circuit and the outside USB device of inserting described micro USB interface complete and shake hands, when enable signal is the second logic level, make M5 and M6 conducting, make the work of described USB high speed output unit;
Described MHL and USB joint circuit are when the USB of non-high speed mode of operation, MHL differential data signals is locked into the first logic level, control M9 and M10 cut-off, thereby close described MHL output unit, USB high-speed-differential data-signal is all locked as the first logic level, controls M1 and M2 cut-off, and enable signal is the first logic level, control M5 and M6 cut-off, close UBS high speed output unit;
At described MHL and USB joint circuit, during in MHL mode of operation, USB high-speed-differential data-signal is all locked as the first logic level, controls M1 and M2 cut-off, and enable signal is the first logic level, controls M5 and M6 cut-off, closes UBS high speed output unit.
7. MHL according to claim 4 and USB joint circuit, is characterized in that,
The a pair of high-speed-differential data-signal that described USB transceiver produces and USB high-speed control signal are connected with the grid of transistor M2 with the grid of transistor M1 through logical circuit,
When described USB high-speed control signal is the second logic level, the conducting of transistor M1 and M2 or cut-off by described a pair of high-speed-differential data-signal, determined, when described USB high-speed control signal is the first logic level, transistor M1 and M2 end.
8. MHL according to claim 4 and USB joint circuit, is characterized in that,
The a pair of MHL differential data signals that MHL reflector produces and MHL emissioning controling signal are connected with the grid of transistor M10 with the grid of transistor M9 through logical circuit,
When described MHL emissioning controling signal is the second logic level, the conducting of transistor M9 and M10 or cut-off by described a pair of MHL differential data signals, determined, when described USB high-speed control signal is the first logic level, transistor M9 and M10 end.
9. according to MHL and USB joint circuit described in claim 3,6,7 or 8, it is characterized in that,
Described transistor is nmos pass transistor, and described the first link is drain electrode, and described the second link is source electrode, and described the first logic level is low level, and described the second logic level is high level; Or
Described transistor is PMOS transistor, and described the first link is source electrode, and described the second link is drain electrode, and described the first logic level is high level, and described the second logic level is low level.
10. according to MHL and USB joint circuit described in claim 3,6,7 or 8, it is characterized in that, it is formed on same wafer.
11. 1 kinds of portable electric appts, is characterized in that, it comprises MHL and USB joint circuit as described in as arbitrary in claim 1-9.
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| CN201410462349.7A CN104202631A (en) | 2014-09-12 | 2014-09-12 | MHL-USB (mobile high-definition link and universal serial bus) joint circuit and portable electronic device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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