CN105208380A - Verification platform and system - Google Patents
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Abstract
The invention discloses a verification platform and system. The verification platform comprises a programmable logic gate array (FPGA) and a program download interface, wherein the FPGA is used for conducting design verification on an intellectual property (IP) nucleus corresponding to integrated circuit design of a high-definition digital video interface; the program download interface is connected with the FPGA, and used for downloading the program corresponding to the IP nucleus into the FPGA. The technical problem that in correlation techniques, as no special verification platform aiming at the high-definition digital video interface IP is provided, the high-definition digital video interface IP is hard to verify accurately, is solved.
Description
Technical field
The present invention relates to circuit design verification field, in particular to a kind of verification platform and system.
Background technology
Usually, for the intellectual property (IntellectualProperty of integrated circuit reusing design, referred to as IP) core, in programming to application-specific integrated circuit (ASIC) (ApplicationSpecificIntegratedCircuit, referred to as ASIC) before chip, must programmable gate array (FieldProgrammableGateArray at the scene, referred to as FPGA) platform carries out design verification, be verified and just can freeze the design of this IP kernel afterwards, and then enter the flow stage.
Such as, during design high definition digital video interface, before making IPASIC chip, generally must test the IP kernel for describing high definition digital video interface and high-definition digital display interface (DisplayPort, referred to as DP) and high-definition media interface (HighDefinitionMultimediaInterface, referred to as HDMI) signal corresponding respectively receives/makes a start mouth (Receiver/Transmitter, referred to as TX/RX), i.e. DPTX/RX, HDMITX/RX, and mobile Industry Processor Interface (MobileIndustryProcessorInterface, referred to as MIPI) corresponding receiver port, i.e. MIPITX/RX.
Although verify, communication signal process, computer digit process, consumption electronic product design and the field such as Industry Control by extensive use and asic chip for FPGA, but because FPGA can the application characteristic of flexible programming and the primacy of high definition digital video interface technology and technical difficulty, be not specifically designed to the FPGA application platform of checking high definition digital video interface IP at present, cause being difficult to verify high definition digital video interface IP exactly.
For above-mentioned problem, at present effective solution is not yet proposed.
Summary of the invention
Embodiments provide a kind of verification platform and system, at least to solve the technical problem being difficult to verify exactly high definition digital video interface IP caused owing to not having the special verification platform for high definition digital video interface IP in correlation technique.
According to an aspect of the embodiment of the present invention, provide a kind of verification platform, comprising: programming logic gate array FPGA, carry out design verification for the intellectual property IP kernel corresponding to the integrated circuit (IC) design of high definition digital video interface; Download program interface, is connected with above-mentioned FPGA, for above-mentioned IP being checked the download program of answering in above-mentioned FPGA.
Further, above-mentioned verification platform also comprises: program storage, is connected between said procedure download interface and above-mentioned FPGA, checks the program of answering for storing the above-mentioned IP downloaded by said procedure download interface.
Further, above-mentioned verification platform also comprise with in lower port or port set one of at least: high-definition digital display receiving port DPRX and Low Voltage Differential Signal LVDS output port; High-definition digital display transmit port DPTX; High-definition multimedia receiving port HDMIRX and above-mentioned Low Voltage Differential Signal LVDS output port; High-definition multimedia transmit port HDMITX; Mobile Industry Processor transmit port MIPITX.
Further, above-mentioned high-definition digital display receiving port DPRX, is connected with above-mentioned FPGA, for receiving the DP digital format images that outside high-definition digital display DP signal source exports; Above-mentioned Low Voltage Differential Signal LVDS output port, is connected with above-mentioned FPGA, for exporting the picture signal that above-mentioned FPGA recovers according to the digital format images that above-mentioned DPRX receives.
Further, above-mentioned verification platform also comprises: external memory storage, is connected with above-mentioned FPGA, for storing the above-mentioned DP digital format images exported by above-mentioned DP signal source.
Further, above-mentioned high-definition digital display transmit port DPTX, is connected with above-mentioned FPGA, for reading the picture format of outside high-definition digital DP display screen support and the test image signal meeting this picture format generated being sent to above-mentioned DP display screen.
Further, above-mentioned high-definition multimedia receiving port HDMIRX, is connected with above-mentioned FPGA, for receiving the HDMI digital format images that outside high-definition multimedia HDMI signal source exports; Above-mentioned Low Voltage Differential Signal LVDS output port, is connected with above-mentioned FPGA, for exporting the picture signal that above-mentioned FPGA recovers according to the HDMI digital format images that above-mentioned HDMIRX receives.
Further, above-mentioned high-definition multimedia transmit port HDMITX, is connected with above-mentioned FPGA, for reading the picture format of outside high-definition multimedia HDMI display screen support and the test image signal meeting this picture format generated being sent to above-mentioned HDMI display screen.
Further, above-mentioned mobile Industry Processor transmit port MIPITX, is connected with above-mentioned FPGA, for the test image signal of generation is sent to HDMI display screen.
According to the another aspect of the embodiment of the present invention, additionally provide a kind of verification system, comprising: the verification platform that any one is above-mentioned.
In embodiments of the present invention, the mode of the FPGA verification platform checking high definition digital video interface IP adopting design special, by programming logic gate array FPGA, carry out design verification for the intellectual property IP kernel corresponding to the integrated circuit (IC) design of high definition digital video interface; Download program interface, be connected with FPGA, for by download program corresponding for IP kernel in FPGA, reach the verification platform object for high definition digital video interface IP that design is special, thus achieve the technique effect verifying high definition digital video interface IP exactly, and then solve the technical problem being difficult to verify exactly high definition digital video interface IP caused owing to not having the special verification platform for high definition digital video interface IP in correlation technique.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, and form a application's part, schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of a kind of optional verification system according to the embodiment of the present invention;
Fig. 2 is the schematic diagram of a kind of optional DPRXIP verification system according to the embodiment of the present invention;
Fig. 3 is the schematic diagram of a kind of optional DPTXIP verification system according to the embodiment of the present invention;
Fig. 4 is the schematic diagram of a kind of optional HDMIRXIP verification system according to the embodiment of the present invention;
Fig. 5 is the schematic diagram of a kind of optional HDMITXIP verification system according to the embodiment of the present invention;
Fig. 6 is the schematic diagram of a kind of optional MIPITXIP verification system according to the embodiment of the present invention;
Fig. 7 is the schematic diagram of a kind of optional verification platform according to the embodiment of the present invention.
Embodiment
The present invention program is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the embodiment of a part of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, should belong to the scope of protection of the invention.
It should be noted that, term " first ", " second " etc. in specification of the present invention and claims and above-mentioned accompanying drawing are for distinguishing similar object, and need not be used for describing specific order or precedence.Should be appreciated that the data used like this can be exchanged in the appropriate case, so as embodiments of the invention described herein can with except here diagram or describe those except order implement.In addition, term " comprises " and " having " and their any distortion, and intention is to cover not exclusive comprising.
Embodiment 1
According to the embodiment of the present invention, provide a kind of device embodiment of verification system.
This verification system comprises: verification platform.Wherein, this verification platform comprises: programming logic gate array FPGA, carries out design verification for the intellectual property IP kernel corresponding to the integrated circuit (IC) design of high definition digital video interface; Download program interface, is connected with FPGA, for by download program corresponding for IP kernel in FPGA.
Alternatively, above-mentioned verification platform can also be the verification platform in the technical scheme that in following embodiment 2, arbitrary preferred implementation provides, and does not repeat them here.
Fig. 1 is the schematic diagram of a kind of optional verification system according to the embodiment of the present invention, and as shown in Figure 1, this system comprises: verification platform 10 and host computer 20.During enforcement, IP kernel in the asic chip of the high definition digital video interface designed in advance can directly be downloaded in the FPGA102 in verification platform 10 by the download program interface 104 (as FPGAJTAG (JointTestActionGroup) download interface) on verification platform 10 by host computer 20, and host computer 20 can by FPGAJTAG download interface on-line debugging and the IP kernel monitored in the asic chip of high definition digital video interface simultaneously.Wherein, when IP program upgrade, verification platform 10 can download the IP program after upgrading by download program interface 104 from host computer 20.But after this verification platform power-off, in FPGA102, code can be lost.
Pass through the embodiment of the present invention, solve prior art and be difficult to verify exactly that in asic chip, high-definition digital video connects the problem of corresponding IP kernel, reach the verification platform object for high definition digital video interface IP that design is special, thus achieve the technique effect verifying high definition digital video interface IP exactly, and then reach the object improving and realize the success rate of high definition digital video interface IP.
Further, above-mentioned verification system, except comprising verification platform 10 and host computer 20, can also comprise in following external equipment one or more: high-definition digital display DP signal source, Low Voltage Differential Signal LVDS display screen, DP display screen (or DP display), high-definition multimedia HDMI signal source, HDMI display screen (or HDMI display), MIPI turns HDMITX chip, thus forms as the verification system in Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 respectively.Wherein, Fig. 2 is the schematic diagram of a kind of optional DPRXIP verification system according to the embodiment of the present invention; Fig. 3 is the schematic diagram of a kind of optional DPTXIP verification system according to the embodiment of the present invention; Fig. 4 is the schematic diagram of a kind of optional HDMIRXIP verification system according to the embodiment of the present invention; Fig. 5 is the schematic diagram of a kind of optional HDMITXIP verification system according to the embodiment of the present invention; Fig. 6 is the schematic diagram of a kind of optional MIPITXIP verification system according to the embodiment of the present invention.Like this, verification platform 10 can load different high definition digital video interface asic chip IP by FPGA102, and coordinates different external equipments to form different verification systems to carry out design verification.
It should be noted that, the verification system related in Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6 will be described in detail in conjunction with corresponding verification platform in following embodiment 2, not repeat them here.
Embodiment 2
According to the embodiment of the present invention, provide a kind of device embodiment of verification platform.
Fig. 7 is the schematic diagram of a kind of optional verification platform according to the embodiment of the present invention, as shown in Figure 7, this verification platform 10 comprises: programming logic gate array FPGA 102 (as XilinxVirtex-6XC6VLX240T), carries out design verification for the intellectual property IP kernel (hereinafter referred to as high definition digital video interface IP) corresponding to the integrated circuit (IC) design of high definition digital video interface; Download program interface 104, is connected with FPGA102, for by download program corresponding for IP kernel in FPGA102.
Composition graphs 1 and Fig. 7, high definition digital video interface IP can be directly downloaded in FPGA102 by download program interface 104 (as FPGAJTAG download interface) by host computer 20, and host computer 20 can by download program interface 104 (as FPGAJTAG download interface) on-line debugging and monitoring high definition digital video interface IP simultaneously.Wherein, when IP program upgrade, verification platform 10 can download the IP program after upgrading by download program interface 104 from host computer 20.But after this verification platform power-off, in FPGA102, code can be lost.
Pass through the embodiment of the present invention, the mode of the FPGA verification platform checking high definition digital video interface IP adopting design special, reach the verification platform object for high definition digital video interface IP that design is special, thus achieve the technique effect verifying high definition digital video interface IP exactly, and then reach the object improving and realize the success rate of high definition digital video interface IP.
Alternatively, as shown in Figure 7, above-mentioned verification platform 10 also comprises: program storage 106, is connected between download program interface 104 and FPGA102, for storing by program corresponding to the IP kernel of download program interface 104 download.
Composition graphs 1 and Fig. 7, the program that high definition digital video interface IP is downloaded to FPGA by download program interface 104 (as FPGAJTAG download interface) can store in 106 (i.e. EEPROM (XCF128X)) by host computer 20, after verification platform 10 powers on, FPGA102 automatically can store loading high definition digital video interface IP code 106 (i.e. EEPROM) from the program of FPGA and carry out design verification.Like this, after platform power-off, can ensure that in FPGA2, code is not lost.
Alternatively, the verification system related in composition graphs 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, in order to verify the design conditions of different piece in high definition digital video interface IP, above-mentioned verification platform 10 also comprise with in lower port or port set one of at least: high-definition digital display receiving port DPRX (Receiver) and Low Voltage Differential Signal LVDS output port; High-definition digital display transmit port DPTX; High-definition multimedia receiving port HDMIRX and Low Voltage Differential Signal LVDS output port; High-definition multimedia transmit port HDMITX (Transmitter); Mobile Industry Processor transmit port MIPITX.As shown in Figure 7, above-mentioned verification platform 10 also comprises with lower port or port set: high-definition digital display receiving port DPRX108 and Low Voltage Differential Signal LVDS output port 110; High-definition digital display transmit port DPTX112; High-definition multimedia receiving port HDMIRX114 and Low Voltage Differential Signal LVDS output port 110; High-definition multimedia transmit port HDMITX116; Mobile Industry Processor transmit port MIPITX118.
Below in conjunction with Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, elaborate the function of the corresponding port involved by different verification systems and correspondence system.
As shown in Figure 2, this DPRXIP verification system comprises: verification platform 10, DP signal source 30 and LVDS display screen 40.Wherein, verification platform 10 comprises with lower port: high-definition digital display receiving port DPRX108 and Low Voltage Differential Signal LVDS output port 110.Wherein, high-definition digital display receiving port DPRX108, is connected with FPGA102, for receiving the DP digital format images that outside high-definition digital display DP signal source 30 exports; Low Voltage Differential Signal LVDS output port 110 (as 80pinsLVDS/LVTTL output interface), is connected with FPGA102, for exporting the picture signal that FPGA102 recovers according to the digital format images that DPRX108 receives.During enforcement, DP signal source 30 is connected with DPRX108, exports DP digital format images to FPGA102.FPGA102 and DPRX108 is connected, and recovers the picture signal of the DP digital format images of DP signal source 30.FPGA102 and LVDS output port 110 is connected, and exports the picture signal recovered with the form of LVDS format-pattern.LVDS display screen 40 is connected with LVDS output port 110, may be used for showing the DP digital format images received from DPRX108.
As shown in Figure 7, above-mentioned verification platform 10 also comprises: external memory storage 120, is connected with FPGA102, for storing the DP digital format images exported by DP signal source 30.Wherein, the external memory storage 120 of FPGA can be that Double Data Rate synchronous DRAM DDR3 stores particle (MT41J64M16).As shown in Figure 2, the external memory storage 120 of FPGA is connected with FPGA102, can store the picture signal that DP signal source 30 exports.But when DP signal source 30 stops output image signal, FPGA102 can read data from external memory storage 120 and be shown in LVDS display screen 40.
It should be noted that, by adopting the DPRXIP verification system shown in Fig. 2, DPRXIP function can not only be verified, the PSR function of eDP1.3 can also be verified simultaneously.
As shown in Figure 3, this DPTXIP verification system comprises: verification platform 10, DP display screen 50.Wherein, verification platform 10 comprises: the high-definition digital be connected with FPGA102 shows transmit port DPTX112, for reading the picture format of outside high-definition digital DP display screen 50 support and the test image signal meeting this picture format generated being sent to DP display screen 50.Within the system, DPTX112 with DP display screen 50 is connected.FPGA102 can read the picture format of DP display screen 50 support by DPTX112 and the test image signal of generation is transferred to DP display screen 50 by DPTX112, thus detects DPTXIP by the image of display in DP display screen 50.
By adopting DPTXIP verification system as shown in Figure 3, DPTXIP function can be verified.
As shown in Figure 4, this HDMIRXIP verification system comprises: verification platform 10, HDMI signal source 60 and LVDS display screen 40.Wherein, verification platform 10 comprises: the high-definition multimedia receiving port HDMIRX114 be connected with FPGA102, for receiving the HDMI digital format images that outside high-definition multimedia HDMI signal source 60 exports; Low Voltage Differential Signal LVDS output port 110, is connected with FPGA102, for exporting the picture signal that FPGA102 recovers according to the HDMI digital format images that HDMIRX114 receives.During enforcement, HDMI signal source 60 is connected with HDMIRX114, exports HDMI digital format images.FPGA102 and HDMIRX114 is connected, and recovers the picture signal of HDMI signal source 60.FPGA102 and LVDS output port 110 is connected, and exports LVDS format-pattern signal.LVDS display screen 40 is connected with the LVDS output port 110 on verification platform 10, may be used for showing the image that the HDMI picture signal that receives from HDMIRX114 is corresponding.
By adopting HDMIRXIP verification system as shown in Figure 4, HDMIRXIP function can be verified.
As shown in Figure 5, this HDMITXIP verification system comprises: verification platform 10, HDMI display screen 70.Wherein, verification platform 10 comprises: the high-definition multimedia transmit port HDMITX116 be connected with FPGA102, for reading the picture format of outside high-definition multimedia HDMI display screen 70 support and the test image signal meeting this picture format generated being sent to HDMI display screen 70.During enforcement, HDMITX116 with HDMI display screen 70 is connected, FPGA102 can read the picture format of HDMI display screen 70 support by HDMITX116 and the test image signal of generation is transferred to HDMI display screen 70 by HDMITX116, thus detects HDMITXIP by the image that HDMI display screen 70 shows.
By adopting HDMITXIP verification system as shown in Figure 5, HDMITXIP function can be verified.
As shown in Figure 6, this MIPITXIP verification system comprises: verification platform 10, HDMI display screen 70 and MIPI turn HDMITX chip 80.Wherein, verification platform 10 comprises: the mobile Industry Processor transmit port MIPITX118 be connected with FPGA102, for the test image signal of generation is sent to HDMI display screen.It should be noted that, before test image signal is sent to HDMI display screen by MIPITX118, first will turn through MIPI the picture signal that the test image signal that MIPITX118 sends to be converted to HDMI number format by HDMITX chip 80.During enforcement, FPGA102 and MIPITX118 is connected.MIPITX118 and MIPI turns HDMITX chip 80 and is connected.FPGA102 can send MIPI format-pattern signal by MIPITX118 and turn HDMITX chip 80 to MIPI.MIPI turns HDMITX chip 80 and connects HDMI display 70, HDMI display 70 for showing MIPI image, thus detects MIPITXIP by the image that HDMI display screen 70 shows.
By adopting MIPITXIP verification system as shown in Figure 6, MIPITXIP function can be verified.
The invention described above embodiment sequence number, just to describing, does not represent the quality of embodiment.
In the above embodiment of the present invention, the description of each embodiment is all emphasized particularly on different fields, in certain embodiment, there is no the part described in detail, can see the associated description of other embodiments.
In several embodiments that the application provides, should be understood that, disclosed technology contents, the mode by other realizes.Wherein, device embodiment described above is only schematic, the division of such as unit, can be that a kind of logic function divides, actual can have other dividing mode when realizing, such as multiple unit or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of unit or module or communication connection can be electrical or other form.
The unit illustrated as separating component or can may not be and physically separates, and the parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed on multiple unit.Some or all of unit wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.
Below be only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a verification platform, is characterized in that, comprising:
Programming logic gate array FPGA, carries out design verification for the intellectual property IP kernel corresponding to the integrated circuit (IC) design of high definition digital video interface;
Download program interface, is connected with described FPGA, for by download program corresponding for described IP kernel in described FPGA.
2. verification platform according to claim 1, is characterized in that, also comprises:
Program storage, is connected between described download program interface and described FPGA, for storing by program corresponding to the described IP kernel of described download program interface download.
3. verification platform according to claim 1, is characterized in that, described verification platform also comprise with in lower port or port set one of at least:
High-definition digital display receiving port DPRX and Low Voltage Differential Signal LVDS output port;
High-definition digital display transmit port DPTX;
High-definition multimedia receiving port HDMIRX and described Low Voltage Differential Signal LVDS output port;
High-definition multimedia transmit port HDMITX;
Mobile Industry Processor transmit port MIPITX.
4. verification platform according to claim 3, is characterized in that,
Described high-definition digital display receiving port DPRX, is connected with described FPGA, for receiving the DP digital format images that outside high-definition digital display DP signal source exports;
Described Low Voltage Differential Signal LVDS output port, is connected with described FPGA, for exporting the picture signal that described FPGA recovers according to the digital format images that described DPRX receives.
5. verification platform according to claim 4, is characterized in that, also comprises:
External memory storage, is connected with described FPGA, for storing the described DP digital format images exported by described DP signal source.
6. verification platform according to claim 3, is characterized in that,
Described high-definition digital display transmit port DPTX, is connected with described FPGA, for reading the picture format of outside high-definition digital DP display screen support and the test image signal meeting this picture format generated being sent to described DP display screen.
7. verification platform according to claim 3, is characterized in that,
Described high-definition multimedia receiving port HDMIRX, is connected with described FPGA, for receiving the HDMI digital format images that outside high-definition multimedia HDMI signal source exports;
Described Low Voltage Differential Signal LVDS output port, is connected with described FPGA, for exporting the picture signal that described FPGA recovers according to the HDMI digital format images that described HDMIRX receives.
8. verification platform according to claim 3, is characterized in that,
Described high-definition multimedia transmit port HDMITX, is connected with described FPGA, for reading the picture format of outside high-definition multimedia HDMI display screen support and the test image signal meeting this picture format generated being sent to described HDMI display screen.
9. verification platform according to claim 3, is characterized in that,
Described mobile Industry Processor transmit port MIPITX, is connected with described FPGA, for the test image signal of generation is sent to HDMI display screen.
10. a verification system, is characterized in that, comprising: the verification platform according to any one of claim 1 to 9.
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