CN102129524A - Design and verification platform of medical electronic chip - Google Patents
Design and verification platform of medical electronic chip Download PDFInfo
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- CN102129524A CN102129524A CN2011100712835A CN201110071283A CN102129524A CN 102129524 A CN102129524 A CN 102129524A CN 2011100712835 A CN2011100712835 A CN 2011100712835A CN 201110071283 A CN201110071283 A CN 201110071283A CN 102129524 A CN102129524 A CN 102129524A
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Abstract
The invention relates to a chip developing platform, in particular relating to a design and verification platform of a medical electronic chip. The platform comprises a JTAG (Joint Test Action Group) interface circuit, an ARM (Advanced RISC Machines) processor core, an FPGA (Field Programmable Gata Array) circuit and a peripheral interface circuit, wherein the JTAG interface circuit is connected with a computer by virtue of a JTAG debugging simulator; the ARM processor core is connected with the JTAG interface circuit; the FPGA circuit is connected with the ARM processor core; the FPGA circuit comprises a system bus, a power management module, a digital-to-analogue conversion module, a watchdog module, a clock module, a storage management module, a display control module and at least one IP (Internet Protocol) core for processing physiological signals; and the peripheral interface circuit comprises a memory, a display, a crystal oscillator circuit, a power circuit and a switch. When new medical electronic products are developed on the basis of the design and verification platform of the medical electronic chip, various types of IPs can be flexibly and quickly configured for IP multiplexing, thereby preventing repeated development of the similar function parts of various products, shortening the development period of the product, and lowering the product development cost.
Description
[technical field]
The present invention relates to chip design and verification technique, particularly relate to a kind of low-power consumption, general medical electronics chip design and the platform of checking.
[background technology]
With the specialization of work medical section purpose refinement, medical diagnosis, the demand of medical electric product (for example the heart, brain, flesh, eye monitor and register instrument, blood measuring instrument, electric body-temperature, device for pressure measurement etc.) is increasing.In addition, along with the generally increase of people's health care consciousness and the raising of quality of the life, the medical electric product, for example sphygmomanometer, cardioelectric monitor equipment, blood glucose meter etc. begin to enter general family.For medical electronics product manufacturer, how in the shortest time, the medical electronics product to be introduced to the market, thereby the position of occupying a seat on this market becomes the survival strategy of each big medical electronics manufacturer with minimum cost.
At present, the medical electronics Products Development mainly is based on embedded solution, each Products Development is all based on the relevant hardware platform, this must cause the overlapping development of the identity function part of a plurality of products, cause the bad configuration of intellecture property, technological accumulation is poor, the cost of development height, and the construction cycle is long.Simultaneously, development system uses discrete component more, causes system bulk big, power consumption and cost height.In addition, existing development system generally all adopts baroque general processor or digital signal processor DSP, is not optimized at processing of biomedical signals, makes Wearable, portable medical electronic product power consumption height, and volume is big, the cost height.
[summary of the invention]
Based on this, be necessary to provide a kind of be applicable to the medical electronics product, low-power consumption, general medical electronics chip design and verification platform.
A kind of medical electronics chip design and verification platform comprise the jtag interface circuit, arm processor nuclear, FPGA circuit, and peripheral interface circuit.Described jtag interface circuit is used for linking to each other with computing machine by JTAG debugging emulation device.Described arm processor nuclear links to each other with described jtag interface circuit.Described FPGA circuit and described arm processor nuclear phase connect.This FPGA circuit comprises system bus and the watchdog module, clock module, memory management module and at least one IP kernel at physiological single processing that connect by this system bus and described arm processor nuclear phase.Described peripheral interface circuit comprises storer and crystal oscillating circuit.Described storer links to each other with the memory management module of described FPGA circuit, and described crystal oscillating circuit and clock module and arm processor nuclear phase connect.
In a preferred embodiment, described jtag interface circuit, arm processor nuclear and FPGA circuit are distributed on the printed-wiring board (PWB) of a multilayer.
In a preferred embodiment, described system bus is the low-power consumption ahb bus of compatible AMBA bus.
In a preferred embodiment, the address bus in the described system bus adopts Gray code.
In a preferred embodiment, but described at least one IP kernel at physiological single processing comprises spread F FT module, convolution module, at least one in FIR filtration module and the characteristic extracting module.
In a preferred embodiment, described storer comprises at least a storer in FLASH storer, SRAM storer and the SDRAM storer.
In a preferred embodiment, described FPGA circuit also comprises at least one module in Cache buffer memory, interrupt management module, dma controller, power management module, D/A converter module, display control module, universal serial bus, Ethernet interface and the VGA interface that connects by described system bus and described arm processor nuclear phase.
In a preferred embodiment, described peripheral interface circuit also comprises with the display of described display control module, is at least one module of the power circuit of each module for power supply of platform, the switch module that is used for controlling platform work, serial line interface, Ethernet interface, VGA interface.
In a preferred embodiment, described display control module comprises lcd controller and GPIO controller, and described display comprises LCD display and LED display module.
In a preferred embodiment, described peripheral interface circuit also comprises a plurality of test points that are used to carry out platform voltage and current detecting.
Carry out the medical electronics new product development based on above-mentioned medical electronics chip design and verification platform, can dispose all kinds of IP flexibly apace, carry out IP reuse, avoid the overlapping development of the identity function part of a plurality of products, shorten product development cycle, reduced product development cost.Arm processor nuclear has low-power consumption, advantage that volume is little, is highly suitable for medical electronics product, particularly Wearable, portable medical electronic product.
[description of drawings]
Fig. 1 is the medical electronics chip design of an embodiment and the structural representation of verification system;
Fig. 2 is the medical electronics chip design of an embodiment and the system module figure of verification platform;
Fig. 3 is the detailed structure view of system bus among Fig. 2.
[embodiment]
Below in conjunction with the drawings and specific embodiments medical electronics chip design of the present invention and verification platform are further specified.
As shown in Figure 1, be the structured flowchart of a kind of medical electronics chip design and verification system.This medical electronics chip design and verification system mainly comprise medical electronics chip design and verification platform 100, computing machine 300 and JTAG (Joint Test Action Group, joint test working group) the debugging emulation device 200 that medical electronics chip design and verification platform 100 and computing machine 300 are linked together.
As shown in Figure 2, medical electronics chip design and verification platform 100 mainly comprise jtag interface circuit on the printed-wiring board (PWB) that is distributed in a multilayer, arm processor nuclear, comprise at least one FPGA at the IP kernel of physiological single processing (Field-Programmable Gate Array, field programmable gate array) circuit and peripheral interface circuit.
The jtag interface circuit is used for linking to each other with JTAG debugging emulation device 200, thereby platform 100 can link to each other with JTAG debugging emulation device 200, and links to each other with computing machine 300 by JTAG debugging emulation device 200.
Arm processor nuclear links to each other with the FPGA circuit with the jtag interface circuit.In the present embodiment, arm processor nuclear is selected low-power consumption ARM7TDMI processor for use, is fit to very much the relatively stricter application of volume, power consumption and performance requirement.Arm processor nuclear can be downloaded IP kernel data, software program etc. from computing machine 300 by jtag interface circuit and JTAG debugging emulation device 200.By JTAG debugging emulation device 200, also can debug medical electronics chip design and verification platform 100 simultaneously, comprise the debugging breakpoints of C programmer, STEP debugs etc., and to the debugging of IP kernel.
The FPGA circuit links to each other with peripheral interface circuit with arm processor nuclear.This FPGA circuit (chip) can be based on SRAM technology, also can be based on FLASH technology, mainly realizes system bus, system component, Peripheral Interface and the IP kernel of using at processing of biomedical signals.The FPGA circuit has flexible configurability, can develop special chip at the different medical electronic product by the required IP kernel of flexible customization on the FPGA circuit.And IP kernel can oneself be developed, and also can buy commercial ripe IP kernel.
In the present embodiment, display control module, universal serial bus, ethernet controller, VGA module that the FPGA circuit mainly comprises system bus and the Cathe buffer memory by this system bus and arm processor nuclear phase company, power management module, D/A converter module, watchdog circuit, clock module, memory management module, interrupt management module, dma controller, is made up of lcd controller and GPIO controller, and at least one is at the IP kernel of physiological single processing.In the present embodiment, comprise analysis of spectrum IP kernel at physiological single processing (but be among Fig. 2 spread F FT module), convolution module, FIR filtration module and characteristic extracting module at the IP kernel of physiological single processing.Among other embodiment, but can also can dispose other special I P nuclear again according to wanting development product to select one or more in spread F FT module, convolution module, FIR filtration module and the characteristic extracting module for use.Among other embodiment, can delete as required or revise in the above-mentioned FPGA circuit except that at other modules the IP kernel of physiological single processing, for example display control module, ethernet controller etc.
System bus has adopted the low-power consumption ahb bus (LPAHB bus) of compatible AMBA bus, but standardization connects each module.
The Cache buffer memory is used for data and exchange is read in instruction soon.Power management module is used to the low-power dissipation power supply management of the system that realizes.Digital to analog converter is used to realize that simulating signal changes to digital signal.Watchdog circuit is used for anti-locking system race and flies.Clock module provides the stable clock signal to use to system, and clock and calendar can be provided, alarm clock, functions such as periodic interruptions output.Memory management module is used for the management system storage unit.The management system storage unit mainly comprises the SRAM in the peripheral interface circuit, SDRAM and FLASH.Preserve ephemeral data and program when SRAM and SDRAM are mainly used in program run, and FLASH is used to preserve non-volatile data.The interrupt management unit is used for the system break management.Dma controller is used for data high-speed and moves.
Lcd controller links to each other with LCD display in the peripheral interface circuit.Lcd screen is used for picture and text and shows various information, and it can adopt touch-screen, to realize man-machine interaction.The GPIO controller is connected with LED display module in the peripheral interface circuit, is mainly used in the signal indicative function.Universal serial bus links to each other with serial line interface in the peripheral interface circuit.In the peripheral interface circuit serial line interface can comprise the IO interface, SPI interface, RS485 interface, at least a in RS232 interface and the USB interface.Ethernet controller links to each other with Ethernet interface RJ-45 interface in the peripheral interface circuit, is used to realize that network connects.The VGA module links to each other with VGA interface in the peripheral interface circuit, to realize and being connected of all kinds of monitors.
Peripheral interface circuit removes and comprises the above-mentioned SRAM that mentions, SDRAM and FLASH storer, LCD display, the LED display module, IO interface, SPI interface, the RS485 interface, RS232 interface and USB interface outside RJ-45 interface and the VGA interface, also can comprise crystal oscillator, power module, switch module and test point.Crystal oscillator provides medical electronics chip design and verification platform 100 required clock reference source, and it connects with FPGA circuit and arm processor nuclear phase respectively.Power module will be the required 1.2V of platform by the voltage transitions of power supply adaptor, 1.8V, and 2.5V, 3.3V and 5V think each module for power supply on the platform.Switch module is used to control the startup of medical electronics chip design and verification platform 100 and each module thereof and close.Test point is for making things convenient for the hardware platform test voltage, electric current and reserving.Understandable, among other embodiment, can delete or revise the configuration of peripheral interface circuit as required, for example storer, display etc.
Because bus low power occupies the system power dissipation major part, the present invention is optimized at the system bus power consumption specially, for data bus, adopts the BI coded system, for address bus, adopts Gray code.Specifically the reasons are as follows:
Circuit power consumption is made up of quiescent dissipation and dynamic power consumption, and dynamic power consumption is made up of switch power consumption and alternation power consumption (short-circuit dissipation) again, and circuit power consumption can be represented by formula (1):
In the formula (1), P indication circuit power consumption, C is a node capacitor, V
DDBe supply voltage, f is a circuit work frequency, N
SwBe the node sum that single clock cycle internal state changes, Q
ScBe the transmission charge amount that the short-circuit current of single clock cycle interior nodes causes, I
LeakBe leakage current.First of formula is the switch power consumption, corresponding circuits logic when upset, internal node electric capacity discharge and recharge power consumption; Second of formula is short-circuit dissipation, the power supply that N pipe logic and the conducting simultaneously of P pipe logic cause in the corresponding switching process and the short-circuit dissipation on ground; The 3rd of formula is quiescent dissipation, mainly is the leakage current between leak in anti-leakage current partially of PN junction and subthreshold value scope source.
Switch power consumption and short-circuit dissipation by the visible circuit of following formula all are functions of frequency and voltage, can effectively reduce dynamic power consumption by the operating voltage that reduces power supply, but cross the operating rate that low supply voltage can reduce system, reduce noise margin, simultaneously corresponding threshold voltage adjustment can increase leakage current.The dynamic power consumption of circuit mainly is directly proportional with the upset number of times of signal in the circuit, and in cmos circuit, power consumption mainly comes from the dynamic power consumption of circuit, and system-level bus code technology can effectively reduce the toggle frequency of data and address bus signal, thereby effectively reduces system power dissipation.
The present invention adopts the bus code technology respectively data bus and address bus to be encoded.For data bus, adopt the BI coded system.The BI coding method is additional extra marking signal line on bus, is used for indicating the 2 sections interior signals upset situations of continuous time in bus front and back.This coding method is by judging on the t-1 moment bus through the Hamming code distance (being the bit number that bus changes) between the data that need to transmit on coded data and the t moment bus.When Hamming code distance during greater than N/2 (N is a highway width), the data negate on the bus also will put 1; Otherwise situation is opposite.The B-I coding can be represented by formula (2):
B in the formula (2)
tBe meant t actual address constantly, B
tBe the address behind the coding, H
tBe b
tAnd b
(t-1)Different figure place.At receiving end, when INV is " 1 ", the data negate is received; When INV was " 0 ", data were not done any processing.
B-I decoding formula can be represented by formula (3):
J in the formula (3)
tBe decoded address bus.
For address bus, adopt Gray code.Gray (Gray) sign indicating number is a kind of non-weighted code, adopts absolute addressing mode, when it is changed between any two adjacent numbers, has only a numerical digit to change.The variation figure place of having encoded when it has reduced by a state to next adjacent states widely.If natural binary code is: B
N-1B
N-2... B
2B
1B
0Corresponding Gray code is: G
N-1G
N-2... G
2G
1G
0
Then the calculating of Gray code can be expressed as by formula (4):
Because have only a numerical digit to change between adjacent two numbers of Gray code, so be applicable to address bus, when reading the continuation address data especially in a large number, Gray code can effectively reduce the upset 30%-45% of address wire.The maximum code efficiency of Gray code is 50%.Low-power dissipation system bus structure in the present embodiment as shown in Figure 3.
In the use, can move EDA on computing machine 300 develops software, XILINX ISE instrument for example, the IP kernel that will realize with hardware description language (for example Verilog language) downloads in the FPGA circuit in medical electronics chip design and the verification platform 100 or among the FLASH by JTAG debugging emulation device 200.Simultaneously can also be on computing machine 300 C language or assembly language be downloaded to through compilation tool (for example RVDS development kit) in the program space of arm processor nuclear management (SRAM, SDRAM or FLASH).When system debug, can debug by 200 pairs of medical electronics chip designs of JTAG debugging emulation device and verification platform 100, comprise the debugging breakpoints of C programmer, STEP debugging etc. also can be debugged the IP kernel in the FPGA circuit.
In sum, adopt medical electronics chip design of the present invention and verification platform 100, the designer can flexible configuration develop the required all kinds of IP kernels of medical electronics product, carry out IP reuse, or revise at the parameter of the IP kernel of physiological single processing or change algorithm to develop special chip at the different medical electronic product, avoid the overlapping development of the identity function part of a plurality of products, shortened product development cycle, reduce product development cost.In designing and developing, can simultaneously hardware circuit and software section be downloaded on the FPGA circuit, can realize soft, hardware emulation simultaneously, thereby reach the purpose of software and hardware cooperating simulation.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to claim of the present invention.Should be pointed out that for the person of ordinary skill of the art without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. medical electronics chip design and verification platform is characterized in that, comprising:
The jtag interface circuit is used for linking to each other with computing machine by JTAG debugging emulation device;
Arm processor nuclear links to each other with described jtag interface circuit;
The FPGA circuit, connect with described arm processor nuclear phase, this FPGA circuit comprises system bus and the watchdog module, clock module, memory management module and at least one IP kernel at physiological single processing that connect by this system bus and described arm processor nuclear phase; And
The peripheral interface circuit that comprises storer and crystal oscillating circuit;
Described storer links to each other with the memory management module of described FPGA circuit, and described crystal oscillating circuit and clock module and arm processor nuclear phase connect.
2. medical electronics chip design according to claim 1 and verification platform is characterized in that, described jtag interface circuit, arm processor nuclear and FPGA circuit are distributed on the printed-wiring board (PWB) of a multilayer.
3. medical electronics chip design according to claim 2 and verification platform is characterized in that, described system bus is the low-power consumption ahb bus of compatible AMBA bus.
4. medical electronics chip design according to claim 3 and verification platform is characterized in that, the address bus in the described system bus adopts Gray code.
5. medical electronics chip design according to claim 4 and verification platform, it is characterized in that, but described at least one IP kernel at physiological single processing comprises spread F FT module, convolution module, at least one in FIR filtration module and the characteristic extracting module.
6. medical electronics chip design according to claim 5 and verification platform is characterized in that, described storer comprises at least a storer in FLASH storer, SRAM storer and the SDRAM storer.。
7. medical electronics chip design according to claim 6 and verification platform, it is characterized in that described FPGA circuit also comprises at least one module in Cache buffer memory, interrupt management module, dma controller, power management module, D/A converter module, display control module, universal serial bus, Ethernet interface and the VGA interface that connects by described system bus and described arm processor nuclear phase.
8. medical electronics chip design according to claim 7 and verification platform, it is characterized in that described peripheral interface circuit also comprises with the display of described display control module, is at least one module of the power circuit of each module for power supply of platform, the switch module that is used for controlling platform work, serial line interface, Ethernet interface, VGA interface.
9. medical electronics chip design according to claim 8 and verification platform is characterized in that, described display control module comprises lcd controller and GPIO controller, and described display comprises LCD display and LED display module.
10. medical electronics chip design according to claim 9 and verification platform is characterized in that, described peripheral interface circuit also comprises a plurality of test points that are used to carry out platform voltage and current detecting.
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| WO2016155094A1 (en) * | 2015-04-03 | 2016-10-06 | 深圳市贝沃德克生物技术研究院有限公司 | Node network and method for data transmission based on edge detection |
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