CN102129524B - Design and verification platform of medical electronic chip - Google Patents
Design and verification platform of medical electronic chip Download PDFInfo
- Publication number
- CN102129524B CN102129524B CN 201110071283 CN201110071283A CN102129524B CN 102129524 B CN102129524 B CN 102129524B CN 201110071283 CN201110071283 CN 201110071283 CN 201110071283 A CN201110071283 A CN 201110071283A CN 102129524 B CN102129524 B CN 102129524B
- Authority
- CN
- China
- Prior art keywords
- module
- circuit
- interface circuit
- bus
- jtag
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a chip developing platform, in particular relating to a design and verification platform of a medical electronic chip. The platform comprises a JTAG (Joint Test Action Group) interface circuit, an ARM (Advanced RISC Machines) processor core, an FPGA (Field Programmable Gata Array) circuit and a peripheral interface circuit, wherein the JTAG interface circuit is connected with a computer by virtue of a JTAG debugging simulator; the ARM processor core is connected with the JTAG interface circuit; the FPGA circuit is connected with the ARM processor core; the FPGA circuit comprises a system bus, a power management module, a digital-to-analogue conversion module, a watchdog module, a clock module, a storage management module, a display control module and at least one IP (Internet Protocol) core for processing physiological signals; and the peripheral interface circuit comprises a memory, a display, a crystal oscillator circuit, a power circuit and a switch. When new medical electronic products are developed on the basis of the design and verification platform of the medical electronic chip, various types of IPs can be flexibly and quickly configured for IP multiplexing, thereby preventing repeated development of the similar function parts of various products, shortening the development period of the product, and lowering the product development cost.
Description
[technical field]
The present invention relates to chip design and verification technique, particularly relate to a kind of low-power consumption, general medical electronics chip design and the platform of checking.
[background technology]
With the specialization of work medical section purpose refinement, medical diagnosis, the demand of medical electric product (for example the heart, brain, flesh, eye monitor and register instrument, blood measuring instrument, electric body-temperature, device for pressure measurement etc.) is increasing.In addition, along with the generally increase of people's health care consciousness and the raising of quality of the life, the medical electric product, such as sphygmomanometer, cardioelectric monitor equipment, blood glucose meter etc. begins to enter general family.For medical electronics product manufacturer, how with minimum cost, the medical electronics product to be introduced to the market within the shortest time, thereby the position of occupying a seat on this market becomes the survival strategy of each large medical electronics manufacturer.
At present, the exploitation of medical electronics product mainly is based on embedded solution, the exploitation of each product is based on corresponding hardware platform, this must cause the overlapping development of the identity function part of a plurality of products, cause the bad configuration of intellecture property, technological accumulation is poor, and cost of development is high, and the construction cycle is long.Simultaneously, development system uses discrete component more, causes system bulk large, and power consumption and cost are high.In addition, existing development system generally all adopts baroque general processor or digital signal processor DSP, is not optimized for processing of biomedical signals, makes Wearable, portable medical electronic product power consumption high, and volume is large, and cost is high.
[summary of the invention]
Based on this, be necessary to provide a kind of be applicable to the medical electronics product, low-power consumption, general medical electronics chip design and verification platform.
A kind of medical electronics chip design and verification platform comprise the jtag interface circuit, arm processor core, FPGA circuit, and peripheral interface circuit.Described jtag interface circuit is used for being connected with computing machine by JTAG debugging emulation device.Described arm processor core is connected with described jtag interface circuit.Described FPGA circuit and described arm processor nuclear phase connect.This FPGA circuit comprises system bus and the watchdog module, clock module, memory management module and at least one IP kernel for physiological single processing that connect by this system bus and described arm processor nuclear phase.Described peripheral interface circuit comprises storer and crystal oscillating circuit.Described storer is connected with the memory management module of described FPGA circuit, and described crystal oscillating circuit and clock module and arm processor nuclear phase connect.
In a preferred embodiment, described jtag interface circuit, arm processor core and FPGA circuit are distributed on the printed-wiring board (PWB) of a multilayer.
In a preferred embodiment, described system bus is the low-power consumption ahb bus of compatible AMBA bus.
In a preferred embodiment, the address bus in described system bus adopts Gray code.
In a preferred embodiment, but described at least one IP kernel for physiological single processing comprises spread F FT module, convolution module, at least one in FIR filtration module and characteristic extracting module.
In a preferred embodiment, described storer comprises at least a storer in FLASH storer, SRAM storer and SDRAM storer.
In a preferred embodiment, described FPGA circuit also comprises at least one module in Cache buffer memory, interrupt management module, dma controller, power management module, D/A converter module, display control module, universal serial bus, Ethernet interface and the VGA interface that connects by described system bus and described arm processor nuclear phase.
In a preferred embodiment, described peripheral interface circuit also comprises at least one module with the display of described display control module, the power circuit for the power supply of platform modules, the switch module that is used for controlling working platform, serial line interface, Ethernet interface, VGA interface.
In a preferred embodiment, described display control module comprises lcd controller and GPIO controller, and described display comprises LCD display and LED display module.
In a preferred embodiment, described peripheral interface circuit also comprises a plurality of test points be used to carrying out platform voltage and current detecting.
Carry out the medical electronics new product development based on above-mentioned medical electronics chip design and verification platform, can configure rapidly flexibly all kinds of IP, carry out IP reuse, avoid the overlapping development of the identity function part of a plurality of products, shorten product development cycle, reduced product development cost.Arm processor core has advantages of that low-power consumption, volume are little, is highly suitable for medical electronics product, particularly Wearable, portable medical electronic product.
[description of drawings]
Fig. 1 is the medical electronics chip design of an embodiment and the structural representation of verification system;
Fig. 2 is the medical electronics chip design of an embodiment and the system module figure of verification platform;
Fig. 3 is the detailed structure view of system bus in Fig. 2.
[embodiment]
Below in conjunction with the drawings and specific embodiments, medical electronics chip design of the present invention and verification platform are further illustrated.
As shown in Figure 1, be the structured flowchart of a kind of medical electronics chip design and verification system.This medical electronics chip design and verification system mainly comprise medical electronics chip design and verification platform 100, computing machine 300 and JTAG that medical electronics chip design and verification platform 100 and computing machine 300 are linked together (Joint Test Action Group, joint test working group) debugging emulation device 200.
As shown in Figure 2, medical electronics chip design and verification platform 100 mainly comprise jtag interface circuit, arm processor core on the printed-wiring board (PWB) that is distributed in a multilayer, comprise at least one FPGA for the IP kernel of physiological single processing (Field-Programmable Gate Array, field programmable gate array) circuit and peripheral interface circuit.
The jtag interface circuit is used for being connected with JTAG debugging emulation device 200, thereby platform 100 can be connected with JTAG debugging emulation device 200, and is connected with computing machine 300 by JTAG debugging emulation device 200.
Arm processor core is connected with the FPGA circuit with the jtag interface circuit.In the present embodiment, arm processor core is selected low-power consumption ARM7TDMI processor, is fit to the stricter application of volume, power consumption and performance requirement very much.Arm processor core can be downloaded IP kernel data, software program etc. from computing machine 300 by jtag interface circuit and JTAG debugging emulation device 200.By JTAG debugging emulation device 200, also can debug medical electronics chip design and verification platform 100 simultaneously, comprise the debugging breakpoints of C programmer, STEP debugs etc., and to the debugging of IP kernel.
The FPGA circuit is connected with peripheral interface circuit with arm processor core.This FPGA circuit (chip) can be based on SRAM technique, also can be based on FLASH technique, mainly realizes system bus, system component, Peripheral Interface and the IP kernel of using for processing of biomedical signals.The FPGA circuit has flexible configurability, can develop special chip for the different medical electronic product by the required IP kernel of flexible customization on the FPGA circuit.And IP kernel can oneself be developed, and also can buy commercial ripe IP kernel.
In the present embodiment, display control module, universal serial bus, ethernet controller, VGA module that the FPGA main circuit will comprise system bus and the Cathe buffer memory by this system bus and arm processor nuclear phase company, power management module, D/A converter module, watchdog circuit, clock module, memory management module, interrupt management module, dma controller, be comprised of lcd controller and GPIO controller, and at least one is for the IP kernel of physiological single processing.In the present embodiment, comprise analysis of spectrum IP kernel for physiological single processing (but be in Fig. 2 spread F FT module), convolution module, FIR filtration module and characteristic extracting module for the IP kernel of physiological single processing.In other embodiment, but can select one or more in spread F FT module, convolution module, FIR filtration module and characteristic extracting module according to the product that will develop, also can configure again other special I P core.In other embodiment, can delete as required or revise in above-mentioned FPGA circuit except for other modules the IP kernel of physiological single processing, such as display control module, ethernet controller etc.
System bus has adopted the low-power consumption ahb bus (LPAHB bus) of compatible AMBA bus, but standardization connects modules.
The Cache buffer memory is used for data and exchange is read in instruction soon.Power management module is used for the low-power dissipation power supply management of the system that realizes.Digital to analog converter is used for realizing that simulating signal changes to digital signal.Watchdog circuit is used for anti-locking system race and flies.Clock module provides stable clock signal to use to system, and clock and calendar can be provided, alarm clock, the functions such as periodic interruptions output.Memory management module is used for the management system storage unit.The management system storage unit mainly comprises the SRAM in peripheral interface circuit, SDRAM and FLASH.SRAM and SDRAM preserve ephemeral data and program when being mainly used in the program operation, and FLASH is used for preserving non-volatile data.The interrupt management unit is used for the system break management.Dma controller is used for data high-speed and moves.
Lcd controller is connected with LCD display in peripheral interface circuit.Lcd screen is used for picture and text and shows various information, and it can adopt touch-screen, to realize man-machine interaction.The GPIO controller is connected with LED display module in peripheral interface circuit, is mainly used in the signal designation effect.Universal serial bus is connected with serial line interface in peripheral interface circuit.In peripheral interface circuit serial line interface can comprise the IO interface, SPI interface, RS485 interface, at least a in RS232 interface and USB interface.Ethernet controller is connected with Ethernet interface RJ-45 interface in peripheral interface circuit, is used for realizing that network connects.The VGA module is connected with VGA interface in peripheral interface circuit, to realize and being connected of all kinds of monitors.
Peripheral interface circuit is except comprising the above-mentioned SRAM that mentions, SDRAM and FLASH storer, LCD display, the LED display module, IO interface, SPI interface, the RS485 interface, RS232 interface and USB interface outside RJ-45 interface and VGA interface, also can comprise crystal oscillator, power module, switch module and test point.Crystal oscillator provides medical electronics chip design and verification platform 100 required clock reference source, and it connects with FPGA circuit and arm processor nuclear phase respectively.Power module will be the required 1.2V of platform by the voltage transitions of power supply adaptor, 1.8V, and 2.5V, 3.3V and 5V think the modules power supply on platform.Switch module is used for controlling the startup of medical electronics chip design and verification platform 100 and modules thereof and closing.Test point is for convenience of the hardware platform test voltage, electric current and reserving.Understandable, in other embodiment, can delete as required or revise the configuration of peripheral interface circuit, such as storer, display etc.
Because bus low power occupies the system power dissipation major part, the present invention is optimized for the system bus power consumption specially, for data bus, adopts the BI coded system, for address bus, adopts Gray code.Specifically the reasons are as follows:
Circuit power consumption is comprised of quiescent dissipation and dynamic power consumption, and dynamic power consumption is comprised of switch power consumption and alternation power consumption (short-circuit dissipation) again, and circuit power consumption can be represented by formula (1):
In formula (1), P indication circuit power consumption, C is node capacitor, V
DDBe supply voltage, f is circuit work frequency, N
swBe the node sum that single clock cycle internal state changes, Q
scBe the transmission charge amount that the short-circuit current of single clock cycle interior nodes causes, I
LeakBe leakage current.First of formula is the switch power consumption, corresponding circuits logic when upset, internal node electric capacity discharge and recharge power consumption; Second of formula is short-circuit dissipation, the short-circuit dissipation of the VDD-to-VSS that in corresponding switching process, N pipe logic and the conducting simultaneously of P pipe logic cause; The 3rd of formula is quiescent dissipation, is mainly the leakage current between the anti-leakage current partially of PN junction and the source leakage of subthreshold value scope.
Switch power consumption and short-circuit dissipation by the visible circuit of following formula are all functions of frequency and voltage, can effectively reduce dynamic power consumption by the operating voltage that reduces power supply, but too low supply voltage can reduce the operating rate of system, reduce noise margin, simultaneously corresponding threshold voltage adjustment can increase leakage current.The dynamic power consumption of circuit mainly is directly proportional to the upset number of times of signal in circuit, and in cmos circuit, power consumption mainly comes from the dynamic power consumption of circuit, and system-level bus code technology can effectively reduce the toggle frequency of data and address bus signal, thereby effectively reduces system power dissipation.
The present invention adopts the bus code technology respectively data bus and address bus to be encoded.For data bus, adopt the BI coded system.The BI coding method is additional extra marking signal line on bus, is used for indicating before and after bus the signals upset situations in 2 continuous periods.This coding method is by judging that the Hamming distance that passes through on t-1 moment bus between the data that need to transmit on coded data and t moment bus is from (being the bit number that bus changes).From greater than N/2 (N is highway width) time, the data-conversion on bus also will put 1 when Hamming distance; Otherwise situation is opposite.The B-I coding can be represented by formula (2):
B in formula (2)
tRefer to t actual address constantly, B
tThe address after coding, H
tB
tAnd b
(t-1)Different figure place.At receiving end, when INV is " 1 ", data-conversion is received; When INV was " 0 ", data were not done any processing.
B-I decoding formula can be represented by formula (3):
J in formula (3)
tBe decoded address bus.
For address bus, adopt Gray code.Gray (Gray) code is a kind of non-weighted code, adopts absolute addressing mode, when it is changed between any two adjacent numbers, only has a numerical digit to change.The variation figure place of having encoded when it has reduced by a state to next adjacent states widely.If natural binary code is: B
n-1B
n-2... B
2B
1B
0Corresponding Gray code is: G
n-1G
n-2... G
2G
1G
0
The calculating of Gray code can be expressed as by formula (4):
Owing to only having a numerical digit to change between adjacent two numbers of Gray code, so be applicable to address bus, when reading especially in a large number the continuation address data, Gray code can effectively reduce the upset 30%-45% of address wire.The maximum code efficiency of Gray code is 50%.Low-power dissipation system bus structure in the present embodiment as shown in Figure 3.
In use, can move EDA on computing machine 300 develops software, XILINX ISE instrument for example, the IP kernel that will realize with hardware description language (for example Verilog language) downloads in FPGA circuit in medical electronics chip design and verification platform 100 or in FLASH by JTAG debugging emulation device 200.Simultaneously can also be on computing machine 300 C language or assembly language be downloaded to through compilation tool (for example RVDS development kit) in the program space of arm processor core management (SRAM, SDRAM or FLASH).When system debug, can debug by 200 pairs of medical electronics chip designs of JTAG debugging emulation device and verification platform 100, comprise the debugging breakpoints of C programmer, STEP debugging etc. also can be debugged the IP kernel in the FPGA circuit.
In sum, adopt medical electronics chip design of the present invention and verification platform 100, the designer can flexible configuration develop the required all kinds of IP kernels of medical electronics product, carry out IP reuse, or revise for the parameter of the IP kernel of physiological single processing or change algorithm to develop the special chip for the different medical electronic product, avoid the overlapping development of the identity function part of a plurality of products, shortened product development cycle, reduce product development cost.In designing and developing, can simultaneously hardware circuit and software section be downloaded on the FPGA circuit, can realize soft and hardware emulation simultaneously, thereby reach the purpose of software and hardware cooperating simulation.
The above embodiment has only expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the scope of the claims of the present invention.Should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (2)
1. a medical electronics chip design and verification platform, is characterized in that, comprising:
The jtag interface circuit is used for being connected with computing machine by JTAG debugging emulation device;
Arm processor core is connected with described jtag interface circuit;
The FPGA circuit, connect with described arm processor nuclear phase, this FPGA circuit comprises system bus and the watchdog module, clock module, memory management module and at least one IP kernel for physiological single processing that connect by this system bus and described arm processor nuclear phase;
But described at least one IP kernel for physiological single processing comprises spread F FT module, convolution module, at least one in FIR filtration module and characteristic extracting module;
Described storer comprises at least a storer in FLASH storer, SRAM storer and SDRAM storer; Described FPGA circuit also comprises at least one module in Cache buffer memory, interrupt management module, dma controller, power management module, D/A converter module, display control module, universal serial bus, Ethernet interface and the VGA interface that connects by described system bus and described arm processor nuclear phase; And
The peripheral interface circuit that comprises storer and crystal oscillating circuit; Described peripheral interface circuit also comprises at least one module with the display of described display control module, the power circuit for the power supply of platform modules, the switch module that is used for controlling working platform, serial line interface, Ethernet interface, VGA interface; Described display control module comprises lcd controller and GPIO controller, and described display comprises LCD display and LED display module; Described peripheral interface circuit also comprises a plurality of test points be used to carrying out platform voltage and current detecting; Described system bus is the low-power consumption ahb bus of compatible AMBA bus; Address bus in described system bus adopts Gray code; For data bus, adopt the BI coded system;
Described storer is connected with the memory management module of described FPGA circuit, and described crystal oscillating circuit and clock module and arm processor nuclear phase connect;
In use, move on computers EDA and develop software, the IP kernel that will realize with hardware description language downloads in FPGA circuit in medical electronics chip design and verification platform or in FLASH by JTAG debugging emulation device.
2. medical electronics chip design according to claim 1 and verification platform, is characterized in that, described jtag interface circuit, arm processor core and FPGA circuit are distributed on the printed-wiring board (PWB) of a multilayer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110071283 CN102129524B (en) | 2011-03-23 | 2011-03-23 | Design and verification platform of medical electronic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110071283 CN102129524B (en) | 2011-03-23 | 2011-03-23 | Design and verification platform of medical electronic chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102129524A CN102129524A (en) | 2011-07-20 |
| CN102129524B true CN102129524B (en) | 2013-11-06 |
Family
ID=44267607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201110071283 Active CN102129524B (en) | 2011-03-23 | 2011-03-23 | Design and verification platform of medical electronic chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102129524B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102541568A (en) * | 2012-01-05 | 2012-07-04 | 北京工业大学 | Graphic programming development method based on Cortex-M3-series microprocessor |
| CN102664836B (en) * | 2012-03-29 | 2015-12-02 | 中国科学院计算技术研究所 | A kind of Prototype Verification Platform for broadband wireless communications digital baseband processor |
| CN103142209B (en) * | 2013-03-12 | 2015-08-12 | 广州天高软件科技有限公司 | Portable vision tester |
| CN105989897A (en) * | 2015-03-05 | 2016-10-05 | 中兴通讯股份有限公司 | Test method and device of synchronous dynamic random access memory SDRAM |
| CN104869029A (en) * | 2015-04-03 | 2015-08-26 | 深圳市前海安测信息技术有限公司 | Node network and data transmission method based on edge detection |
| CN105208380B (en) * | 2015-10-20 | 2018-05-25 | 硅谷数模半导体（北京）有限公司 | Verification platform and system |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7165229B1 (en) * | 2004-05-24 | 2007-01-16 | Altera Corporation | Generating optimized and secure IP cores |
| US20070106960A1 (en) * | 2005-11-09 | 2007-05-10 | L-3 Integrated Systems Company | System and method for the development and distribution of a VHDL intellectual property core |
| US7484188B2 (en) * | 2006-03-15 | 2009-01-27 | Marvell International Technology Ltd. | On-chip test circuit and method for testing of system-on-chip (SOC) integrated circuits |
| US8046727B2 (en) * | 2007-09-12 | 2011-10-25 | Neal Solomon | IP cores in reconfigurable three dimensional integrated circuits |
| CN101276318B (en) * | 2008-05-12 | 2010-06-09 | 北京航空航天大学 | Direct access data transmission control apparatus based on PCI-E bus |
| CN201955784U (en) * | 2011-03-23 | 2011-08-31 | 中国科学院深圳先进技术研究院 | Medical electronic chip design and test platform |
-
2011
- 2011-03-23 CN CN 201110071283 patent/CN102129524B/en active Active
Non-Patent Citations (10)
| Title |
|---|
| 凌朝东等.基于NIOSII的便携式远程医疗监护器硬件平台的设计.《仪器仪表学报》.2008,第29卷(第2期),337-341. |
| 基于ARM软核的AHB_PCCard主机端IP核控制寄存器关键模块设计;张来;《中国优秀硕士学位论文全文数据库信息科技辑》;20071015;I137-9 * |
| 基于FPGA的JPEG压缩编码IP核设计;李春蕾;《中国优秀硕士学位论文全文数据库信息科技辑》;20100615;I138-541 * |
| 基于FPGA的M-JPEG编解码器的研究与设计;王张刚;《中国优秀硕士学位论文全文数据库信息科技辑》;20110315;I136-479 * |
| 基于IP 核的FPGA FFT 算法模块的设计与实现;窦秀梅等;《无线电工程》;20080831;第38卷(第8期);29-31 * |
| 基于NIOSII的便携式远程医疗监护器硬件平台的设计;凌朝东等;《仪器仪表学报》;20080229;第29卷(第2期);337-341 * |
| 张来.基于ARM软核的AHB_PCCard主机端IP核控制寄存器关键模块设计.《中国优秀硕士学位论文全文数据库信息科技辑》.2007, |
| 李春蕾.基于FPGA的JPEG压缩编码IP核设计.《中国优秀硕士学位论文全文数据库信息科技辑》.2010,I138-541. |
| 王张刚.基于FPGA的M-JPEG编解码器的研究与设计.《中国优秀硕士学位论文全文数据库信息科技辑》.2011,I136-479. |
| 窦秀梅等.基于IP 核的FPGA FFT 算法模块的设计与实现.《无线电工程》.2008,第38卷(第8期),29-31. |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102129524A (en) | 2011-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102129524B (en) | Design and verification platform of medical electronic chip | |
| CN102934098A (en) | Reducing simultaneous switching outputs using data bus inversion signaling | |
| DE112006001290T5 (en) | Dynamic bus parking | |
| CN104820637A (en) | Handheld type USB3.0 protocol analyzer | |
| CN109189619A (en) | I2C bus compatible test method, system, storage medium and equipment | |
| CN203260029U (en) | System chip prototype verification debugging device based on field programmable gate array (FPGA) | |
| CN104516477A (en) | Techniques for entering a low power state | |
| CN106774790A (en) | One kind wears display device and its method for managing power supply and device | |
| CN109032062A (en) | A kind of PCIE switching chip | |
| Sayyah et al. | Virtual platform-based design space exploration of power-efficient distributed embedded applications | |
| CN201955784U (en) | Medical electronic chip design and test platform | |
| US10324517B2 (en) | FPGA-based system power estimation apparatus and method | |
| US9378027B2 (en) | Field-programmable module for interface bridging and input/output expansion | |
| Kim et al. | System-level online power estimation using an on-chip bus performance monitoring unit | |
| Rodríguez et al. | Execution modeling in self-aware FPGA-based architectures for efficient resource management | |
| Yang et al. | A low-cost and high-performance embedded system architecture and an evaluation methodology | |
| CN206684533U (en) | Wechat remote control chip | |
| CN203250312U (en) | Extensible common core processing daughter board with interferences | |
| CN104461796B (en) | JTAG debugging modules and adjustment method for embedded 8051CPU | |
| CN101603853A (en) | Special integrated circuit for electronic scale | |
| CN104424086A (en) | Computer error detection module and method | |
| McGrath et al. | Key sensor technology components: hardware and software overview | |
| CN205247119U (en) | Gradual signal real -time supervision device of low frequency | |
| CN213545262U (en) | Processor computing module based on Shenwei 121 | |
| CN112711213A (en) | Navigation acquisition resolving Soc processing system based on RiscV kernel and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |