CN111475452A - DisplayPort interface speed bridge system for FPGA prototype verification - Google Patents
DisplayPort interface speed bridge system for FPGA prototype verification Download PDFInfo
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- CN111475452A CN111475452A CN202010371038.5A CN202010371038A CN111475452A CN 111475452 A CN111475452 A CN 111475452A CN 202010371038 A CN202010371038 A CN 202010371038A CN 111475452 A CN111475452 A CN 111475452A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
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Abstract
The invention belongs to the field of integrated circuit design verification, and discloses a DisplayPort interface speed bridge system for FPGA prototype verification, which comprises a data receiving and analyzing module, a data flow control module, a gate, a test chart generating module, a write cache management module, a read cache management module and a cache, wherein the system is a hardware scheme and realizes the functions of identifying training data and image data, caching data frames, reading and outputting data frames and the like, an AXI4 bus interface protocol is adopted by a cache interface, all the functions are RT L which can be integrated, the functions can be integrated in an FPGA where a verified DisplayPort controller is positioned, no influence is caused on other modules in the verified system, the hardware and test cost are saved, and the test efficiency and the test reliability are improved.
Description
The technical field is as follows:
the invention relates to the field of integrated circuit design verification, in particular to a DisplayPort interface speed bridge system for FPGA (field programmable Gate array) prototype verification.
Background art:
the DisplayPort controller mainly comprises 2 layers, namely a data link layer (L INK layer) for generating output data packets and a physical layer (PHY layer) for finishing data physical transmission.
When the FPGA prototype verification system is used for verifying the DisplayPort interface in the chip, the problem of unmatched speed exists. The speed mismatch means that the system operation clock frequency of the FPGA prototype verification platform during system level verification is generally about 10MHz, and even in an image with 640x480 resolution and 60 frame refresh rate, the system operation clock frequency of the FPGA prototype verification platform is required to be at least 50MHz, and a higher operation clock frequency is required for a verification scene with higher resolution, so that the operation clock frequency of the FPGA prototype verification platform system is generally far lower than the hardware requirement of a DisplayPort interface, which may cause a display to fail to normally display, and may not verify the DisplayPort interface function. A DisplayPort interface speed bridge is therefore needed to address the speed mismatch between the proto-verification system running clock frequency and the DisplayPort interface. The prior DisplayPort interface speed bridge has two implementation schemes, wherein the first scheme is based on a virtual display technology, is displayed in a software mode in a simulation mode and can be applied to a formal verification method and a hardware simulation accelerator verification method. In another scheme, based on real hardware, the DisplayPort receiving controller is adopted to analyze and cache data, and then repeated data frames are sent again through other physical interfaces, such as VGA, HDMI or ethernet, so as to meet the requirement of the display refresh rate on the data amount.
The two above schemes for designing the DisplayPort interface speed bridge have the following disadvantages: the main drawback of the software-based solution is that its verification efficiency is much lower than that of the hardware solution because the DisplayPort software simulation based on the virtual reality technology is slow and the amount of computation is huge. The hardware-based solution requires purchasing DisplayPort receiving controller ip (intellectual property), which increases the cost of verification and complexity of the verification environment.
The invention content is as follows:
in order to solve the above problems, the present invention provides a DisplayPort interface speed bridge system for FPGA prototype verification, which is a hardware solution, and can solve the speed mismatch problem between the FPGA prototype verification system and the DisplayPort interface without using DisplayPort to receive a controller IP.
The invention realizes the functions of identifying training data and image data, caching data frames, reading and outputting data frames and the like, and the caching interface adopts an AXI4 bus interface protocol, all the functions are RT L which can be integrated, can be integrated in an FPGA where a verified DisplayPort controller is positioned, has no influence on other modules in a verified system, saves hardware and test cost, and improves test efficiency and test reliability.
In order to achieve the purpose, the invention adopts the following technical scheme:
a DisplayPort interface speed bridge system for FPGA prototype verification comprises a data receiving and analyzing module, a data flow control module, a gate, a test chart generating module, a write cache management module, a read cache management module and a cache;
the data receiving and analyzing module is used for analyzing whether current data input by an L INK layer of the DisplayPort is training data or image data, if the current input data is the training data, the current input data is sent to the gate, and if the current input data is the image data, the current input data is sent to the write cache management module;
the data receiving and analyzing module is also used for detecting whether the current character is training character, blanking field starting character or blanking field ending character information, generating a control signal according to the detection result and outputting the control signal to the data flow control module;
the data flow control module is used for guiding the destination of data flow, receiving the control information output by the data receiving and analyzing module, outputting address signals to the writing cache management module and the reading cache management module to realize cache reading and writing address management, and outputting control signals to the gate to realize the shunt control of training data and image data flow;
the gate selects one of the training data output by the data receiving and analyzing module, the image data output by the read buffer management module or the test chart generated by the test chart generating module according to the control signal output by the data flow control module, and outputs the selected data to the PHY layer of the DisplayPort controller;
the test pattern generation module is used for generating a piece of specific image data to solve the problem that a buffer memory does not have a free position of a complete image frame when a first frame image is buffered, and outputting a test pattern to the gate;
the write cache management module writes the image data output by the data analysis module into a cache of the FPGA through an AXI4 bus interface according to the control signal output by the data flow control module;
the read cache management module reads the data in the cache of the FPGA through an AXI4 bus interface according to the control signal output by the data flow control module and outputs the read image data to a gate;
the cache of the FPGA selects a DDR3(Double Data Rate 3) memory, and an AXI4-memory interface is adopted as an interface protocol.
As a further improvement of the present invention, the data receiving and parsing module comprises the following working steps:
step S11: starting;
step S12: judging whether the training character is finished, if not, continuing to execute the step S12, if so, outputting a training character finishing flag bit to the data flow control module and executing the step S13;
step S13: judging whether blanking field line data are received, if so, executing step S14, otherwise, continuing to execute step S13;
step S14: outputting an image data transmission flag bit to the data flow control module;
step S15: receiving image line data;
step S16: and judging whether the transmission of the current frame image data is finished, if so, returning to the step S13 after the frame count is accumulated by 1, and otherwise, returning to the step S15.
As a further improvement of the present invention, the data flow control module comprises the following working steps:
step S21: starting;
step S22: judging whether a training character ending flag bit output by the data receiving and analyzing module is received, if so, entering a step S23, otherwise, continuing to execute the step S22;
step S23: enabling the gate module and selecting a training data channel;
step S24: judging whether the image data transmission flag bit output by the data receiving and analyzing module is received, if so, executing step S25, otherwise, continuing to execute step S24;
step S25: enabling the test image generation module to generate a test image and output the test image to the gate, enabling the gate module to select a test image data channel, enabling the write cache management module to write the first frame image into the cache;
step S26: judging whether the first frame image is cached completely, if so, executing the step S27, otherwise, continuing to execute the step S26;
step S27: enabling the read cache management module, enabling the gate module and selecting a read cache data channel;
step S28: enabling the write cache management module to continue caching the next frame of image data;
step S29: judging whether the next frame of image data is completely written into the cache, if so, executing step S2B, otherwise, executing step S2A;
step S2A: enabling the reading cache management module to repeatedly read the current frame image data, and returning to the step S28;
step S2B: enabling the read buffer management module to read the next frame of image data written into the buffer in the step S28, and returning to the step S28;
as a further improvement of the invention, a DDR4(Double Data Rate 4) memory is selected as the cache of the FPGA, and an AXI4-memory interface is adopted as an interface protocol.
The invention has the beneficial effects that: the DisplayPort interface speed bridge for FPGA prototype verification is a hardware implementation scheme, and can realize high-efficiency DisplayPort interface verification; meanwhile, the invention does not need to use DisplayPort to receive controller IP, thus reducing economic cost and complexity of verification environment.
Description of the drawings:
FIG. 1 is a schematic structural view of the present invention;
FIG. 2 is a flow chart of the data receiving and parsing module;
fig. 3 is a flow chart of the data flow control module.
Description of reference numerals:
the device comprises a data receiving and analyzing module-1, a data flow control module-2, a gate-3, a test chart generating module-4, a write buffer management module-5, a read buffer management module-6, a buffer-7 and a PHY layer-8 of a DisplayPort controller.
The specific implementation mode is as follows:
in the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
As shown in fig. 1, a DisplayPort interface speed bridge system for FPGA prototype verification includes a data receiving and parsing module, a data flow control module, a gate, a test chart generating module, a write buffer management module, a read buffer management module, and a buffer.
As shown in fig. 1, the data receiving and parsing module is configured to analyze whether current data input by an L INK layer of the DisplayPort is training data or image data, send the current input data to the gate if the current input data is the training data, and send the current input data to the write buffer management module if the current input data is the image data;
as shown in fig. 1, the data receiving and parsing module further detects whether the current character is training character, blanking start character or blanking end character information, and generates a control signal according to the detection result and outputs the control signal to the data flow control module;
as shown in fig. 1, the data flow control module is configured to direct the direction of a data flow, receive control information output by the data receiving and parsing module, output address signals to the write buffer management module and the read buffer management module to implement buffer read and write address management, and output control signals to the gate to implement shunt control of training data and an image data flow;
as shown in fig. 1, the gate selects one of the training data output by the data receiving and parsing module, the image data output by the read buffer management module, or the test chart generated by the test chart generation module according to the control signal output by the data flow control module, and outputs the selected data to the PHY layer of the DisplayPort controller;
as shown in fig. 1, the test pattern generating module is configured to generate a specific image data to solve a situation that there is no empty space in the buffer memory for a complete image frame when the first frame image is buffered, and output the test pattern to the gate;
as shown in fig. 1, the write buffer management module writes the image data output by the data parsing module into the buffer of the FPGA through an AXI4 bus interface according to the control signal output by the data flow control module;
as shown in fig. 1, the read buffer management module reads data in the buffer of the FPGA through an AXI4 bus interface and outputs the read image data to a gate according to the control signal output by the data flow control module;
the cache of the FPGA selects a DDR3(Double Data Rate 3) or DDR4(Double Data Rate 4) memory, and an AXI4-memory interface is adopted as an interface protocol.
As shown in fig. 2, the data receiving and parsing module includes the following steps:
step S11: starting;
step S12: judging whether the training character is finished, if not, continuing to execute the step S12, if so, outputting a training character finishing flag bit to the data flow control module and executing the step S13;
step S13: judging whether blanking field line data are received, if so, executing step S14, otherwise, continuing to execute step S13;
step S14: outputting an image data transmission flag bit to the data flow control module;
step S15: receiving image line data;
step S16: and judging whether the transmission of the current frame image data is finished, if so, returning to the step S13 after the frame count is accumulated by 1, and otherwise, returning to the step S15.
As shown in fig. 3, the data flow control module works as follows:
step S21: starting;
step S22: judging whether a training character ending flag bit output by the data receiving and analyzing module is received, if so, executing the step S23, otherwise, continuing to execute the step S22;
step S23: enabling the gate module and selecting a training data channel;
step S24: judging whether the image data transmission flag bit output by the data receiving and analyzing module is received, if so, executing step S25, otherwise, continuing to execute step S24;
step S25: enabling the test image generation module to generate a test image and output the test image to the gate, enabling the gate module to select a test image data channel, enabling the write cache management module to write the first frame image into the cache;
step S26: judging whether the first frame image is cached completely, if so, executing the step S27, otherwise, continuing to execute the step S26;
step S27: enabling the read cache management module, enabling the gate module and selecting a read cache data channel;
step S28: enabling the write cache management module to continue caching the next frame of image data;
step S29: judging whether the next frame of image data is completely written into the cache, if so, executing step S2B, otherwise, executing step S2A;
S2A, enabling the read buffer management module to repeatedly read the current frame image data, and returning to the step S28;
step S2B, the read buffer management module is enabled, the next frame image data written into the buffer in step S28 is read, and the process returns to step S28.
The above description is of the preferred embodiment of the invention. It is to be understood that the invention is not limited to the particular embodiments described above, in that devices and structures not described in detail are understood to be implemented in a manner common in the art; those skilled in the art can make many possible variations and modifications to the disclosed embodiments, or modify equivalent embodiments to equivalent variations, without departing from the spirit of the invention, using the methods and techniques disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.
Claims (4)
1. A DisplayPort interface speed bridge system for FPGA prototype verification is characterized by comprising a data receiving and analyzing module, a data flow control module, a gate, a test chart generating module, a write cache management module, a read cache management module and a cache;
the data receiving and analyzing module is used for analyzing whether current data input by an L INK layer of the DisplayPort is training data or image data, if the current input data is the training data, the current input data is sent to the gate, and if the current input data is the image data, the current input data is sent to the write cache management module;
the data receiving and analyzing module is also used for detecting whether the current character is training character, blanking field starting character or blanking field ending character information, generating a control signal according to the detection result and outputting the control signal to the data flow control module;
the data flow control module is used for guiding the destination of data flow, receiving the control information output by the data receiving and analyzing module, outputting address signals to the writing cache management module and the reading cache management module to realize cache reading and writing address management, and outputting control signals to the gate to realize the shunt control of training data and image data flow;
the gate selects one of the training data output by the data receiving and analyzing module, the image data output by the read buffer management module or the test chart generated by the test chart generating module according to the control signal output by the data flow control module, and outputs the selected data to the PHY layer of the DisplayPort controller;
the test pattern generation module is used for generating a piece of specific image data to solve the problem that a buffer memory does not have a free position of a complete image frame when a first frame image is buffered, and outputting a test pattern to the gate;
the write cache management module writes the image data output by the data analysis module into a cache of the FPGA through an AXI4 bus interface according to the control signal output by the data flow control module;
the read cache management module reads the data in the cache of the FPGA through an AXI4 bus interface according to the control signal output by the data flow control module and outputs the read image data to a gate;
DDR3 memory is selected as the cache of the FPGA, and an AXI4-memory interface is adopted as an interface protocol.
2. The DisplayPort interface speed bridge system for FPGA proto-verification of claim 1, wherein said data receiving parsing module operates by the steps of:
step S11: starting;
step S12: judging whether the training character is finished, if not, continuing to execute the step S12, if so, outputting a training character finishing flag bit to the data flow control module and executing the step S13;
step S13: judging whether blanking field line data are received, if so, executing step S14, otherwise, continuing to execute step S13;
step S14: outputting an image data transmission flag bit to the data flow control module;
step S15: receiving image line data;
step S16: and judging whether the transmission of the current frame image data is finished, if so, returning to the step S13 after the frame count is accumulated by 1, and otherwise, returning to the step S15.
3. The DisplayPort interface speed bridge system for FPGA proto-verification of claim 1, wherein said data flow control module operates by the steps of:
step S21: starting;
step S22: judging whether a training character ending flag bit output by the data receiving and analyzing module is received, if so, entering a step S23, otherwise, continuing to execute the step S22;
step S23: enabling the gate module and selecting a training data channel;
step S24: judging whether the image data transmission flag bit output by the data receiving and analyzing module is received, if so, executing step S25, otherwise, continuing to execute step S24;
step S25: enabling the test image generation module to generate a test image and output the test image to the gate, enabling the gate module to select a test image data channel, enabling the write cache management module to write the first frame image into the cache;
step S26: judging whether the first frame image is cached completely, if so, executing the step S27, otherwise, continuing to execute the step S26;
step S27: enabling the read cache management module, enabling the gate module and selecting a read cache data channel;
step S28: enabling the write cache management module to continue caching the next frame of image data;
step S29: judging whether the next frame of image data is completely written into the cache, if so, executing step S2B, otherwise, executing step S2A;
step S2A: enabling the reading cache management module to repeatedly read the current frame image data, and returning to the step S28;
step S2B: the read buffer management module is enabled to read the next frame of image data written in the buffer in step S28, and the process returns to step S28.
4. The DisplayPort interface speed bridge system for FPGA proto-verification according to claim 1, wherein the buffer of the FPGA uses DDR4 memory, and the interface protocol uses AXI4-memory interface.
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