CN112201700A - Solar cell and preparation method thereof - Google Patents

Solar cell and preparation method thereof Download PDF

Info

Publication number
CN112201700A
CN112201700A CN202011059369.1A CN202011059369A CN112201700A CN 112201700 A CN112201700 A CN 112201700A CN 202011059369 A CN202011059369 A CN 202011059369A CN 112201700 A CN112201700 A CN 112201700A
Authority
CN
China
Prior art keywords
layer
type
passivation layer
doping
type doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011059369.1A
Other languages
Chinese (zh)
Other versions
CN112201700B (en
Inventor
杨洁
武禄
张昕宇
郑霈霆
金浩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Anhui Jinko Energy Co ltd
Original Assignee
Zhejiang Jinko Solar Co Ltd
Jinko Solar Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang Jinko Solar Co Ltd, Jinko Solar Co Ltd filed Critical Zhejiang Jinko Solar Co Ltd
Priority to CN202210519969.4A priority Critical patent/CN114975683B/en
Priority to CN202011059369.1A priority patent/CN112201700B/en
Publication of CN112201700A publication Critical patent/CN112201700A/en
Application granted granted Critical
Publication of CN112201700B publication Critical patent/CN112201700B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0682—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Sustainable Energy (AREA)
  • Photovoltaic Devices (AREA)

Abstract

The application relates to the field of photovoltaics, and provides a solar cell and a preparation method thereof, wherein the method comprises the following steps: carrying out N-type doping treatment on the back surface of the textured N-type semiconductor substrate to form a first N-type doping layer; carrying out P-type doping treatment on the front surface of the textured N-type semiconductor substrate to form a P-type emitter, wherein the P-type emitter and the N-type semiconductor substrate form a PN junction; forming a dielectric layer on the upper surface of the P-type emitter; forming a second N-type doped layer on the upper surface of the dielectric layer, wherein the crystalline state of the second N-type doped layer comprises one or more of an amorphous phase, a microcrystalline phase or a polycrystalline phase; forming a front passivation layer on the upper surface of the second N-type doped layer, and forming a back passivation layer on the lower surface of the first N-type doped layer; and forming an electrode on the front passivation layer and/or the back passivation layer. According to the solar cell and the preparation method thereof, the passivation effect of the cell is enhanced, and the conversion efficiency of the cell is improved.

Description

Solar cell and preparation method thereof
Technical Field
The present disclosure relates to the field of photovoltaic cell technology, and in particular, to a solar cell and a method for manufacturing the same.
Background
The Topcon battery realizes the back passivation by means of a tunneling effect, and the back structure of the existing Topcon battery sequentially comprises a substrate, a tunneling oxidation layer, a doped polycrystalline silicon layer and a back passivation layer from inside to outside. Because the doped polysilicon layer and the back passivation layer are respectively deposited and formed in two different devices, some unsaturated defects are inevitably introduced between the doped polysilicon layer and the back passivation layer, carrier recombination and electrical property loss are easily caused, and the passivation effect is not ideal. Therefore, it is necessary to research methods for improving the back passivation effect to further improve the battery conversion efficiency.
Disclosure of Invention
In view of this, the present application provides a solar cell and a method for manufacturing the same, which can reduce the unsaturated defect between the doped polysilicon layer and the passivation layer (such as the silicon nitride layer), effectively improve the passivation effect, and improve the cell conversion efficiency.
The application provides a solar cell preparation method, which comprises the following steps:
carrying out N-type doping treatment on the back surface of the textured N-type semiconductor substrate to form a first N-type doping layer;
carrying out P-type doping treatment on the front surface of the textured N-type semiconductor substrate to form a P-type emitter, wherein the P-type emitter and the N-type semiconductor substrate form a PN junction;
forming a dielectric layer on the upper surface of the P-type emitter;
forming a second N-type doped layer on the upper surface of the dielectric layer, wherein the crystalline state of the second N-type doped layer comprises one or more of an amorphous phase, a microcrystalline phase or a polycrystalline phase;
forming a front passivation layer on the upper surface of the second N-type doped layer, and forming a back passivation layer on the lower surface of the first N-type doped layer; and
forming an electrode on the front passivation layer and/or the back passivation layer.
In one possible embodiment, the dielectric layer has a thickness of 0.5nm to 2 nm; and/or the dielectric layer comprises at least one of silicon oxide, aluminum oxide, titanium oxide, gallium oxide, silicon nitride and hafnium oxide.
In one possible embodiment, depositing an N-type doped layer on the upper surface of the dielectric layer includes:
and depositing and forming a polycrystalline silicon layer on the upper surface of the dielectric layer, and carrying out doping treatment to form the N-type doped polycrystalline silicon layer.
In one possible embodiment, depositing an N-type doped layer on the surface of the dielectric layer includes:
depositing and forming an amorphous silicon layer on the surface of the dielectric layer, and carrying out doping treatment to form the N-type doped amorphous silicon layer;
and annealing the N-type doped amorphous silicon layer, wherein the annealed N-type doped amorphous silicon layer is converted into N-type doped mixed phase crystalline silicon, and the mixed phase crystalline silicon comprises at least two of amorphous phase crystalline silicon, microcrystalline phase crystalline silicon or polycrystalline phase crystalline silicon.
In one possible embodiment, the thickness of the first N-type doped layer is 1nm to 10 nm;
the doping element of the first N-type doping layer is phosphorus or arsenic, and the doping sheet resistance of the first N-type doping layer is 20-300 omega/sqr.
In a feasible implementation mode, the doping element of the P-type emitter is boron or gallium, and the doping sheet resistance of the P-type emitter is 80-400 Ω/sqr.
In a possible embodiment, the doping process is performed by any one of a high temperature diffusion process, a slurry doping process, or an ion implantation process.
In a possible embodiment, the thickness of the front passivation layer and/or the back passivation layer is 60nm to 150nm, and the material of the front passivation layer and/or the back passivation layer includes at least one of hydrogen-containing silicon nitride, hydrogen-containing silicon oxynitride, hydrogen-containing silicon oxycarbide, and hydrogen-containing silicon oxynitride.
In one possible embodiment, forming an electrode on the front passivation layer and/or the back passivation layer includes:
carrying out metallization treatment on the surface of the front passivation layer to form a front electrode, wherein the front electrode penetrates through the front passivation layer, the second N-type doping layer and the dielectric layer to form electric contact with the P-type emitter;
and carrying out metallization treatment on the surface of the back passivation layer to form a back electrode, wherein the back electrode penetrates through the back passivation layer to form electric contact with the first N-type doping layer.
The application also provides a solar cell, which is obtained by the solar cell preparation method, and the solar cell comprises a front electrode, a front passivation layer, a second N-type doping layer, a dielectric layer, a P-type emitter, a semiconductor substrate, a first N-type doping layer, a back passivation layer and a back electrode which are sequentially arranged from top to bottom.
The technical scheme of the application has at least the following beneficial effects:
the dielectric layer is formed on the surface of the P + heavily doped P-type emitter, and the N-type doped layer is formed on the surface of the dielectric layer, so that the passivation effect can be optimized, the preparation method is simple, and the preparation cost of the solar cell can be effectively reduced.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a solar cell according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a solar cell according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another solar cell provided in an embodiment of the present application.
Detailed Description
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In a first aspect, embodiments of the present application provide a method for manufacturing a solar cell, including the following steps:
carrying out N-type doping treatment on the back surface of the textured N-type semiconductor substrate to form a first N-type doping layer;
carrying out P-type doping treatment on the front surface of the textured N-type semiconductor substrate to form a P-type emitter, wherein the P-type emitter and the N-type semiconductor substrate form a PN junction;
forming a dielectric layer on the upper surface of the P-type emitter;
forming a second N-type doped layer on the upper surface of the dielectric layer, wherein the crystalline state of the second N-type doped layer comprises one or more of an amorphous phase, a microcrystalline phase, or a polycrystalline phase;
forming a front passivation layer on the upper surface of the second N-type doped layer, and forming a back passivation layer on the lower surface of the first N-type doped layer; and
forming an electrode on the front passivation layer and/or the back passivation layer.
In the scheme, the P + heavily doped P-type emitter, the dielectric layer, the second N-type doped layer and the front passivation layer are arranged on the front side of the battery, so that the back passivation effect of the battery can be effectively improved, and the conversion efficiency of the battery is improved.
Hereinafter, a method for manufacturing an N-type battery will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, which are only a part of the embodiments of the present invention, but not all of them. All other embodiments obtained by a person skilled in the art without making any inventive step are within the scope of protection of the present invention.
Fig. 1 is a flowchart of a method for manufacturing a solar cell according to this embodiment, and as shown in fig. 1, embodiment 1 of this application provides a method for manufacturing a solar cell, including the following steps:
in step S10, N-type doping treatment is performed on the back surface of the textured N-type semiconductor substrate to form a first N-type doped layer.
Specifically, the front and back sides of the N-type semiconductor substrate may be subjected to a texturing process to form a textured or surface texture structure (e.g., a pyramid structure) prior to the doping process. The texturing process may be chemical etching, laser etching, mechanical method, plasma etching, etc., and is not limited herein. Illustratively, the front and back surfaces of the silicon wafer can be subjected to texturing treatment by using a NaOH solution, and the etching of the NaOH solution has anisotropy, so that a pyramid structured texture surface can be prepared.
In this embodiment, the surface of the silicon substrate has a texture structure through texturing, so that a light trapping effect is generated, the light absorption quantity of the solar cell is increased, and the conversion efficiency of the solar cell is improved.
In some embodiments, the front surface of the N-type semiconductor substrate is a surface facing the sun, and the back surface is a surface facing away from the sun. It should be further noted that the semiconductor substrate may be a crystalline silicon substrate (silicon substrate), such as a polycrystalline silicon substrate, a monocrystalline silicon substrate, or a monocrystalline-like silicon substrate, and the specific type of the semiconductor substrate is not limited in the embodiments of the present invention.
Optionally, before the texturing process, a step of cleaning the semiconductor substrate can be further included to remove metal and organic contaminants on the surface.
The thickness of the first N-type doped layer is 20nm to 300nm, and may be, for example, 20nm, 40nm, 50nm, 80nm, 100nm, 120nm, 150nm, 200nm, 220nm, 250nm, or 300 nm. Other values within the range are also possible and are not limited herein.
The doping element of the first N-type doping layer is phosphorus or arsenic, the doping sheet resistance of the first N-type doping layer is 10 omega/sqr-200 omega/sqr, for example, 10 omega/sqr, 30 omega/sqr, 50 omega/sqr, 80 omega/sqr, 100 omega/sqr, 120 omega/sqr, 150 omega/sqr, 180 omega/sqr, 200 omega/sqr, etc.
It is to be understood that the first N-doped layer is an N + doped layer, and in some embodiments, the first N-doped layer may also be an N + passivation contact structure, such as a Topcon passivation structure.
Within the proper diffusion sheet resistance or thickness range of the first N-type doping layer, the photoelectric conversion efficiency of the solar cell is improved, and the performance of the solar cell is improved.
And step S20, carrying out P-type doping treatment on the front surface of the textured N-type semiconductor substrate to form a P-type emitter, wherein the P-type emitter and the N-type semiconductor substrate form a PN junction.
The doping element of the P-type emitter is boron or gallium, and can be other trivalent elements. The doping sheet resistance of the P-type emitter is 80-400 omega/sqr, such as 80-150 omega/sqr, 100-150 omega/sqr, 200-200 omega/sqr, 250-300 omega/sqr, 350-omega/sqr, 400-omega/sqr, etc.
The thickness of the P-type emitter is 0.4um to 2.0um, and can be, for example, 0.4um, 0.6um, 0.8um, 1.0um, 1.2um, 1.5um, 1.8um or 2.0 um; other values within the range are also possible and are not limited herein.
Within the proper diffusion sheet resistance or thickness range of the P-type emitter, the photoelectric conversion efficiency of the solar cell is improved, and the performance of the solar cell is improved.
Further, in steps S10 and S20, the doping process includes any one of a high temperature diffusion process, a slurry doping process, or an ion implantation process, and forms a doped layer on the surface of the N-type semiconductor substrate. The first N-type doped layer and the P-type emitter are formed by doping the surface layer of the semiconductor substrate, and the thickness of the semiconductor substrate may not be changed.
In step S30, a dielectric layer is formed on the upper surface of the P-type emitter.
In some of these embodiments, the dielectric layer comprises at least one of silicon oxide, aluminum oxide, titanium oxide, gallium oxide, silicon nitride, hafnium oxide.
The embodiment of the present invention does not limit the specific operation manner of forming the dielectric layer. Illustratively, forming the dielectric layer on the upper surface of the P-type emitter includes: and forming a dielectric layer on the upper surface of the P-type emitter by at least one of chemical vapor deposition, high-temperature thermal oxidation, nitric acid oxidation and the like.
When the dielectric layer is formed on the upper surface of the P-type emitter by using the chemical vapor deposition method, the oxidizing gas comprises at least one of oxygen, nitrous oxide gas and ozone. Thereby forming a thinner dielectric layer on the upper surface of the P-type emitter.
Preferably, the dielectric layer is silicon oxide. Understandably, by forming silicon oxide on the upper surface of the P-type emitter, a better passivation effect can be realized, the application of metal oxide is avoided, and the preparation cost of the solar cell is reduced.
In other embodiments, the dielectric layer may be formed by using metal oxide such as aluminum oxide and titanium oxide, but an organic metal source is required in the deposition process, and the organic metal source is flammable and explosive, has a safety hazard, and increases the manufacturing cost of the solar cell, and therefore, the electrolyte layer is preferably silicon oxide.
For example, the dielectric layer may also be a stack of silicon oxide and aluminum oxide, a stack of silicon oxide and silicon nitride, a stack of silicon oxide and hafnium oxide, a multi-layer stack of silicon oxide, aluminum oxide and titanium oxide, and the like, which is not limited herein.
In a specific embodiment, the dielectric layer has a thickness of 0.5nm to 2nm, and may be, for example, 0.5nm, 0.8nm, 1.0nm, 1.2nm, 1.5nm, 1.8nm, or 2.0 nm. The dielectric layer not only passivates the surface of the semiconductor substrate, but also needs to enable carriers to tunnel through, when the thickness of the dielectric layer is too small, the passivation effect cannot be achieved, and when the thickness of the dielectric layer is too large, the carriers cannot effectively penetrate through the dielectric layer. In this embodiment, the dielectric thin film is used to optimize the passivation effect of the front surface of the battery, so that the conversion efficiency of the battery can be significantly improved.
Step S40, forming a second N-type doped layer on the upper surface of the dielectric layer, wherein the crystalline state of the second N-type doped layer includes one or more of an amorphous phase, a microcrystalline phase, or a polycrystalline phase.
The thickness of the second N-type doped layer is 1nm to 10nm, and may be, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 8nm, or 10 nm. The doping element of the second N-type doping layer is phosphorus or arsenic, the doping sheet resistance of the second N-type doping layer is 1000-100000 omega/sqr, such as 1000 omega/sqr, 2000 omega/sqr, 5000 omega/sqr, 10000 omega/sqr, 20000 omega/sqr, 30000 omega/sqr, 50000 omega/sqr, 80000 omega/sqr or 100000 omega/sqr.
In one embodiment, step S40 specifically includes the following steps:
and depositing and forming a polycrystalline silicon layer on the upper surface of the dielectric layer, and carrying out doping treatment to form the N-type doped polycrystalline silicon layer.
The polysilicon layer can be deposited on the upper surface of the dielectric layer by any one of a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method and an atmospheric pressure chemical vapor deposition method.
In another embodiment, step S40 specifically includes the following steps:
depositing and forming an amorphous silicon layer on the surface of the dielectric layer, and carrying out doping treatment to form the N-type doped amorphous silicon layer;
and annealing the N-type doped amorphous silicon layer, wherein the annealed N-type doped amorphous silicon layer is converted into N-type doped mixed phase crystalline silicon, and the mixed phase crystalline silicon comprises at least two of amorphous phase crystalline silicon, microcrystalline phase crystalline silicon or polycrystalline phase crystalline silicon.
In some embodiments, the peak temperature of the annealing process is 500 ℃ to 900 ℃, and may be, for example, 700 ℃, 750 ℃, 800 ℃, 840 ℃, 850 ℃, 860 ℃, 880 ℃, 900 ℃, 950 ℃, 1000 ℃, etc. Preferably, the peak temperature of the annealing treatment is xx ℃ -xx ℃.
The annealing treatment time is 0.5min to 30min, and may be, for example, 0.5min, 1min, 3min, 5min, 8min, 10min, 12min, 15min, 20min, 23min, 25min, 28min or 30 min. Preferably, the time of the annealing treatment is 5min to 10 min.
Alternatively, the protective atmosphere during the annealing process may be an inert gas, such as nitrogen, argon, or the like.
In the annealing temperature and time range, the method is favorable for realizing the doping process of a specified region by one-step high-temperature annealing treatment, and can improve the crystalline silicon structure and the electrical property thereof and improve the conversion efficiency of the solar cell.
Step S50, a front passivation layer is formed on the upper surface of the second N-type doped layer, and a back passivation layer is formed on the lower surface of the first N-type doped layer.
As an alternative solution of the present application, a front passivation layer and a back passivation layer may be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD), but other methods, such as organic chemical vapor deposition, may also be used, and are not limited herein.
The thickness of the front passivation layer and/or the back passivation layer is 60nm to 150nm, and may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 150nm, or the like. Other values within the range are also possible and are not limited herein.
In some embodiments, the front passivation layer and/or the back passivation layer may include, but is not limited to, a single layer or a stacked layer structure of silicon nitride, silicon oxynitride, aluminum oxide, and the like. Of course, other types of passivation layers can be used for the front passivation layer, and the specific material of the front passivation layer is not limited in the present invention.
Preferably, the material of the front passivation layer and/or the back passivation layer includes at least one of a hydrogen-containing silicon nitride layer, a hydrogen-containing silicon oxynitride, a hydrogen-containing silicon oxycarbide, and a hydrogen-containing silicon oxynitride. It will be appreciated that the incorporation of hydrogen atoms into the passivation layer may optimize the passivation effect. In other embodiments, the passivation layer may also be a stack of silicon dioxide and silicon nitride, or the like. The passivation layer can generate a good passivation effect on the semiconductor substrate, and is beneficial to improving the conversion efficiency of the battery.
The passivation structure is reinforced by superposing the front passivation layer, the second N-type doping layer and the dielectric layer, and the second N-type doping layer and the dielectric layer on the upper surface of the P-type emitter form an inversion caused by band bending, so that the passivation effect can be better realized.
Step S60, forming an electrode on the front passivation layer and/or the back passivation layer.
In some embodiments, the back main grid and the back auxiliary grid can be printed on the back surface of the semiconductor substrate by using silver paste, and then dried, and the front main grid and the front auxiliary grid can be printed on the front surface of the semiconductor substrate by using aluminum-doped silver paste, and then dried, and finally sintered, so as to obtain the solar cell.
In one embodiment, step S60 specifically includes:
carrying out metallization treatment on the surface of the front passivation layer to form a front electrode, wherein the front electrode penetrates through the front passivation layer, the second N-type doping layer and the dielectric layer to form electric contact with the P-type emitter;
and carrying out metallization treatment on the surface of the back passivation layer to form a back electrode, wherein the back electrode penetrates through the back passivation layer to form electric contact with the first N-type doping layer.
The embodiment of the present application further provides a solar cell, which may be an N-PERT solar cell, and as shown in fig. 2, the solar cell includes a front electrode 17, a front passivation layer 14, a second N-type doped layer 13, a dielectric layer 12, a P-type emitter 11, a semiconductor substrate 10, a first N-type doped layer 15, a back passivation layer 16, and a back electrode 18, which are sequentially arranged from top to bottom.
Note that the front electrode 17 penetrates through the front passivation layer 14, the second N-type doped layer 13, and the dielectric layer 12 to form an electrical contact with the P-type emitter 11; the back electrode 18 penetrates the back passivation layer 16 to make electrical contact with the first N-doped layer 15.
The doping element of the P-type emitter 11 is boron or gallium, but may be other trivalent elements. The doping sheet resistance of the P-type emitter 11 is 80 Ω/sqr to 400 Ω/sqr, for example, 80 Ω/sqr, 100 Ω/sqr, 150 Ω/sqr, 200 Ω/sqr, 250 Ω/sqr, 300 Ω/sqr, 350 Ω/sqr, 400 Ω/sqr, etc.
The thickness of the P-type emitter 11 is 0.4um to 2.0um, and may be, for example, 0.4um, 0.6um, 0.8um, 1.0um, 1.2um, 1.5um, 1.8um, or 2.0 um; other values within the range are also possible and are not limited herein.
The dielectric layer 12 includes at least one of silicon oxide, aluminum oxide, titanium oxide, gallium oxide, silicon nitride, and hafnium oxide. The thickness of the dielectric layer 12 is 0.5nm to 2nm, and may be, for example, 0.5nm, 0.8nm, 1.0nm, 1.2nm, 1.5nm, 1.8nm or 2.0 nm. The dielectric layer 12 not only passivates the surface of the semiconductor substrate, but also needs to allow carriers to tunnel through, and when the thickness of the dielectric layer is too small, the passivation cannot be performed, and when the thickness of the dielectric layer 12 is too large, the carriers cannot effectively pass through. In this embodiment, the dielectric thin film is used to optimize the passivation effect of the front surface of the battery, so that the conversion efficiency of the battery can be significantly improved.
The thickness of second N-type doped layer 13 is 1nm to 10nm, and may be, for example, 1nm, 2nm, 3nm, 4nm, 5nm, 8nm, or 10 nm. The doping element of the second N-type doped layer 13 is phosphorus or arsenic, and the doping sheet resistance of the second N-type doped layer is 1000 to 100000 Ω/sqr, for example, 1000 Ω/sqr, 2000 Ω/sqr, 5000 Ω/sqr, 10000 Ω/sqr, 20000 Ω/sqr, 30000 Ω/sqr, 50000 Ω/sqr, 80000 Ω/sqr or 100000 Ω/sqr.
The thickness of the first N-type doped layer 15 is 20nm to 300nm, and may be, for example, 20nm, 40nm, 50nm, 80nm, 100nm, 120nm, 150nm, 200nm, 220nm, 250nm, or 300 nm. Other values within the range are also possible and are not limited herein. The doping element of the first N-type doped layer 15 is phosphorus or arsenic, and the doping sheet resistance of the first N-type doped layer 15 is 20 Ω/sqr to 300 Ω/sqr, for example, 20 Ω/sqr, 50 Ω/sqr, 80 Ω/sqr, 100 Ω/sqr, 150 Ω/sqr, 200 Ω/sqr, 250 Ω/sqr, 300 Ω/sqr, etc.
The thickness of the front passivation layer 14 and/or the back passivation layer 16 is 60nm to 150nm, and may be, for example, 60nm, 70nm, 80nm, 90nm, 100nm, 110nm, 120nm, 150nm, or the like. The front passivation layer and/or the back passivation layer are made of at least one of a hydrogen-containing silicon nitride layer, a hydrogen-containing silicon oxynitride, a hydrogen-containing silicon oxycarbide and a hydrogen-containing silicon oxynitride. It will be appreciated that the incorporation of hydrogen atoms into the passivation layer may optimize the passivation effect. In other embodiments, the passivation layer may also be a stack of silicon dioxide and silicon nitride, or the like. The passivation layer can generate a good passivation effect on the semiconductor substrate, and is beneficial to improving the conversion efficiency of the battery.
In the embodiment of the present invention, the specific material of the front electrode 17 and the back electrode 18 is not limited. For example, the front electrode 17 is a silver electrode or a silver/aluminum electrode, and the back electrode 18 is a silver electrode.
For the specific structure of the solar cell, such as the specific type of each layer, reference may be made to the description related to the preparation method of the solar cell, and the detailed description is omitted here.
The embodiment of the present application further provides a solar cell, which may be an N-TopCon solar cell, as shown in fig. 3, the solar cell includes a front electrode 17, a front passivation layer 14, a second N-type doped layer 13, a dielectric layer 12, a P-type emitter 11, a semiconductor substrate 10, a tunneling oxide layer 19, a first N-type doped layer 15, a back passivation layer 16, and a back electrode 18, which are sequentially arranged from top to bottom.
Wherein, the first N-type doped layer 15 and the tunneling oxide layer 19 form a TopCon structure.
Note that the front electrode 17 penetrates through the front passivation layer 14, the second N-type doped layer 13, and the dielectric layer 12 to form an electrical contact with the P-type emitter 11; the back electrode 18 penetrates the back passivation layer 16 to make electrical contact with the first N-doped layer 15.
For the specific structure of the solar cell, such as the specific type of each layer, reference may be made to the description related to the preparation method of the solar cell, and the detailed description is omitted here. The thickness of each layer structure in the solar cell is not limited in the embodiments of the present invention, and can be adjusted and controlled by those skilled in the art according to actual situations.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Although the present application has been described with reference to preferred embodiments, it is not intended to limit the scope of the claims, and many possible variations and modifications may be made by one skilled in the art without departing from the spirit of the application.

Claims (10)

1. A method for manufacturing a solar cell, comprising:
carrying out N-type doping treatment on the back surface of the textured N-type semiconductor substrate to form a first N-type doping layer;
carrying out P-type doping treatment on the front surface of the textured N-type semiconductor substrate to form a P-type emitter, wherein the P-type emitter and the N-type semiconductor substrate form a PN junction;
forming a dielectric layer on the upper surface of the P-type emitter;
forming a second N-type doped layer on the upper surface of the dielectric layer, wherein the crystalline state of the second N-type doped layer comprises one or more of an amorphous phase, a microcrystalline phase or a polycrystalline phase;
forming a front passivation layer on the upper surface of the second N-type doped layer, and forming a back passivation layer on the lower surface of the first N-type doped layer; and
forming an electrode on the front passivation layer and/or the back passivation layer.
2. The method according to claim 1, wherein the dielectric layer has a thickness of 0.5nm to 2 nm; and/or the dielectric layer comprises at least one of silicon oxide, aluminum oxide, titanium oxide, gallium oxide, silicon nitride and hafnium oxide.
3. The method of claim 1 or 2, wherein depositing an N-type doped layer on the top surface of the dielectric layer comprises:
and depositing and forming a polycrystalline silicon layer on the upper surface of the dielectric layer, and carrying out doping treatment to form the N-type doped polycrystalline silicon layer.
4. The method according to claim 1 or 2, wherein depositing an N-type doped layer on the surface of the dielectric layer comprises:
depositing and forming an amorphous silicon layer on the surface of the dielectric layer, and carrying out doping treatment to form the N-type doped amorphous silicon layer;
and annealing the N-type doped amorphous silicon layer, wherein the annealed N-type doped amorphous silicon layer is converted into N-type doped mixed phase crystalline silicon, and the mixed phase crystalline silicon comprises at least two of amorphous phase crystalline silicon, microcrystalline phase crystalline silicon or polycrystalline phase crystalline silicon.
5. The method according to claim 1, wherein the thickness of the first N-type doped layer is 1nm to 10 nm;
the doping element of the first N-type doping layer is phosphorus or arsenic, and the doping sheet resistance of the first N-type doping layer is 20-300 omega/sqr.
6. The method according to claim 1, wherein the doping element of the P-type emitter is boron or gallium, and the doping sheet resistance of the P-type emitter is 80 Ω/sqr to 400 Ω/sqr.
7. The method for manufacturing a solar cell according to claim 1, 5 or 6, wherein the doping treatment is performed by any one of a high temperature diffusion process, a slurry doping process or an ion implantation process.
8. The method according to any one of claims 1 to 7, wherein the thickness of the front passivation layer and/or the back passivation layer is 60nm to 150nm, and the material of the front passivation layer and/or the back passivation layer comprises at least one of silicon nitride containing hydrogen, silicon oxynitride containing hydrogen, silicon oxycarbide containing hydrogen, and silicon oxynitride containing hydrogen.
9. The method of claim 1, wherein forming an electrode on the front passivation layer and/or the back passivation layer comprises:
carrying out metallization treatment on the surface of the front passivation layer to form a front electrode, wherein the front electrode penetrates through the front passivation layer, the second N-type doping layer and the dielectric layer to form electric contact with the P-type emitter;
and carrying out metallization treatment on the surface of the back passivation layer to form a back electrode, wherein the back electrode penetrates through the back passivation layer to form electric contact with the first N-type doping layer.
10. A solar cell obtained by the method according to any one of claims 1 to 9, wherein the solar cell comprises a front electrode, a front passivation layer, a second N-type doped layer, a dielectric layer, a P-type emitter, a semiconductor substrate, a first N-type doped layer, a back passivation layer, and a back electrode, which are sequentially arranged from top to bottom.
CN202011059369.1A 2020-09-30 2020-09-30 Solar cell and preparation method thereof Active CN112201700B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202210519969.4A CN114975683B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof
CN202011059369.1A CN112201700B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011059369.1A CN112201700B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN202210519969.4A Division CN114975683B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof

Publications (2)

Publication Number Publication Date
CN112201700A true CN112201700A (en) 2021-01-08
CN112201700B CN112201700B (en) 2022-06-24

Family

ID=74008543

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202210519969.4A Active CN114975683B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof
CN202011059369.1A Active CN112201700B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202210519969.4A Active CN114975683B (en) 2020-09-30 2020-09-30 Solar cell and preparation method thereof

Country Status (1)

Country Link
CN (2) CN114975683B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113345969A (en) * 2021-04-28 2021-09-03 中国科学院宁波材料技术与工程研究所 Passivated contact structure, preparation method and application thereof
CN113471311A (en) * 2021-07-06 2021-10-01 安徽华晟新能源科技有限公司 Heterojunction battery and preparation method thereof
CN115132851B (en) * 2021-08-26 2023-06-16 上海晶科绿能企业管理有限公司 Solar cell, manufacturing method thereof and photovoltaic module
JP7395041B1 (en) 2022-12-07 2023-12-08 ジョジアン ジンコ ソーラー カンパニー リミテッド Solar cells and photovoltaic modules

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102144303A (en) * 2008-09-03 2011-08-03 弗兰霍菲尔运输应用研究公司 Hetero solar cell and method for producing hetero solar cells
CN102263157A (en) * 2010-05-04 2011-11-30 美国喜瑞能源公司 Solar cell with oxide tunneling junctions
CN107644925A (en) * 2017-09-18 2018-01-30 浙江晶科能源有限公司 A kind of preparation method of P-type crystal silicon solar cell
CN109216491A (en) * 2018-10-10 2019-01-15 泰州隆基乐叶光伏科技有限公司 Solar battery and preparation method thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7468485B1 (en) * 2005-08-11 2008-12-23 Sunpower Corporation Back side contact solar cell with doped polysilicon regions
CN104617167A (en) * 2013-11-01 2015-05-13 国际商业机器公司 Method for forming photovoltaic device, and photovoltaic device
KR101614190B1 (en) * 2013-12-24 2016-04-20 엘지전자 주식회사 Solar cell and manufacturing method thereof
KR101778128B1 (en) * 2016-01-20 2017-09-13 엘지전자 주식회사 Solar cell
CN105742391B (en) * 2016-04-27 2017-03-08 中国科学院宁波材料技术与工程研究所 A kind of tunnelling silica nitrogen layer passivation contact solar cell and preparation method thereof
NL2018356B1 (en) * 2017-02-10 2018-09-21 Tempress Ip B V A method of manufacturing a passivated solar cell and resulting passivated solar cell
CN107946405B (en) * 2017-11-16 2019-10-18 隆基乐叶光伏科技有限公司 A kind of production method being passivated contact solar cell
CN107887478B (en) * 2017-12-15 2019-09-06 浙江晶科能源有限公司 A kind of N-type double-sided solar battery and preparation method thereof
CN109065639A (en) * 2018-06-22 2018-12-21 晶澳（扬州）太阳能科技有限公司 N-type crystalline silicon solar battery and preparation method, photovoltaic module
CN110828583B (en) * 2019-09-24 2021-09-14 苏州腾晖光伏技术有限公司 Crystalline silicon solar cell with locally passivated and contacted front surface and preparation method thereof
CN111180555B (en) * 2020-03-04 2022-05-27 泰州中来光电科技有限公司 Preparation method of passivated contact battery based on PERC
CN111509072A (en) * 2020-03-20 2020-08-07 中国科学院宁波材料技术与工程研究所 Novel silicon solar cell with n-type back junction design and preparation method thereof
CN111599895A (en) * 2020-06-03 2020-08-28 通威太阳能(眉山)有限公司 Preparation method of crystalline silicon solar passivated contact cell

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102144303A (en) * 2008-09-03 2011-08-03 弗兰霍菲尔运输应用研究公司 Hetero solar cell and method for producing hetero solar cells
CN102263157A (en) * 2010-05-04 2011-11-30 美国喜瑞能源公司 Solar cell with oxide tunneling junctions
CN107644925A (en) * 2017-09-18 2018-01-30 浙江晶科能源有限公司 A kind of preparation method of P-type crystal silicon solar cell
CN109216491A (en) * 2018-10-10 2019-01-15 泰州隆基乐叶光伏科技有限公司 Solar battery and preparation method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113345969A (en) * 2021-04-28 2021-09-03 中国科学院宁波材料技术与工程研究所 Passivated contact structure, preparation method and application thereof
CN113345969B (en) * 2021-04-28 2024-05-14 中科研和(宁波)科技有限公司 Passivation contact structure and preparation method and application thereof
CN113471311A (en) * 2021-07-06 2021-10-01 安徽华晟新能源科技有限公司 Heterojunction battery and preparation method thereof
CN113471311B (en) * 2021-07-06 2023-05-23 安徽华晟新能源科技有限公司 Heterojunction battery and preparation method thereof
CN115132851B (en) * 2021-08-26 2023-06-16 上海晶科绿能企业管理有限公司 Solar cell, manufacturing method thereof and photovoltaic module
JP7395041B1 (en) 2022-12-07 2023-12-08 ジョジアン ジンコ ソーラー カンパニー リミテッド Solar cells and photovoltaic modules

Also Published As

Publication number Publication date
CN112201700B (en) 2022-06-24
CN114975683A (en) 2022-08-30
CN114975683B (en) 2023-06-06

Similar Documents

Publication Publication Date Title
CN112201700B (en) Solar cell and preparation method thereof
US11264529B1 (en) Solar cell and method for manufacturing the same
US7838400B2 (en) Rapid thermal oxide passivated solar cell with improved junction
CN110838536A (en) Back contact solar cell with various tunnel junction structures and preparation method thereof
CN110289333B (en) Solar cell, production method and photovoltaic module
CN114038928B (en) Solar cell, preparation method thereof and photovoltaic module
CN111755552A (en) Solar cell and manufacturing method thereof
CN111933752A (en) Solar cell and preparation method thereof
JP7461573B2 (en) Solar cell and its manufacturing method, photovoltaic module
WO2024087838A1 (en) Solar cell, and manufacturing method therefor
CN115188837A (en) Back contact solar cell, preparation method and cell module
CN113506832A (en) Passivated contact structure, preparation method thereof and solar cell using passivated contact structure
CN114005888A (en) Solar cell and preparation method thereof
CN113421949B (en) Solar cell, preparation method thereof and photovoltaic module
WO2022156101A1 (en) Solar cell stack passivation structure and preparation method therefor
CN117238998A (en) N-type TOPCON battery and novel back structure preparation method
KR20160061409A (en) Method for producing a solar cell
CN113875025A (en) Solar cell and method for manufacturing solar cell
WO2022156102A1 (en) Solar cell stack passivation structure and preparation method therefor
CN112786738B (en) Solar cell and preparation method thereof
CN113871493A (en) Aluminum-doped titanium oxide film based on atomic layer deposition technology and preparation method thereof
JP6647425B2 (en) Solar cell manufacturing method
CN117497626B (en) Solar cell and method for manufacturing solar cell
CN116110978B (en) Solar cell, preparation method thereof and photovoltaic module
CN114093980B (en) Manufacturing method of interdigital back contact battery

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: 314416 west of lumansi bridge, Yuanxi Road, Yuanhua Town, Haining City, Jiaxing City, Zhejiang Province

Applicant after: ZHEJIANG JINKO SOLAR Co.,Ltd.

Applicant after: Jingke Energy Co.,Ltd.

Address before: 314416 west of lumansi bridge, Yuanxi Road, Yuanhua Town, Haining City, Jiaxing City, Zhejiang Province

Applicant before: ZHEJIANG JINKO SOLAR Co.,Ltd.

Applicant before: JINKO SOLAR Co.,Ltd.

GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20221026

Address after: No. 1, northeast corner of the intersection of Longxing Avenue and Ruquan Road, Hefei Circular Economy Demonstration Park, Feidong County, Hefei City, Anhui Province, 231600

Patentee after: Anhui Jinko Energy Co.,Ltd.

Address before: 314416 west of lumansi bridge, Yuanxi Road, Yuanhua Town, Haining City, Jiaxing City, Zhejiang Province

Patentee before: ZHEJIANG JINKO SOLAR Co.,Ltd.

Patentee before: Jingke Energy Co.,Ltd.