CN112165324A - Low-jitter ultra-narrow pulse width local oscillator signal generating device and method of sampler - Google Patents

Low-jitter ultra-narrow pulse width local oscillator signal generating device and method of sampler Download PDF

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Publication number
CN112165324A
CN112165324A CN202011094690.3A CN202011094690A CN112165324A CN 112165324 A CN112165324 A CN 112165324A CN 202011094690 A CN202011094690 A CN 202011094690A CN 112165324 A CN112165324 A CN 112165324A
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China
Prior art keywords
jitter
low
module
triode
ultra
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CN202011094690.3A
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Chinese (zh)
Inventor
张敏娟
刘震
王志斌
姚鑫凯
苗婉茹
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North University of China
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North University of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Abstract

The invention belongs to the technical field of local oscillator signal generation, and particularly relates to a low-jitter ultra-narrow pulse width local oscillator signal generation device and method of a sampler. The invention utilizes the low-jitter clock generating circuit to obtain a low-jitter clock signal, obtains an ultra-narrow pulse signal through the power division amplifying circuit, and drives the 50GHz sampler to work. The invention is used for generating local oscillation signals.

Description

Low-jitter ultra-narrow pulse width local oscillator signal generating device and method of sampler
Technical Field
The invention belongs to the technical field of local oscillator signal generation, and particularly relates to a low-jitter ultra-narrow pulse width local oscillator signal generation device and method of a sampler.
Background
In a communication system, a local oscillator signal has a basic function of frequency conversion, and is one of essential key links in the communication system. The local oscillation signal is generated by the local oscillation circuit, and the phase-locked loop circuit is added in the local oscillation circuit, so that the extremely high stability is ensured. The stability of the local oscillator frequency is very important, otherwise, the local oscillator frequency drift can be generated, and the result that the television cannot be viewed is caused. The phase-locked loop circuit is a feedback control circuit for eliminating frequency error, and is called phase-locked loop for short, and its controlled quantity is phase, and its controlled object is voltage-controlled oscillator. The phase-locked loop is characterized in that the frequency and the phase of an internal oscillation signal of the loop are controlled by using an externally input reference signal, so that the automatic tracking of the frequency of an output signal to the frequency of an input signal is realized, and the phase-locked loop is usually used for a closed-loop tracking circuit. Phase-locked loop technology has wide application in signal processing and digital systems, such as frequency modulation, frequency locking, clock synchronization, frequency synthesis, and the like. In general, a phase-locked loop consists of three basic units: a phase detector, a loop filter and a voltage controlled oscillator. The phase discriminator is a phase comparator, and the reference frequency and the sampling frequency output by the voltage-controlled oscillator are subjected to phase comparison in the phase discriminator to output error voltage; the loop filter filters the error voltage output by the phase discriminator, and filters interference and high-frequency components in current so as to ensure the performance required by the loop and improve the stability of the system; and the voltage-controlled oscillator is controlled by the direct-current voltage output by the loop filter, the direct-current voltage pulls the output frequency of the voltage-controlled oscillator to the reference frequency input by the loop, and when the frequencies of the voltage-controlled oscillator and the reference frequency are equal and the phase difference is constant, the loop is locked. At present, most of common local oscillator signal generators adopt a structure of combining a phase-locked loop chip, a loop filter and a voltage-controlled oscillator, each part of the phase-locked loop chip, the loop filter, the voltage-controlled oscillator and the like needs to be independently powered, the volume occupied by a printed circuit board is large, and the corresponding debugging process and the debugging steps are relatively complex.
Disclosure of Invention
Aiming at the technical problems that the existing local oscillator signal generating device is large in size and the debugging process and the debugging steps are complex, the invention provides the local oscillator signal generating device and the local oscillator signal generating method for the sampler, which are strong in performance, high in reliability and large in output frequency range, and have the advantages of low jitter and ultra-narrow pulse width.
In order to solve the technical problems, the invention adopts the technical scheme that:
the utility model provides a low jitter ultra-narrow pulse width local oscillator signal generating device of sampler, includes low jitter clock generation module, high-speed low jitter frequency divider module, FPGA module, time base amplification module, the output of low jitter clock generation module is connected with the input of high-speed low jitter frequency divider module, the control communication module of FPGA module is connected with the communication interface of low jitter clock generation module, high-speed low jitter frequency divider module respectively, high-speed low jitter frequency divider module is connected with time base amplification module.
The low-jitter clock generation module comprises a program-controlled reference source module and a clock generation module, and the program-controlled reference source module is connected with the clock generation module.
The chip of the low-jitter clock generation module adopts HMC1035, the frequency range of a clock signal generated by the low-jitter clock generation module is 25MHz-2500MHz, and the jitter index of the clock signal generated by the jitter clock generation module is less than 97 fsRMS.
The high-speed low-jitter frequency divider module is formed by cascading high-speed low-jitter chips HMC988, the jitter index of the high-speed low-jitter frequency divider module is smaller than 70fsRMS, and the frequency division range of the high-speed low-jitter frequency divider module is 1-1024.
The time base amplification module is including the input, first triode, second triode, third triode, first electric capacity, second electric capacity, the inductance of amplifying the module, the input of amplifying the module is connected on the base of first triode, the collecting electrode ground connection of first triode, the projecting pole of first triode is connected on the base of second triode, the collecting electrode ground connection of second triode, the projecting pole of second triode is connected on the base of third triode through first electric capacity, the projecting pole ground connection of third triode, the collecting electrode of third triode passes through the second electric capacity and connects on the inductance, be equipped with the output of super narrow pulse width between second electric capacity and the inductance.
The emitting electrode of the first triode is connected with-5V voltage, the emitting electrode of the second triode is connected with-15V voltage, and the collecting electrode of the third triode is connected with 15V voltage.
A low-jitter ultra-narrow pulse width local oscillation signal generation method of a sampler comprises the following steps:
s1, determining parameters of jitter and precision time base;
s2, after the low-jitter clock generating module is controlled by the FPGA module to generate a low-jitter clock signal, the low-jitter clock signal is generated by integer frequency division of the high-speed low-jitter frequency divider module;
and S3, after the low-jitter time-base signal passes through the time-base amplification module, amplifying the low-jitter time-base signal and performing pulse narrowing processing to generate a low-jitter ultra-narrow pulse width local oscillator signal.
The jitter and the precise time base in S1 have the following parameters: the frequency of a clock signal generated by the low-jitter clock generation module, the frequency division multiple of the high-speed low-jitter frequency divider module, the falling edge of a low-jitter ultra-narrow pulse width local oscillator signal of the time base amplification module, and the jitter index of the clock signal generated by the low-jitter clock generation module.
Compared with the prior art, the invention has the following beneficial effects:
the invention utilizes the low-jitter clock generating circuit to obtain a low-jitter clock signal, obtains an ultra-narrow pulse signal through the power division amplifying circuit, and drives the 50GHz sampler to work.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a schematic circuit diagram of a low jitter clock generation module according to the present invention;
FIG. 3 is a schematic circuit diagram of a high speed low jitter frequency divider module according to the present invention;
fig. 4 is a schematic circuit diagram of the time base amplification module of the present invention.
Wherein: u1 is a low-jitter clock generation module, U2 is a high-speed low-jitter frequency divider module, U3 is an FPGA module, U4 is a time base amplification module, 1 is a program control reference source module, 2 is a clock generation module, IN is an input end of the amplification module, T1 is a first triode, T2 is a second triode, T3 is a third triode, C1 is a second capacitor, C2 is a second capacitor, and L1 is an inductor.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A low-jitter ultra-narrow pulse width local oscillation signal generating device of a sampler comprises a low-jitter clock generating module U1, a high-speed low-jitter frequency divider module U2, an FPGA module U3 and a time base amplifying module U4, wherein the output end of the low-jitter clock generating module U1 is connected with the input end of a high-speed low-jitter frequency divider module U2, a control communication module of the FPGA module U3 is respectively connected with communication interfaces of the low-jitter clock generating module U1 and the high-speed low-jitter frequency divider module U2, and a high-speed low-jitter frequency divider module U2 is connected with the time base amplifying module U4, as shown in figure 1.
Further, as shown in fig. 2, the low-jitter clock generation module U1 includes a programmable reference source module 1 and a clock generation module 2, where the programmable reference source module 1 is connected to the clock generation module 2, and the clock generation module 2 synthesizes a required broadband clock by using a variable reference source.
Further, preferably, the chip of the low jitter clock generation module U1 employs an HMC1035, and the HMC1035 provides industry-advanced phase noise and jitter performance over the entire operating range, which improves link-level jitter performance, Bit Error Rate (BER) and eye diagram index. The frequency range of the clock signal generated by the low-jitter clock generation module U1 is 25MHz-2500MHz, and the jitter index of the clock signal generated by the jitter clock generation module U1 is less than 97 fsRMS.
Further, as shown in fig. 3, preferably, the high-speed low-jitter frequency divider module U2 is cascaded by using high-speed low-jitter chips HMC988, the jitter index of the high-speed low-jitter frequency divider module U2 is less than 70fsRMS, and the frequency division range of the high-speed low-jitter frequency divider module U2 is 1-1024.
Further, as shown IN fig. 4, the time-base amplification module U4 includes an input terminal IN of the amplification module, a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, and an inductor L1, where the input terminal IN of the amplification module is connected to the base of the first transistor T1, the collector of the first transistor T1 is grounded, the emitter of the first transistor T1 is connected to the base of the second transistor T2, the collector of the second transistor T2 is grounded, the emitter of the second transistor T2 is connected to the base of the third transistor T3 through the first capacitor C1, the emitter of the third transistor T3 is grounded, the collector of the third transistor T3 is connected to the inductor L1 through the second capacitor C2, and an output terminal with a very narrow pulse width is disposed between the second capacitor C2 and the inductor L1. The time base amplification module U4 is mainly composed of a triode, the conduction and turn-off time of the triode is short, the circuit which influences the front and back edges of the pulse is mainly a driving circuit, the output capacitor of the triode and the input capacitor of the lower stage, through tests, the time base amplification module U4 can enable the falling edge of the low-jitter time base signal pulse to reach within 100ps, and can drive a sampler to work.
Further, an emitter of the first triode T1 is connected with-5V voltage, an emitter of the second triode T2 is connected with-15V voltage, and a collector of the third triode T3 is connected with 15V voltage.
A low-jitter ultra-narrow pulse width local oscillation signal generation method of a sampler comprises the following steps:
determining parameters of jitter and a precision time base, wherein the parameters of jitter and the precision time base are as follows: the frequency of a clock signal generated by the low-jitter clock generation module, the frequency division multiple of the high-speed low-jitter frequency divider module, the falling edge of a low-jitter ultra-narrow pulse width local oscillator signal of the time base amplification module, and the jitter index of the clock signal generated by the low-jitter clock generation module.
Step two, after the low-jitter clock generating module is controlled by the FPGA module to generate a low-jitter clock signal, the low-jitter clock signal is generated by integer frequency division of the high-speed low-jitter frequency divider module;
and step three, after the low-jitter time-base signal passes through the time-base amplification module, amplifying the low-jitter time-base signal and performing pulse narrowing processing to generate a low-jitter ultra-narrow pulse width local oscillator signal.
Although only the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art, and all changes are encompassed in the scope of the present invention.

Claims (8)

1. The utility model provides a low jitter super narrow pulse width local oscillator signal generating device of sampler which characterized in that: the high-speed low-jitter frequency divider comprises a low-jitter clock generation module (U1), a high-speed low-jitter frequency divider module (U2), an FPGA module (U3) and a time-base amplification module (U4), wherein the output end of the low-jitter clock generation module (U1) is connected with the input end of the high-speed low-jitter frequency divider module (U2), a control communication module of the FPGA module (U3) is connected with communication interfaces of the low-jitter clock generation module (U1) and the high-speed low-jitter frequency divider module (U2), and the high-speed low-jitter frequency divider module (U2) is connected with the time-base amplification module (U4).
2. The low-jitter ultra-narrow pulse width local oscillator signal generating device of the sampler according to claim 1, wherein: the low-jitter clock generation module (U1) comprises a program-controlled reference source module (1) and a clock generation module (2), wherein the program-controlled reference source module (1) is connected with the clock generation module (2).
3. The low-jitter ultra-narrow pulse width local oscillator signal generating device of the sampler according to claim 1, wherein: the chip of the low-jitter clock generation module (U1) adopts HMC1035, the frequency range of a clock signal generated by the low-jitter clock generation module (U1) is 25MHz-2500MHz, and the jitter index of the clock signal generated by the jitter clock generation module (U1) is less than 97 fsRMS.
4. The low-jitter ultra-narrow pulse width local oscillator signal generating device of the sampler according to claim 1, wherein: the high-speed low-jitter frequency divider module (U2) is cascaded by adopting a high-speed low-jitter chip HMC988, the jitter index of the high-speed low-jitter frequency divider module (U2) is less than 70fsRMS, and the frequency division range of the high-speed low-jitter frequency divider module (U2) is 1-1024.
5. The low-jitter ultra-narrow pulse width local oscillator signal generating device of the sampler according to claim 1, wherein: the time base amplification module (U4) comprises an input end (IN) of the amplification module, a first triode (T1), a second triode (T2), a third triode (T3), a first capacitor (C1), a second capacitor (C2) and an inductor (L1), the input end (IN) of the amplifying module is connected to the base electrode of a first triode (T1), the collector of the first triode (T1) is grounded, the emitter of the first triode (T1) is connected with the base of the second triode (T2), the collector of the second triode (T2) is grounded, the emitter of the second triode (T2) is connected to the base of the third triode (T3) through a first capacitor (C1), the emitter of the third triode (T3) is grounded, the collector of the third triode (T3) is connected to the inductor (L1) through the second capacitor (C2), an output end with ultra-narrow pulse width is arranged between the second capacitor (C2) and the inductor (L1).
6. The low-jitter ultra-narrow pulse width local oscillator signal generating device of claim 5, wherein: the emitter of the first triode (T1) is connected with-5V voltage, the emitter of the second triode (T2) is connected with-15V voltage, and the collector of the third triode (T3) is connected with 15V voltage.
7. A low-jitter ultra-narrow pulse width local oscillation signal generation method of a sampler is characterized by comprising the following steps: comprises the following steps:
s1, determining parameters of jitter and precision time base;
s2, after the low-jitter clock generating module is controlled by the FPGA module to generate a low-jitter clock signal, the low-jitter clock signal is generated by integer frequency division of the high-speed low-jitter frequency divider module;
and S3, after the low-jitter time-base signal passes through the time-base amplification module, amplifying the low-jitter time-base signal and performing pulse narrowing processing to generate a low-jitter ultra-narrow pulse width local oscillator signal.
8. The method according to claim 7, wherein the local oscillator signal generating method comprises: the jitter and the precise time base in S1 have the following parameters: the frequency of a clock signal generated by the low-jitter clock generation module, the frequency division multiple of the high-speed low-jitter frequency divider module, the falling edge of a low-jitter ultra-narrow pulse width local oscillator signal of the time base amplification module, and the jitter index of the clock signal generated by the low-jitter clock generation module.
CN202011094690.3A 2020-10-14 2020-10-14 Low-jitter ultra-narrow pulse width local oscillator signal generating device and method of sampler Pending CN112165324A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113098452A (en) * 2021-03-30 2021-07-09 中北大学 Ultra-narrow pulse compression device based on triode and step recovery diode

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113098452A (en) * 2021-03-30 2021-07-09 中北大学 Ultra-narrow pulse compression device based on triode and step recovery diode
CN113098452B (en) * 2021-03-30 2023-03-07 中北大学 Ultra-narrow pulse compression device based on triode and step recovery diode

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