CN205792524U - Radar clock multiplier based on step-recovery diode - Google Patents
Radar clock multiplier based on step-recovery diode Download PDFInfo
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- CN205792524U CN205792524U CN201620500049.8U CN201620500049U CN205792524U CN 205792524 U CN205792524 U CN 205792524U CN 201620500049 U CN201620500049 U CN 201620500049U CN 205792524 U CN205792524 U CN 205792524U
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Abstract
The utility model discloses a kind of radar clock multiplier based on step-recovery diode, including biasing circuit, step pipe pulse generator, amplifying circuit and bandwidth-limited circuit, the signal input part of described biasing circuit is as the signal input part of whole radar clock multiplier, the signal output part of described biasing circuit is connected with the signal input part of described step pipe pulse generator, the described signal output part of step pipe pulse generator is connected with the signal input part of described amplifying circuit, the signal output part of described amplifying circuit is connected with the signal input part of described bandwidth-limited circuit, the signal output part of described bandwidth-limited circuit is as the signal output part of whole radar clock multiplier.This utility model improves clock signal quality, improves Radar Digital Receiver signal processing performance, reduces hardware cost, enhances system stability and interference free performance, reduces system debug difficulty.
Description
Technical field
This utility model digital radar receives system regions, is specifically related to a kind of based on step-recovery diode
Radar clock multiplier.
Background technology
In recent decades, China is military, commerical radar is all able to high speed development, and substantial amounts of advanced radar also obtains
With large scale deployment.
Along with the arrival of digital times, Radar Digital Receiver instead of the analogue signal that technology is old
Processing system, Radar Digital Receiver is mainly by high speed digital sample, digital demodulation, smothing filtering, pulse
Several parts compositions such as compression.Relative to analog receiver, Radar Digital Receiver has that integrated level is high, is prone to debugging,
The advantages such as anti-interference is good, but digital receiver all working and performance thereof all rely on digital system clocks and
Its quality.It is defeated to target acquisition that the quality of radar clock signal, stability, reliability will have a strong impact on radar
Go out quality and the stability of whole radar system work of product.Due to limits such as the signal frequency of radar, bandwidth
System, typically requires clock frequency higher to meet higher sample rate.In existing most of radars, one
As take crystal oscillator export lower frequency clock, then by doubler frequency multiplication export high frequency clock signal.
The clock signal output scheme one of existing radar system:
Using the output of phaselocked loop phase locking frequency multiplying, its primary structure block diagram is as shown in Figure 1.
Frequency multiplication of phase locked loop method is one of current radar system clock multiplier most common method, and phaselocked loop is one
The tracking system of closed loop, its primary structure (is again mirror by voltage controlled oscillator (being called for short VCO), phase comparator
Phase device, is called for short PD), low-pass loop filter (be called for short LF) and frequency divider form；
In phaselocked loop, phase comparator benchmark signal Ui(t) and output signal UoBetween the Fractional-N frequency of (t)
Phase deviation Φe(t), and thus produce error signal Ud(t), UdT () is through the smooth filter of low-pass loop filter
Ripple, to improve stability and the tracking performance of loop, after filtering radio-frequency component, output controls voltage Uc(t), VCO
For voltage-controlled oscillator, producing local oscillating frequency, its frequency can be according to UcT the control of () produces corresponding
Skew, thus reach to follow the tracks of reference frequency N frequency multiplication U of output reference frequencyoThe function of (t).
Scheme one also exists following defect:
1) system complex, is difficult to debugging；
2) poor stability, easily receives external environment impact；
3) cost is high；
4) phase of output signal noise is big.
The clock signal output scheme two of existing radar system:
Using multiplier frequency multiplication method, in existing clock multiplier method, multiplier frequency multiplication is also relatively common
, its primary structure block diagram is as shown in Figure 2.
In the middle of the program, by crystal oscillator produce reference frequency Fr, and its merit is divided two-way obtain Fr1 and
Being respectively fed to two inputs of multiplier after Fr2, multiplier output will obtain Fr1+Fr2's and Fr1-Fr2
Two sideband signals, obtain multiplier output signal relatively after a high pass filter filters lower sideband signal
For pure Fr1+Fr2 signal, due to Fr1=Fr2, so on the basis of high pass filter output signal frequency is
The twice of frequency.Thus, the cascade of multistage multiplier just can get the arbitrary integer overtones band of reference frequency, takes advantage of
Musical instruments used in a Buddhist or Taoist mass cascade structure is as shown in Figure 3.
Scheme two also exists following defect:
1) system complex, signal quality deteriorates,
2) cost is high；
3) application flexibility is poor.
Utility model content
The purpose of this utility model is that providing a kind of recovers two poles in order to solve the problems referred to above based on step
The radar clock multiplier of pipe.
This utility model is achieved through the following technical solutions above-mentioned purpose:
A kind of radar clock multiplier based on step-recovery diode, including biasing circuit, step pipe pulse
Generator, amplifying circuit and bandwidth-limited circuit, the signal input part of described biasing circuit is as whole radar
The signal input part of clock multiplier, the signal output part of described biasing circuit and described step pipe pulse generation
The signal input part of device connects, the signal output part of described step pipe pulse generator and described amplifying circuit
Signal input part connects, and the signal output part of described amplifying circuit inputs with the signal of described bandwidth-limited circuit
End connects, and the signal output part of described bandwidth-limited circuit exports as the signal of whole radar clock multiplier
End.
Specifically, described biasing circuit includes capacitance and the first high frequency choke coil, described capacitance
One end is as the signal input part of described biasing circuit, the other end of described capacitance and described first high frequency
One end connection of choke coil the signal output part as described biasing circuit, described first high frequency choke coil
Other end ground connection.
Specifically, described step pipe pulse generator includes step-recovery diode, excitation inductance and tuning electricity
Holding, one end of described excitation inductance is connected with one end of described tuning capacity and sends out as described step pipe pulse
The signal input part of raw device, the described other end of excitation inductance is connected with the positive pole of step-recovery diode and makees
For the signal output part of described step pipe pulse generator, the negative pole of described step-recovery diode and described tune
The other end of humorous electric capacity connects and ground connection.
Specifically, described amplifying circuit includes that amplifier, biasing resistor, the second high frequency choke coil and power supply move back
Coupling electric capacity, coupling output capacitance, the model of described amplifier is PSA4-5043+, the 3rd of described amplifier
Pin all connects as the signal input part of described amplifying circuit, the second pin and the 4th pin of described amplifier
Ground, the first pin of described amplifier simultaneously with one end of described second high frequency choke coil and described couple output
One end of electric capacity connects, the other end of described coupling output capacitance as the signal output part of described amplifying circuit,
The other end of described second high frequency choke coil is connected with one end of described biasing resistor, described biasing resistor another
Power supply, the other end of described power supply decoupling capacitance are accessed after being connected with one end of described power supply decoupling capacitance in one end
Ground connection.
Specifically, described bandwidth-limited circuit is formed by the cascade of two-stage 5 rank LC resonance band filter.
The beneficial effects of the utility model are:
This utility model improves clock signal quality, improves Radar Digital Receiver signal processing performance,
Reduce hardware cost, enhance system stability and interference free performance, reduce system debug difficulty.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of Phase Locked Loop Frequency Doubler in prior art；
Fig. 2 is the structured flowchart of multiplier doubler in prior art；
Fig. 3 is the theory diagram of multistage multiplier cascade；
Fig. 4 is the structured flowchart of radar clock multiplier based on step-recovery diode described in the utility model；
Fig. 5 is the circuit theory diagrams of biasing circuit described in the utility model；
Fig. 6 is the circuit theory diagrams of step pipe pulse generator described in the utility model；
Fig. 7 is the circuit theory diagrams of amplifying circuit described in the utility model.
Detailed description of the invention
The utility model is described in further detail below in conjunction with the accompanying drawings:
As shown in Figure 4, this utility model include biasing circuit, step pipe pulse generator, amplifying circuit and
Bandwidth-limited circuit, the signal input part of biasing circuit as the signal input part of whole radar clock multiplier,
The signal output part of biasing circuit is connected with the signal input part of step pipe pulse generator, and step pipe pulse is sent out
The signal output part of raw device is connected with the signal input part of amplifying circuit, the signal output part of amplifying circuit and band
The signal input part of bandpass filter circuit connects, and the signal output part of bandwidth-limited circuit is as whole radar clock
The signal output part of doubler.
Biasing circuit provides suitable bias voltage for step pipe pulse generator, and 48MHz reference signal is passed through
After biasing circuit, enter step pipe pulse generator, utilize step in step pipe pulse generator to recover two poles
The strong nonlinearity characteristic of pipe SRD produces abundant higher hamonic wave, selects through amplifying circuit and bandwidth-limited circuit
Go out required harmonic frequency.
As it is shown in figure 5, biasing circuit includes capacitance C1 and the first high frequency choke coil L1, capacitance
One end of C1 is as the signal input part of biasing circuit, the other end of capacitance C1 and the first high frequency choke
One end connection of circle L1 the signal output part as biasing circuit, the other end of the first high frequency choke coil L1
Ground connection.
Enrich owing to step-recovery diode SRD utilizes the rapid mutation of the reverse recovery current after pinch off to produce
Harmonic wave, it is therefore desirable to biasing networks is that diode provides a suitable bias, in order to SRD is just negative
The moment generation current step that electric current is maximum, to obtain the current step value of maximum.
The design uses self-supporting zero-bias voltage, and the first high frequency choke coil L1 can prevent radio-frequency component to be diverted to ground
Network, capacitance C1 is for blocking the DC channel of reference frequency source and biasing networks.
As shown in Figure 6, step pipe pulse generator includes step-recovery diode SRD, excitation inductance L2
With tuning capacity C2, one end of excitation inductance L2 is connected with one end of tuning capacity C2 and as step pipe arteries and veins
Rush the signal input part of generator, the other end of excitation inductance L2 and the positive pole of step-recovery diode SRD
Connection the signal output part as step pipe pulse generator, the negative pole of step-recovery diode SRD and tune
The other end of humorous electric capacity C2 connects and ground connection.
Excitation inductance L2 is used for storing and releasing energy, and tuning capacity C2 makes excitation inductance L2 at input frequency
Off resonance in rate, and other harmonic wave beyond output frequency is constituted bypass.Step-recovery diode SRD is at PN
There is at junction boundary precipitous impurity profile region, thus form " self-service electric field ".Owing to PN junction is in forward bias
Pressure, with minority carrier electronic conduction, and has charge storage effect near PN junction so that it is reverse current needs
Minima just can be down to after experiencing one " waiting time "." the self-service electricity of step-recovery diode SRD
" shorten waiting time, make reverse current quickly end.When diode in the conduction state adds suddenly
During backward voltage, moment reverse current reaches maximum immediately, and maintains regular hour ts, and immediately
Return to zero.Step-recovery diode SRD presents Low ESR conducting state under forward voltage bias, instead
Under voltage bias, diode impedance is the highest, and little with bias variations.If to step-recovery diode
SRD applies sine-wave excitation because this diode turn-off time is extremely short, can to the hurried pinch off of output waveform,
Therefore it is equivalent to a pulse generator, it is possible to produce the burst pulse containing abundant harmonic components.
As it is shown in fig. 7, amplifying circuit include amplifier U, biasing resistor R, the second high frequency choke coil L3 and
Power supply decoupling capacitance C4, coupling output capacitance C3, the model of amplifier U is PSA4-5043+, amplifier
The three-prong of U is as the signal input part of amplifying circuit, and the second pin and the 4th pin of amplifier U are equal
Ground connection, first pin of amplifier U simultaneously with one end of the second high frequency choke coil L3 and couple output capacitance
One end of C3 connects, the other end of coupling output capacitance C3 as the signal output part of amplifying circuit, second
The other end of high frequency choke coil L3 is connected with one end of biasing resistor R, the other end of biasing resistor R and electricity
Power supply, the other end ground connection of power supply decoupling capacitance C4 are accessed after connecting in one end of source decoupling capacitance C4.
Owing to pulse generator output harmonic wave signal is abundanter, therefore output signal energy comparison dispersion, for
Meet the digital receiver power requirement to clock signal, need the amplifying circuit harmonic signal is carried out merit
Rate is amplified.The design amplifying circuit uses the PSA4-5043+ low noise amplification core that mini circuit company produces
Sheet, this chip 50 Ω impedance, operating frequency range 50MHz～4GHz, maximum input 23dBm is less than 5
Minute, maximum lasting input power 17dBm, 3.3V powers, 500MHz maximum gain 21.2dBm, makes an uproar
Sonic system number maximum 0.66.
Biasing resistor R provides DC bias current for amplifier U, and the second high frequency choke coil L3 can prevent partially
Put the resistance R shunting action to harmonic signal.Power supply decoupling capacitance C4 is used for power conditioner.Second high frequency is gripped
Stream circle L3, biasing resistor R, power supply decoupling capacitance C4 installation site should be close proximity to the 1 of amplifier U
Foot (output pin).The high frequency harmonic signals coupling output after amplifying of coupling output capacitance C3.
Bandwidth-limited circuit is formed by the cascade of two-stage 5 rank LC resonance band filter.
This utility model radar based on step-recovery diode SRD clock multiplier, reduces cost, carries
High Radar Digital Receiver signal processing performance, input reference frequency 48MHz, frequency is 5 times, defeated
Go out 240MHz, this doubler output clock signal excellent performance, meet digital receiver and the performance of clock is wanted
Ask.
These are only preferred embodiment of the present utility model, not in order to limit this utility model, all
Any amendment, equivalent and the improvement etc. made within spirit of the present utility model and principle, all should comprise
In protection domain of the present utility model.
Claims (5)
1. a radar clock multiplier based on step-recovery diode, it is characterised in that: include biased electrical
Road, step pipe pulse generator, amplifying circuit and bandwidth-limited circuit, the signal input of described biasing circuit
Holding the signal input part as whole radar clock multiplier, the signal output part of described biasing circuit is with described
The signal input part of step pipe pulse generator connects, the signal output part of described step pipe pulse generator with
The signal input part of described amplifying circuit connects, the signal output part of described amplifying circuit and described bandpass filtering
The signal input part of circuit connects, and the signal output part of described bandwidth-limited circuit is as whole radar clock times
Frequently the signal output part of device.
Radar clock multiplier based on step-recovery diode the most according to claim 1, its feature
Being: described biasing circuit includes capacitance and the first high frequency choke coil, one end of described capacitance is made
For the signal input part of described biasing circuit, the other end of described capacitance and described first high frequency choke coil
One end connect and as the signal output part of described biasing circuit, the other end of described first high frequency choke coil
Ground connection.
Radar clock multiplier based on step-recovery diode the most according to claim 1, its feature
It is: described step pipe pulse generator includes step-recovery diode, excitation inductance and tuning capacity, institute
The one end stating excitation inductance is connected with one end of described tuning capacity and as described step pipe pulse generator
Signal input part, the described other end of excitation inductance is connected with the positive pole of step-recovery diode and as described
The signal output part of step pipe pulse generator, the negative pole of described step-recovery diode and described tuning capacity
The other end connect and ground connection.
Radar clock multiplier based on step-recovery diode the most according to claim 1, its feature
Be: described amplifying circuit include amplifier, biasing resistor, the second high frequency choke coil and power supply decoupling capacitance,
Coupling output capacitance, the model of described amplifier is PSA4-5043+, the three-prong conduct of described amplifier
The signal input part of described amplifying circuit, the second pin of described amplifier and the 4th equal ground connection of pin are described
First pin of amplifier simultaneously with one end of described second high frequency choke coil and described couple the one of output capacitance
End connects, the other end of described coupling output capacitance as the signal output part of described amplifying circuit, described the
The other end of two high frequency choke coils is connected with one end of described biasing resistor, the other end of described biasing resistor with
Power supply, the other end ground connection of described power supply decoupling capacitance are accessed after connecting in one end of described power supply decoupling capacitance.
Radar clock multiplier based on step-recovery diode the most according to claim 1, its feature
It is: described bandwidth-limited circuit is formed by the cascade of two-stage 5 rank LC resonance band filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620500049.8U CN205792524U (en) | 2016-05-25 | 2016-05-25 | Radar clock multiplier based on step-recovery diode |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620500049.8U CN205792524U (en) | 2016-05-25 | 2016-05-25 | Radar clock multiplier based on step-recovery diode |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863943A (en) * | 2017-12-04 | 2018-03-30 | 中国电子科技集团公司第四十研究所 | A kind of Novel resistor bias pulse generator and method for generation |
| CN111505638A (en) * | 2020-05-06 | 2020-08-07 | 中国科学院电子学研究所 | Reference frequency signal generation method and device for double-base satellite-borne SAR system |
| CN117411438A (en) * | 2023-12-13 | 2024-01-16 | 成都威频通讯技术有限公司 | Step diode Guan Ji frequency multiplier |
-
2016
- 2016-05-25 CN CN201620500049.8U patent/CN205792524U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107863943A (en) * | 2017-12-04 | 2018-03-30 | 中国电子科技集团公司第四十研究所 | A kind of Novel resistor bias pulse generator and method for generation |
| CN107863943B (en) * | 2017-12-04 | 2020-10-27 | 中国电子科技集团公司第四十一研究所 | Resistance bias pulse generator and generation method |
| CN111505638A (en) * | 2020-05-06 | 2020-08-07 | 中国科学院电子学研究所 | Reference frequency signal generation method and device for double-base satellite-borne SAR system |
| CN117411438A (en) * | 2023-12-13 | 2024-01-16 | 成都威频通讯技术有限公司 | Step diode Guan Ji frequency multiplier |
| CN117411438B (en) * | 2023-12-13 | 2024-03-08 | 成都威频通讯技术有限公司 | Step diode Guan Ji frequency multiplier |
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