CN202364176U - Clock circuit - Google Patents
Clock circuit Download PDFInfo
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- CN202364176U CN202364176U CN2011204647597U CN201120464759U CN202364176U CN 202364176 U CN202364176 U CN 202364176U CN 2011204647597 U CN2011204647597 U CN 2011204647597U CN 201120464759 U CN201120464759 U CN 201120464759U CN 202364176 U CN202364176 U CN 202364176U
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Abstract
The utility model aims at the defect of poor phase noise index of a clock circuit in the prior art to provide a clock circuit capable of improving the phase noise index. The clock circuit comprises a reference frequency generating circuit, a first amplifying circuit, a first frequency multiplier circuit, a first filter circuit, a second amplifying circuit, a second frequency multiplier circuit and a second filter circuit. The reference frequency generating circuit generates reference frequency, the reference frequency is amplified by the first amplifying circuit, the first frequency multiplier circuit performs frequency multiplication, the first filter circuit performs filtering, the second amplifying circuit performs amplification, the second frequency multiplier circuit performs frequency multiplication, and the second filter circuit performs filtering and then outputs expected clock frequency.
Description
Technical field
The utility model relates to electronic circuit field, relates in particular to a kind of clock circuit.
Background technology
The clock source is the key that electronic systems such as radar, communication, tester realize high performance index, and the realization of a lot of modern electronic equipments and systemic-function all directly depends on the performance in used clock source.Current, all realize through frequency synthesis technique in high performance clock source.At present, the main method of frequency synthesis has phase locking technique (being the indirect type frequency synthesis) and Direct Digital method (directly frequency synthesis of base).Indirect frequency synthesizer is the frequency synthesizer that utilizes phase-locked loop to constitute, and it utilizes phase-locked loop narrow-band tracking characteristic, and output frequency is locked on the stable reference frequency.Shortcoming based on the indirect frequency synthesizer of phase-locked loop is the phase noise index error, therefore can not use phase-locked loop to produce the high clock source of phase noise index request.
The utility model content
The utility model provides a kind of clock circuit that can improve the phase noise index to the defective of the phase noise index error of clock circuit in the prior art.
The utility model provides a kind of clock circuit, and this clock circuit comprises that connecting reference frequency in order produces circuit, first amplifying circuit, first frequency multiplier circuit, first filter circuit, second amplifying circuit, second frequency multiplier circuit and second filter circuit, wherein:
Said reference frequency produces circuit and produces reference frequency signal, and said reference frequency signal is through said first amplifying circuit amplifies, the said first frequency multiplier circuit frequency multiplication, the said first filter circuit filtering, said second amplifying circuit are amplified, output is expected after the said second frequency multiplier circuit frequency multiplication and the said second filter circuit filtering clock frequency signal.
Since according to the clock circuit of the utility model through two-stage amplifying circuit, two-stage frequency multiplier circuit and two-stage filter circuit come to reference frequency produce that the reference frequency signal that circuit produces amplifies, frequency multiplication and filtering; So it has the following advantages: (1) phase noise index is good; Because phase noise depends primarily on the phase noise that reference frequency produces circuit, the influence of each frequency multiplier circuit is very little; (2) clock circuit according to the utility model does not adopt phase-locked loop circuit, because phase-locked loop circuit is very responsive to mains fluctuations, so can further reduce phase noise and working stability according to the clock circuit of the utility model; (3) clock circuit according to the utility model does not adopt phase-locked loop circuit, so debugging is simple, and the influence to phase noise is also very little in the debug process; (4) clock circuit according to the utility model does not adopt expensive phase-locked loop and voltage-controlled oscillator circuit, so cost is low.
Description of drawings
Fig. 1 is the block diagram according to the clock circuit of the utility model;
Fig. 2 is a kind of circuit diagram according to the clock circuit of the utility model;
Fig. 3 is the spectral characteristic sketch map according to the negative terminal node place of diode D11 in first frequency multiplier circuit of the clock circuit of the utility model;
Fig. 4 is the spectral characteristic sketch map according to the output signal of first frequency multiplier circuit of the clock circuit of the utility model;
Fig. 5 is the schematic spectral characteristic according to the output signal of first filter circuit of the clock circuit of the utility model;
Fig. 6 is the schematic spectral characteristic according to the output signal of second frequency multiplier circuit of the clock circuit of the utility model;
Fig. 7 is the schematic spectral characteristic according to the output signal of second filter circuit of the clock circuit of the utility model;
Fig. 8 is another circuit diagram according to the clock circuit of the utility model.
Embodiment
Come the clock circuit according to the utility model is described in detail below in conjunction with accompanying drawing.
Of Fig. 1; Comprise that according to the clock circuit of the utility model reference frequency produces circuit 101, first amplifying circuit 102, first frequency multiplier circuit 103, first filter circuit 104, second amplifying circuit 105, second frequency multiplier circuit 106 and second filter circuit 107; Wherein: said reference frequency produces circuit 101 and produces reference frequency signal, the clock frequency signal of said reference frequency signal output expectation after 102 amplifications of said first amplifying circuit, said first frequency multiplier circuit, 103 frequencys multiplication, 104 filtering of said first filter circuit, 105 amplifications of said second amplifying circuit, said second frequency multiplier circuit, 106 frequencys multiplication and 107 filtering of said second filter circuit.
Reference frequency produces circuit 101 and is used for coming as required to the whole system clock circuit of (promptly according to the utility model) reference frequency signal f0 being provided; Wherein, Reference frequency produces circuit 101 can adopt the various forms of circuit that can produce reference frequency signal, preferably adopts active crystal oscillator.Fig. 2 shows a kind of circuit diagram according to the clock circuit of the utility model.In Fig. 2; Reference frequency produces circuit 101 and comprises active crystal oscillator Y1, magnetic bead FB1, capacitor C1; Wherein, Terminal, an other end that said magnetic bead FB1 one end is connected to said capacitor C1 are connected to power supply VCC, and the another terminal of said capacitor C1 is connected to ground, said active crystal oscillator Y1 have four terminals be power supply terminal, terminal, lead-out terminal and unsettled terminal; And the public terminal of said magnetic bead FB1 and said capacitor C1 is connected on the power supply terminal of said active crystal oscillator Y1; The ground terminal ground connection of said active crystal oscillator Y1, the lead-out terminal of said active crystal oscillator Y1 is to the said reference frequency signal of said first amplifying circuit, 102 outputs, and the unsettled terminal of said active crystal oscillator Y1 is unsettled.Like this, power supply VCC just supplies power to active crystal oscillator Y1 through magnetic bead FB1, and capacitor C1 is as power supply coupling capacitor.
Preferably; As shown in Figure 2; First amplifying circuit 102 can comprise the first amplifier U1, capacitor C2, capacitor C5 and inductor L1; The termination of wherein said capacitor C2 is received said reference frequency, another terminal is connected on the input terminal of the said first amplifier U1; The end of said inductor L1 is connected on the power supply VCC, another terminal is connected on the lead-out terminal of said first amplifier, and the end of said capacitor C5 is connected on the power supply VCC, another terminal ground connection, the 3rd terminal ground connection of the said first amplifier U1.It is thus clear that the first amplifier U1, inductor L1 and capacitor C5 have constituted radio-frequency amplifier circuit, be used for the reference frequency signal f0 that reference frequency generation circuit 101 produces is amplified.
Also as shown in Figure 2; Said first frequency multiplier circuit 103 can comprise capacitor C4, inductor L4, diode D11, diode D10, inductor L2, inductor L3, capacitor C16 and capacitor C21; Wherein, Output signal, the another terminal that said capacitor C4 one termination is received said first amplifying circuit 102 is connected to the negative terminal of said diode D11; The public terminal of said inductor L4 and said inductor L2 and the plus end of said diode D10 are connected on the negative terminal of said diode D11; The plus end of said inductor L4, said diode D11 and the negative terminal ground connection of said diode D10; The another terminal of said inductor L2 is connected to the public terminal of said capacitor C16 and said inductor L3, the another terminal ground connection of said inductor L3, and the another terminal of said capacitor C16 is connected on the terminal of said capacitor C21; The another terminal ground connection of said capacitor C21, the public terminal of said capacitor C16 and said capacitor C21 is as the output of said first frequency multiplier circuit 103.In this first frequency multiplier circuit 103; Reference frequency signal f0 produces harmonic signal through diode D11 and D10; Wherein, parallel connection oppositely is connected diode D11 with D10, as the frequency selection circuit of odd harmonics; It can carry out frequency multiplication with the output signal of first amplifying circuit 102, and keep odd number time signal gain, slacken the gain of even number time signal.Wherein, said diode D11 and said diode D10 can be PIN diode or variable capacitance diode.Schematic spectral characteristic at the output signal at the negative terminal node place of diode D11 is as shown in Figure 3.In addition, in this first frequency multiplier circuit 103, inductor L4 plays a part frequency multiplication input coupling; Inductor L2, inductor L3, capacitor C16 and capacitor C21 have constituted the frequency-selecting impedance matching circuit of holding concurrently, and selected harmonic wave is produced resonance, and suppress unwanted harmonic signal.Numerical value through adjustment inductor L2, inductor L3, capacitor C16 and capacitor C21; Can from the odd harmonics signal that filters out, filter out the N subharmonic once more; Keeping the signal gain of N subharmonic to greatest extent, and slacken the intensity of other harmonic signals.Fig. 4 is the schematic spectral characteristic of the output signal of first frequency multiplier circuit 103, and it shows finishing screen and selects the 5th harmonic signal.
In addition, first filter circuit 104 is used for filtering is carried out in the output of first frequency multiplier circuit 103, thereby suppresses unwanted harmonic signal.First filter circuit 104 can adopt SAW filter, and its centre frequency is the centre frequency of selected harmonic wave.Fig. 5 is the schematic spectral characteristic of the output signal of first filter circuit 104 because first frequency multiplier circuit, 103 finishing screens select the 5th harmonic signal, so 104 filterings of first filter circuit other each harmonic signals, only kept the 5th harmonic signal.
The output signal of first filter circuit 104 is amplified by second amplifying circuit 105 once more.Second amplifying circuit 105 can be as shown in Figure 2; Comprise the second amplifier U3, capacitor C24, capacitor C7 and inductor L5; Output signal, another terminal that the termination of wherein said capacitor C24 is received said first filter circuit are connected on the input terminal of the said second amplifier U3; The end of said inductor L5 is connected on the power supply VCC, another terminal is connected on the lead-out terminal of the said second amplifier U3; The end of said capacitor C7 is connected on the power supply VCC, another terminal ground connection, the 3rd terminal ground connection of the said second amplifier U3.
In addition, second frequency multiplier circuit 106 is used for the output signal of second amplifying circuit 105 is carried out the odd harmonics frequency-selecting, and to keep odd number time signal gain to greatest extent and to slacken even number time signal gain, its circuit diagram can be as shown in Figure 2.Second frequency multiplier circuit 106 can comprise capacitor C25, capacitor C26, capacitor C27, capacitor C18, diode D21 and diode D20; Wherein, Output signal, another terminal that the termination of said capacitor C25 is received said second amplifying circuit 105 are connected on the negative terminal of said diode D21; The public terminal of said capacitor C26, said capacitor C27, said capacitor C18 and the plus end of said diode D20 are connected on the negative terminal of said diode D21; The negative terminal ground connection of the another terminal of the plus end of the another terminal of said capacitor C26, said diode D21, said capacitor C18 and said diode D20, the another terminal of said capacitor C27 is as the output of said second frequency multiplier circuit 106.In second frequency multiplier circuit 106, diode D21 and D20 are used to produce harmonic signal, and capacitor C26 is as frequency multiplication input coupling, and capacitor C18 is used for the frequency-selecting impedance matching of holding concurrently.Wherein, said diode D21 and said diode D20 can be PIN diode.The schematic spectral characteristic of the output signal of second frequency multiplier circuit 106 is as shown in Figure 6.
The output of second frequency multiplier circuit 106 can obtain the odd harmonics nnf of appointment after 107 filtering of second filter circuit
0, promptly obtain a local oscillation signal L
0, the spectral characteristic sketch map of the output signal of second filter circuit 107 is as shown in Figure 7.
The circuit implementation of odd harmonics being carried out frequency multiplication has more than been described.Below in conjunction with Fig. 8 the circuit implementation that the dual numbers subharmonic carries out frequency multiplication is described.
For the dual numbers subharmonic carries out frequency multiplication; First frequency multiplier circuit 103 and second frequency multiplier circuit 106 can be as shown in Figure 8, and reference frequency produces circuit 101, first amplifying circuit 102, first filter circuit 104, second amplifying circuit 105, second filter circuit 107 then can be same as shown in Figure 2.
As shown in Figure 8; First frequency multiplier circuit 103 can comprise capacitor C4, inductor L4, diode D1, resistor R 1, inductor L2, inductor L3, capacitor C16 and capacitor C21; Wherein, Output signal, the another terminal that said capacitor C4 one termination is received the said first amplifying circuit U1 is connected to the negative terminal of said diode D1; The public terminal of said inductor L4, said resistor R 1 and said inductor L2 is connected on the negative terminal of said diode D1; The another terminal ground connection of the plus end of the another terminal of said inductor L4, said diode D1 and said resistor R 1; The another terminal of said inductor L2 is connected to the public terminal of said capacitor C16 and said inductor L3, the another terminal ground connection of said inductor L3, and the another terminal of said capacitor C16 is connected on the terminal of said capacitor C21; The another terminal ground connection of said capacitor C21, the public terminal of said capacitor C16 and said capacitor C21 is as the output of said first frequency multiplier circuit 103.Wherein, diode D1 can be PIN diode or variable capacitance diode.
In addition; As shown in Figure 8; Second frequency multiplier circuit 106 can comprise capacitor C25, capacitor C26, capacitor C27, capacitor C18, diode D2 and resistor R 2; Wherein, Output signal, another terminal that the termination of said capacitor C25 is received the said second amplifying circuit U3 are connected on the negative terminal of said diode D2; The public terminal of said capacitor C26, said capacitor C27, said capacitor C18 and said resistor R 2 is connected on the negative terminal of said diode D2, the another terminal ground connection of the plus end of the another terminal of said capacitor C26, said diode D2, the another terminal of said capacitor C18 and said resistor R 2, and the another terminal of said capacitor C27 is as the output of said second frequency multiplier circuit 106.Wherein, diode D2 can be PIN diode.
In another preferred implementation according to the utility model; Can produce in the circuit 101 in reference frequency and increase frequency tuning circuit; Reference frequency reference frequency is produced circuit 101 generations is finely tuned, thereby makes reference frequency produce the more accurate reference frequency of circuit 101 outputs.
As shown in Figures 2 and 3; Said frequency tuning circuit can comprise variable resistance R3 and capacitor C9; Wherein, First fixed terminal of said variable resistance R3 is connected to power supply VCC, and second fixed terminal of said variable resistance R3 and the movable terminal of said variable resistance R3 all are connected on the unsettled terminal of said active crystal oscillator Y1, and the terminal of said capacitor C9 is connected on the unsettled terminal of said active crystal oscillator Y1, another terminal ground connection.Through the resistance value of adjustment variable resistance R3, just can finely tune the output reference frequency that reference frequency produces circuit 101.
More than combine preferred implementation that the clock circuit according to the utility model is described, should be appreciated that under the situation that does not deviate from the utility model spirit and scope, can carry out various distortion and modification the utility model.
Claims (15)
1. a clock circuit is characterized in that, this clock circuit comprises that the reference frequency that connects in order produces circuit, first amplifying circuit, first frequency multiplier circuit, first filter circuit, second amplifying circuit, second frequency multiplier circuit and second filter circuit, wherein:
Said reference frequency produces circuit and produces reference frequency signal, and said reference frequency signal is through said first amplifying circuit amplifies, the said first frequency multiplier circuit frequency multiplication, the said first filter circuit filtering, said second amplifying circuit are amplified, output is expected after the said second frequency multiplier circuit frequency multiplication and the said second filter circuit filtering clock frequency signal.
2. clock circuit according to claim 1; It is characterized in that; Said reference frequency produces circuit and comprises active crystal oscillator Y1, magnetic bead FB1, capacitor C1, and wherein, terminal, an other end that said magnetic bead FB1 one end is connected to said capacitor C1 are connected to power supply; The another terminal of said capacitor C1 is connected to ground; Said active crystal oscillator Y1 have four terminals be power supply terminal, terminal, lead-out terminal and unsettled terminal, and the public terminal of said magnetic bead FB1 and said capacitor C1 is connected on the power supply terminal of said active crystal oscillator Y1 the ground terminal ground connection of said active crystal oscillator Y1; The lead-out terminal of said active crystal oscillator Y1 is exported said reference frequency to said first amplifying circuit, and the unsettled terminal of said active crystal oscillator Y1 is unsettled.
3. clock circuit according to claim 2 is characterized in that, said reference frequency produces circuit and also comprises the frequency tuning circuit that the said reference frequency generation reference frequency signal that circuit produced is finely tuned.
4. clock circuit according to claim 3; It is characterized in that; Said frequency tuning circuit comprises variable resistance R3 and capacitor C9, and wherein, first fixed terminal of said variable resistance R3 is connected to said power supply; Second fixed terminal of said variable resistance R3 and the movable terminal of said variable resistance R3 all are connected on the unsettled terminal of said active crystal oscillator Y1, and the terminal of said capacitor C9 is connected on the unsettled terminal of said active crystal oscillator Y1, another terminal ground connection.
5. clock circuit according to claim 1; It is characterized in that; Said first amplifying circuit comprises first amplifier, capacitor C2, capacitor C5 and inductor L1; The termination of wherein said capacitor C2 is received said reference frequency, another terminal is connected on said first amplifier input terminal; The end of said inductor L1 is connected on the power supply, another terminal is connected on the lead-out terminal of said first amplifier, and the end of said capacitor C5 is connected on the said power supply, another terminal ground connection, the 3rd terminal ground connection of said first amplifier.
6. according to the described clock circuit of each claim in the claim 1 to 5; It is characterized in that; Said first frequency multiplier circuit comprises capacitor C4, inductor L4, diode D11, diode D10, inductor L2, inductor L3, capacitor C16 and capacitor C21; Wherein, Output signal, the another terminal that said capacitor C4 one termination is received said first amplifying circuit is connected to the negative terminal of said diode D11; The public terminal of said inductor L4 and said inductor L2 and the plus end of said diode D10 are connected on the negative terminal of said diode D11, the plus end of said inductor L4, said diode D11 and the negative terminal ground connection of said diode D10, and the another terminal of said inductor L2 is connected to the public terminal of said capacitor C16 and said inductor L3; The another terminal ground connection of said inductor L3; The another terminal of said capacitor C16 is connected on the terminal of said capacitor C21, the another terminal ground connection of said capacitor C21, and the public terminal of said capacitor C16 and said capacitor C21 is as the output of said first frequency multiplier circuit.
7. clock circuit according to claim 6 is characterized in that, said diode D11 and said diode D10 are PIN diode or variable capacitance diode.
8. clock circuit according to claim 6; It is characterized in that; Said second amplifying circuit comprises second amplifier, capacitor C24, capacitor C7 and inductor L5; Output signal, another terminal that the termination of wherein said capacitor C24 is received said first filter circuit are connected on said second amplifier input terminal; The end of said inductor L5 is connected on the power supply, another terminal is connected on the lead-out terminal of said second amplifier, and the end of said capacitor C7 is connected on the said power supply, another terminal ground connection, the 3rd terminal ground connection of said second amplifier.
9. clock circuit according to claim 6; It is characterized in that; Said second frequency multiplier circuit comprises capacitor C25, capacitor C26, capacitor C27, capacitor C18, diode D21 and diode D20; Wherein, Output signal, another terminal that the termination of said capacitor C25 is received said second amplifying circuit are connected on the negative terminal of said diode D21; The public terminal of said capacitor C26, said capacitor C27, said capacitor C18 and the plus end of said diode D20 are connected on the negative terminal of said diode D21, the negative terminal ground connection of the plus end of the another terminal of said capacitor C26, said diode D21, the another terminal of said capacitor C18 and said diode D20, and the another terminal of said capacitor C27 is as the output of said second frequency multiplier circuit.
10. clock circuit according to claim 9 is characterized in that, said diode D21 and said diode D20 are PIN diode.
11. according to the described clock circuit of each claim in the claim 1 to 5; It is characterized in that; Said first frequency multiplier circuit comprises capacitor C4, inductor L4, diode D1, resistor R 1, inductor L2, inductor L3, capacitor C16 and capacitor C21; Wherein, Output signal, the another terminal that said capacitor C4 one termination is received said first amplifying circuit is connected to the negative terminal of said diode D1; The public terminal of said inductor L4, said resistor R 1 and said inductor L2 is connected on the negative terminal of said diode D1, the plus end of the another terminal of said inductor L4, said diode D1 and the another terminal ground connection of said resistor R 1, and the another terminal of said inductor L2 is connected to the public terminal of said capacitor C16 and said inductor L3; The another terminal ground connection of said inductor L3; The another terminal of said capacitor C16 is connected on the terminal of said capacitor C21, the another terminal ground connection of said capacitor C21, and the public terminal of said capacitor C16 and said capacitor C21 is as the output of said first frequency multiplier circuit.
12. clock circuit according to claim 11 is characterized in that, said diode D1 is PIN diode or variable capacitance diode.
13. clock circuit according to claim 11; It is characterized in that; Said second amplifying circuit comprises second amplifier, capacitor C24, capacitor C7 and inductor L5; Output signal, another terminal that the termination of wherein said capacitor C24 is received said first filter circuit are connected on said second amplifier input terminal; The end of said inductor L5 is connected on the power supply, another terminal is connected on the lead-out terminal of said second amplifier, and the end of said capacitor C7 is connected on the said power supply, another terminal ground connection, the 3rd terminal ground connection of said second amplifier.
14. clock circuit according to claim 11; It is characterized in that; Said second frequency multiplier circuit comprises capacitor C25, capacitor C26, capacitor C27, capacitor C18, diode D2 and resistor R 2; Wherein, Output signal, another terminal that the termination of said capacitor C25 is received said second amplifying circuit are connected on the negative terminal of said diode D2; The public terminal of said capacitor C26, said capacitor C27, said capacitor C18 and said resistor R 2 is connected on the negative terminal of said diode D2, the another terminal ground connection of the plus end of the another terminal of said capacitor C26, said diode D2, the another terminal of said capacitor C18 and said resistor R 2, and the another terminal of said capacitor C27 is as the output of said second frequency multiplier circuit.
15. clock circuit according to claim 14 is characterized in that, said diode D2 is a PIN diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204647597U CN202364176U (en) | 2011-11-21 | 2011-11-21 | Clock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204647597U CN202364176U (en) | 2011-11-21 | 2011-11-21 | Clock circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202364176U true CN202364176U (en) | 2012-08-01 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204647597U Expired - Lifetime CN202364176U (en) | 2011-11-21 | 2011-11-21 | Clock circuit |
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| CN (1) | CN202364176U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014032253A1 (en) * | 2012-08-30 | 2014-03-06 | 海能达通信股份有限公司 | Voltage-controlled oscillator and wireless communication device |
| CN104660257A (en) * | 2015-03-25 | 2015-05-27 | 天津七六四通信导航技术有限公司 | L-band frequency synthesizer circuit |
| CN105959002A (en) * | 2016-05-18 | 2016-09-21 | 成都福兰特电子技术股份有限公司 | Wireless signal emission system of aviation communication |
-
2011
- 2011-11-21 CN CN2011204647597U patent/CN202364176U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014032253A1 (en) * | 2012-08-30 | 2014-03-06 | 海能达通信股份有限公司 | Voltage-controlled oscillator and wireless communication device |
| CN104660257A (en) * | 2015-03-25 | 2015-05-27 | 天津七六四通信导航技术有限公司 | L-band frequency synthesizer circuit |
| CN105959002A (en) * | 2016-05-18 | 2016-09-21 | 成都福兰特电子技术股份有限公司 | Wireless signal emission system of aviation communication |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120801 |
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| CX01 | Expiry of patent term |