CN112151600A - Cell structure of power semiconductor device and manufacturing method thereof - Google Patents
Cell structure of power semiconductor device and manufacturing method thereof Download PDFInfo
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 118
- 239000002184 metal Substances 0.000 claims abstract description 118
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- 229910002704 AlGaN Inorganic materials 0.000 claims abstract 2
- 238000000034 method Methods 0.000 claims description 32
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7789—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface the two-dimensional charge carrier gas being at least partially not parallel to a main surface of the semiconductor body
Abstract
The invention discloses a cell structure of a power semiconductor device and a manufacturing method thereof, wherein the cell structure comprises: a first conductivity type epitaxial layer on a surface of the first conductivity type substrate; the second conductive type base regions are positioned at two sides of the middle part of the epitaxial layer and are preset with junction depths; the channel layer is positioned on the surface of the second conductive type base region and is in contact with the middle part of the epitaxial layer; a barrier layer over a surface of the channel layer; a dielectric layer on the barrier layer near the middle of the epitaxial layer and a gate metal on the dielectric layer; the source metal is positioned on the barrier layer far away from the middle part of the epitaxial layer, and the source metal is isolated from the gate metal by adopting an insulating layer; and the drain metal is positioned at the bottom of the first conduction type substrate. According to the invention, the AlGaN/GaN heterojunction is arranged, so that the channel carrier mobility is greatly increased, the on-resistance is reduced, and the influence of gate oxide failure on the reliability of the device is avoided due to the fact that the grid oxide layer is not arranged, so that the high-voltage-resistant capacity is realized.
Description
Technical Field
The invention relates to the technical field of power semiconductor devices, in particular to a cell structure of a power semiconductor device and a manufacturing method thereof.
Background
Silicon carbide SiC power devices have been rapidly developed in recent years due to their excellent material advantages. The device characteristics of high voltage, high frequency, high temperature and high power density make it have a huge market in the field of high-efficiency power conversion, wherein the development of metal-oxide-semiconductor field effect transistors (MOSFET) is most concerned.
The traditional SiC planar MOSFET device has low channel mobility, large on-resistance, high density of gate oxide interface states and poor reliability, and the further development of the SiC MOSFET is restricted by the problems of the channel mobility and the gate oxide reliability.
The cross-sectional structure of a conventional MOSFET device is shown in fig. 1, and includes: the structure comprises a drain electrode metal 1, a substrate layer 2, an epitaxial layer 3, a p-type base region 4, an n-type source region 5, a grid oxide layer 6, a polycrystalline silicon grid electrode 7, a grid electrode insulating medium 8 and a source electrode metal 9.
There is a need for an enhanced MOSFET device that improves channel carrier mobility and overcomes the effect of gate oxide failure on device reliability.
Disclosure of Invention
The cellular structure of the power semiconductor device solves the technical problem of low channel mobility of the MOSFET device, improves the carrier mobility of the channel of the device, and avoids the influence of gate oxide failure on the reliability of the device.
The invention provides a cell structure of a power semiconductor device, comprising:
a first conductive type epitaxial layer on a surface of the first conductive type substrate;
the second conductive type base region is positioned at two sides of the middle part of the epitaxial layer and is preset with junction depth;
the channel layer is positioned on the surface of the second conduction type base region and is in contact with the middle of the epitaxial layer;
a barrier layer over a surface of the channel layer;
a dielectric layer over the barrier layer near the middle of the epitaxial layer and a gate metal over the dielectric layer;
a source metal located on the barrier layer away from the middle of the epitaxial layer, wherein the source metal is isolated from the gate metal by an insulating layer;
and the drain metal is positioned at the bottom of the first conduction type substrate.
In an embodiment of the present invention, it is,
the middle surface of the epitaxial layer is higher than the surfaces of the second conductive type base regions at the two ends of the epitaxial layer.
In an embodiment of the present invention, it is,
the channel layer comprises a first channel layer, a second channel layer and a third channel layer, wherein two sides of the first channel layer are connected with the second channel layer and the third channel layer, the first channel layer covers two side walls of the middle part of the epitaxial layer, the second channel layer covers the surface of the second conduction type base region, and the third channel layer covers part of the surface of the middle part of the epitaxial layer;
the barrier layers comprise a first barrier layer, a second barrier layer and a third barrier layer, wherein the second barrier layer and the third barrier layer are connected to two sides of the first barrier layer, the first barrier layer covers the surface of the first channel layer, the second barrier layer covers the surface of the second channel layer, and the third barrier layer covers the surface of the third channel layer.
In an embodiment of the present invention, it is,
a metal layer is arranged on the middle surface of the epitaxial layer;
the channel layer comprises a first channel layer and a second channel layer, two sides of the first channel layer are connected with the second channel layer and the metal layer, the first channel layer covers two side walls of the middle part of the epitaxial layer, and the second channel layer covers the surface of the second conduction type base region;
the barrier layers comprise the first barrier layer and the second barrier layer, two sides of the first barrier layer are connected with the second barrier layer and the metal layer, the first barrier layer covers the surface of the first channel layer, and the second barrier layer covers the surface of the second channel layer.
In an embodiment of the present invention, it is,
the middle surface of the epitaxial layer is flush with the surfaces of the second conduction type base regions at two ends of the epitaxial layer;
the channel layer is positioned on the surface of the second conduction type base region and is in contact with part of the surface of the middle part of the epitaxial layer;
the barrier layer is positioned above the surface of the channel layer and is in contact with a part of the surface of the middle part of the epitaxial layer.
In an embodiment of the present invention, it is,
the material of the channel layer is GaN;
the barrier layer is made of AlGaN;
the preset junction depth of the second conductive type base region is 0.2-1.5 microns;
the doping concentration of the base region of the second conduction type is 1e18cm-3～5e19cm-3；
The thickness of the channel layer is 6 nm-14 nm;
the thickness of the barrier layer is 10 nm-20 nm.
The present invention provides a power semiconductor device having a plurality of power transistors,
a cell structure comprising several power semiconductor devices as described in any of the above.
In an embodiment of the present invention, it is,
the shapes of the cellular structures comprise strips, quadrangles, hexagons, octagons, circles, lattice arrays or combinations of the above shapes.
The invention provides a method for manufacturing a cellular structure of a power semiconductor device, which comprises the following steps:
forming a first conductive type epitaxial layer on a surface of a first conductive type substrate;
implanting ions into the upper surfaces of the two ends of the epitaxial layer through photoetching to form a second conductive type base region at a preset junction depth;
forming a channel layer on the surface of the second conductive type base region through deposition and etching processes, wherein the channel layer is in contact with the middle of the epitaxial layer;
forming a barrier layer on the surface of the channel layer by deposition and etching processes;
forming a dielectric layer over the barrier layer near the middle of the epitaxial layer and a gate metal over the dielectric layer;
forming a source metal over the barrier layer away from a middle portion of the epitaxial layer;
and forming drain metal at the bottom of the first conduction type substrate.
In an embodiment of the present invention, it is,
after the step of forming the first conductive type epitaxial layer on the surface of the first conductive type substrate, the method further comprises the following steps:
and etching the two sides of the middle part of the surface of the epitaxial layer to a preset depth, wherein the preset depth is 0.2-0.5 mu m.
One or more embodiments of the present invention may have the following advantages over the prior art:
according to the invention, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is arranged, so that the channel carrier mobility is greatly increased, and the on-resistance is reduced; the MOSFET device structure does not need to be provided with a grid oxide layer, so that the influence of grid oxide failure on the reliability of the device is avoided; the second conductive type base region with the appointed junction depth is arranged, so that the high-voltage-resistance LED lamp has higher voltage-resistance capability; the invention also reduces the pitch of the cellular structure of the device, and is beneficial to improving the yield of the device.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
fig. 1 is a cross-sectional structural view showing a conventional MOSFET device;
fig. 2 is a schematic sectional structure of a power semiconductor device of embodiment 1 of the present invention;
fig. 3 is a schematic sectional current path of a power semiconductor device according to embodiment 1 of the present invention;
fig. 4 is a schematic sectional structure of a power semiconductor device of embodiment 2 of the present invention;
fig. 5 is a schematic sectional structure of a power semiconductor device of embodiment 3 of the invention;
FIG. 6 is a schematic flow chart of a manufacturing method according to example 5 of the present invention;
FIG. 7 is a schematic cross-sectional view of the structure of example 5 of the present invention after S100;
FIG. 8 is a schematic cross-sectional view of example 5 of the present invention after S101;
FIG. 9 is a schematic cross-sectional view of example 5 after S102;
fig. 10 is a schematic cross-sectional view of embodiment 5 of the present invention after S103.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following detailed description of the present invention with reference to the accompanying drawings is provided to fully understand and implement the technical effects of the present invention by solving the technical problems through technical means. It should be noted that, as long as there is no conflict, the embodiments and the features of the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
First embodiment
Fig. 2 is a schematic sectional structure of a power semiconductor device of embodiment 1 of the present invention;
fig. 3 is a schematic sectional current path of a power semiconductor device according to embodiment 1 of the present invention;
the power semiconductor device of the present embodiment, as shown in fig. 2, includes: a first conductivity type substrate 11, a first conductivity type epitaxial layer 12, a second conductivity type base region 13, a channel layer 14, a barrier layer 15, a source metal 16, a second conductivity type dielectric layer 17, a gate metal 18, and a drain metal 19.
The conductivity type used in each part in this embodiment may be set to be a first conductivity type or a second conductivity type, and the first conductivity type and the second conductivity type are complementary conductivity types.
In this embodiment, the N-type is set to be the first conductivity type, and the P-type is set to be the second conductivity type.
The power semiconductor device includes a MOSFET or an IGBT, and the present embodiment is described with the MOSFET as an example. The substrate material includes semiconductor elements such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials such as silicon carbide, gallium nitride, gallium sesquioxide, alloy semiconductors, or combinations thereof, without limitation. In this embodiment, the first conductivity type substrate is a doped substrate, the substrate in this embodiment is preferably a silicon carbide substrate, and an N-type or P-type silicon carbide substrate may be used, and in this embodiment, the doped N-type substrate is taken as an example, and the N-type substrate 11 has a resistivity in a range of 0.01 Ω · cm to 0.03 Ω · cm and a thickness in a range of 200 μm to 400 μm.
The embodiment provides a cell structure of a power semiconductor device, which comprises:
a first conductivity type epitaxial layer 12 on a surface of the first conductivity type substrate 11;
a second conductive type base region 13 located at two sides of the middle of the epitaxial layer 12 and with a preset junction depth;
a channel layer 14 located on the surface of the second conductivity type base region 13 and in contact with the middle of the epitaxial layer 12;
a barrier layer 15 located over a surface of the channel layer 14;
a dielectric layer 17 over the barrier layer 15 near the middle of the epitaxial layer 12 and a gate metal 18 over the dielectric layer 17;
a source metal 16 located on the barrier layer away from the middle of the epitaxial layer 12, wherein the source metal 16 is separated from the gate metal 18 by an insulating layer;
a drain metal 19 located at the bottom of the first conductive type substrate 11.
Specifically, in the present embodiment, the first conductivity type epitaxial layer 12 is disposed on the surface of the first conductivity type substrate 11, the material of the first conductivity type epitaxial layer 12 includes, but is not limited to, silicon carbide, gallium nitride or gallium sesquioxide, the present embodiment is preferably silicon carbide, and the doping concentration of the first conductivity type epitaxial layer 12 is 5e 14-5 e16cm-3。
Second conductive type base regions 13 with preset junction depths are arranged on two sides of the middle of the epitaxial layer 12, in this embodiment, the middle surface of the epitaxial layer 12 is higher than the surfaces of the second conductive type base regions 13 at two ends of the epitaxial layer 12, the preset junction depths of the second conductive type base regions 13 are 0.2-1.0 μm, and the doping concentration of the second conductive type base regions 13 is 1e18cm-3～5e19cm-3。
In this embodiment, the channel layer includes a first channel layer, a second channel layer, and a third channel layer, where the second channel layer and the third channel layer are connected to two sides of the first channel layer, and specifically, the second channel layer on the surface of the second conductive type base region 13 and the third channel layer on the surface of the middle portion of the epitaxial layer 12 are connected to two sides of the first channel layer covering sidewalls on two sides of the middle portion of the epitaxial layer 12, where the first channel layer covers sidewalls on two sides of the middle portion of the epitaxial layer 12, the second channel layer is disposed on the surface of the second conductive type base region 13, and the third channel layer covers the surface of the middle portion of the epitaxial layer 12. In this embodiment, the material of the channel layer is GaN, and the thickness of the channel layer is 6nm to 14 nm. The upper surface of the second conductivity type base region 13 is in contact with the second channel layer, and the left surface and the lower surface are in contact with the epitaxial layer 12.
The barrier layer 15 is disposed on the surface of the channel layer 14, and in this embodiment, the barrier layer includes a first barrier layer, a second barrier layer, and a third barrier layer, where two sides of the first barrier layer are connected to the second barrier layer and the third barrier layer, specifically, two sides of the first barrier layer covering the first channel layer are connected to the second barrier layer on the surface of the second channel layer and the third barrier layer covering the surface of the third channel layer, where the first barrier layer covers the first channel layer, the second barrier layer is disposed on the surface of the second channel layer, and the third barrier layer covers the surface of the third channel layer. In this embodiment, the material of the barrier layer 15 is AlGaN, and the thickness of the barrier layer 15 is 10nm to 20 nm. The first surface of the channel layer 14 is entirely in contact with the barrier layer 15, and a portion of the second surface is in contact with the upper surface of the second conductivity-type base region 13, a portion of the second surface is in contact with the side walls on both sides of the middle portion of the epitaxial layer 12, and a portion of the second surface is in contact with a portion of the surface of the middle portion of the epitaxial layer 12.
A dielectric layer 17 is arranged on the barrier layer 15 close to the middle part of the epitaxial layer 12, and a gate metal 18 is arranged on the dielectric layer 17; a source metal 16 is disposed over the barrier layer 15 away from the middle of the epitaxial layer 12, wherein the source metal 16 is separated from the gate metal 18 by an insulating layer. Except the bottom of the dielectric layer 17, the other surfaces of the dielectric layer are isolated from the barrier layer 15 by insulating layers, and the gate metal 18 is isolated from the barrier layer 15 by insulating layers. In the present embodiment, the dielectric layer 17 is a second conductivity type GaN dielectric layer. In the present embodiment, the barrier layer 15 is in full contact with the upper surface of the channel layer 14, wherein the bottom of the third barrier layer of the barrier layer 15 is also in contact with the surface of the middle portion of the epitaxial layer 12 except the surface covered by the channel layer 14.
A drain metal 19 is provided on the bottom of the first conductivity type substrate 11.
The cell structure of the power semiconductor device of the embodiment extends a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on a silicon carbide (SiC) drift region, and generates a high-concentration two-dimensional electron gas at an interface through the polarization effect of a GaN/AlGaN heterojunction, wherein the two-dimensional electron gas (2DEG) refers to a quantum well with degenerate depth of electrons or holes, the quantum well is only 1-2 nm wide, and carriers can move in a two-dimensional plane parallel to the interface and are limited in the well in a direction perpendicular to the interface. HEMTs take advantage of the fact that impurities and electrons in a semiconductor heterostructure can be spatially separated, so that the electrons have a high mobility. In the structure, the current from the source (source) to the drain (drain) can be controlled by changing the voltage of the gate (gate), and the HEMT structure has the advantages of high carrier concentration and high electron mobility. Therefore, a two-dimensional electron gas layer in the HEMT structure is adopted to replace a channel region below a grid electrode in a typical metal-oxide-semiconductor field effect transistor (MOSFET) device, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is adopted to greatly increase the channel carrier mobility, and the on-resistance of the device is reduced. After the device structure of the embodiment is adopted, the NPN latch-up effect of the SiC planar MOSFET can be avoided due to the fact that the on-resistance of the device is reduced. Meanwhile, as the device structure of the embodiment is not provided with the grid oxide layer, the influence of grid oxide failure on the reliability of the power semiconductor device is avoided, and the reliability of the power semiconductor device is improved.
In the power semiconductor device of the embodiment, the bias voltage is simultaneously applied to the gate and the drain, when the voltage applied to the gate is less than or equal to the threshold voltage, the two-dimensional electron gas channel is closed, no obvious current passes through, and when the voltage applied to the gate is greater than the threshold voltage, the two-dimensional electron gas channel DEG is opened, and a larger current can pass through. Under the action of drain voltage, electrons enter the 2DEG channel of AlGaN/GaN from the ohmic contact metal of the source electrode, then enter the SiC epitaxial layer and the SiC substrate to reach the drain metal to form a current loop, and the current path is shown in FIG. 3.
In the power semiconductor device structure of the embodiment, the P-type injection base region and the N-type drift region form a PN junction to bear blocking voltage, and the spaced P-type base regions can effectively shield an electric field for the upper structure, so that the voltage withstanding capability of the device is enhanced.
According to the embodiment, the device structure of the traditional MOSFET is optimized, so that the pitch of the cell structure of the device is reduced, and the cost of the device is reduced.
In summary, in the present embodiment, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is arranged, so that the channel carrier mobility is greatly increased, and the on-resistance is reduced; the MOSFET device structure is not provided with the grid oxide layer, so that the influence of grid oxide failure on the reliability of the device is avoided; the second conductive type base region with the appointed junction depth is arranged, so that the high-voltage-resistance LED lamp has higher voltage resistance.
Second embodiment
Fig. 4 is a schematic cross-sectional structure of the power semiconductor device of the present embodiment 2;
the power semiconductor device of the present embodiment, as shown in fig. 4, includes: the semiconductor device includes a drain metal 21, a first conductivity type substrate 22, a first conductivity type epitaxial layer 23, a second conductivity type base region 24, a channel layer 25, a barrier layer 26, a source metal 27, a second conductivity type dielectric layer 28, a gate metal 29, and a metal layer 30.
The conductivity type used in each part in this embodiment may be set to be a first conductivity type or a second conductivity type, and the first conductivity type and the second conductivity type are complementary conductivity types.
In this embodiment, the N-type is set to be the first conductivity type, and the P-type is set to be the second conductivity type.
The power semiconductor device includes a MOSFET or an IGBT, and the present embodiment is described with the MOSFET as an example. The substrate material includes semiconductor elements such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials such as silicon carbide, gallium nitride, gallium sesquioxide, alloy semiconductors, or combinations thereof, without limitation. In this embodiment, the first conductive type substrate is a doped substrate, the substrate in this embodiment is preferably a silicon carbide substrate, and an N-type or P-type silicon carbide substrate may be used, and in this embodiment, the doped N-type substrate is taken as an example, and the N-type substrate 22 has a resistivity in a range of 0.01 Ω · cm to 0.03 Ω · cm and a thickness in a range of 200 μm to 400 μm.
The embodiment provides a cell structure of a power semiconductor device, which comprises:
a first conductivity type epitaxial layer 23 on the surface of the first conductivity type substrate 22;
a second conductive type base region 24 located at two sides of the middle of the epitaxial layer 23 and with a preset junction depth;
a channel layer 25 located on the surface of the second conductivity-type base region 24 and in contact with the middle of the epitaxial layer 23;
a barrier layer 26 located over the surface of the channel layer 25;
a dielectric layer 28 over the barrier layer 26 near the middle of the epitaxial layer 23 and a gate metal 29 over the dielectric layer 28;
a source metal 27 located on the barrier layer far from the middle part of the epitaxial layer 23, wherein the source metal 27 is isolated from the gate metal 29 by an insulating layer;
a drain metal 21 located at the bottom of the first conductive type substrate 22.
Specifically, in the present embodiment, the first conductivity type epitaxial layer 23 is disposed on the surface of the first conductivity type substrate 22, the material of the first conductivity type epitaxial layer 23 includes, but is not limited to, silicon carbide, gallium nitride or gallium sesquioxide, the present embodiment is preferably silicon carbide, and the doping concentration of the first conductivity type epitaxial layer 23 is 5e 14-5 e16cm-3。
Second conductive type base regions 24 with preset junction depths are arranged on two sides of the middle of the epitaxial layer 23, in the embodiment, the middle surface of the epitaxial layer 23 is higher than the surfaces of the second conductive type base regions 24 at two ends of the epitaxial layer 23, the preset junction depths of the second conductive type base regions 24 are 0.2-1.0 μm, and the doping concentration of the second conductive type base regions 24 is 1e18cm-3～5e19cm-3。
A channel layer 25 is arranged on the surface of the second conduction type base region 24, wherein the channel layer 25 is also contacted with the middle part of the epitaxial layer 23, in the embodiment, a metal layer 30 is arranged on the surface of the middle part of the epitaxial layer 23, and the length of the metal layer 30 in the horizontal direction of the cross section of the cellular structure is greater than that of the surface of the middle part of the epitaxial layer.
In this embodiment, the channel layer includes the first channel layer with the second channel layer, and second channel layer and metal layer 30 layer are connected to first channel layer both sides, specifically, cover and connect second channel layer and metal layer 30 on the second conduction type base region surface in the first channel layer both sides of epitaxial layer 23 middle part both sides lateral wall, and wherein first channel layer covers on epitaxial layer 23 middle part both sides lateral wall, and the second channel layer sets up on second conduction type base region 24 surface, and the metal layer covers on epitaxial layer 23 middle part surface, and the bottom of metal layer outside covering epitaxial layer middle part surface is in contact with the first channel layer. In this embodiment, the material of the channel layer is GaN, and the thickness of the channel layer is 6nm to 14 nm. The upper surface of the second conductivity-type base region 24 is in contact with the second channel layer, and the left surface and the lower surface are in contact with the epitaxial layer 23.
The barrier layer 26 is disposed on the surface of the channel layer 25, and in this embodiment, the barrier layer includes the first barrier layer and the second barrier layer, two sides of the first barrier layer are connected to the second barrier layer and the metal layer, specifically, two sides of the first barrier layer covering the first channel layer are connected to the second barrier layer and the metal layer on the surface of the second channel layer, wherein the first barrier layer covers the first channel layer, the second barrier layer is disposed on the surface of the second channel layer, the metal layer covers the middle surface of the epitaxial layer 23, and the bottom of the metal layer outside the middle surface of the epitaxial layer is also in contact with the first barrier layer. In the present embodiment, the material of the barrier layer 26 is AlGaN, and the thickness of the barrier layer 26 is 10nm to 20 nm. The first surface of the channel layer 25 is entirely in contact with the barrier layer 26, and a portion of the second surface is in contact with the upper surface of the second conductivity-type base region 24, a portion of the second surface is in contact with the side walls on both sides of the middle portion of the epitaxial layer 23, and a portion of the second surface is in contact with the bottom of the metal layer covering the middle portion of the epitaxial layer 23.
Providing a dielectric layer 28 over the barrier layer 26 near the middle of the epitaxial layer 23 and a gate metal 29 over the dielectric layer 28; a source metal 27 is provided over the barrier layer 26 away from the middle of the epitaxial layer 23, with an insulating layer separating the source metal 27 from the gate metal 29. Except for the bottom, the dielectric layer 28 is isolated from the barrier layer 26 by an insulating layer, and the gate metal 29 is isolated from the barrier layer 26 by an insulating layer. In the present embodiment, the dielectric layer 28 is a second conductivity type GaN dielectric layer. In the present embodiment, the barrier layer 26 is in full contact with the upper surface of the channel layer 25, wherein the bottom of the third barrier layer of the barrier layer 26 is also in contact with the surface of the middle of the epitaxial layer 23 except the surface covered by the channel layer 25.
A drain metal 21 is provided on the bottom of the first conductivity type substrate 22.
The cell structure of the power semiconductor device of the embodiment extends a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on a silicon carbide (SiC) drift region, and generates a high-concentration two-dimensional electron gas at an interface through the polarization effect of a GaN/AlGaN heterojunction, wherein the two-dimensional electron gas (2DEG) refers to a quantum well with degenerate depth of electrons or holes, the quantum well is only 1-2 nm wide, and carriers can move in a two-dimensional plane parallel to the interface and are limited in the well in a direction perpendicular to the interface. HEMTs take advantage of the fact that impurities and electrons in a semiconductor heterostructure can be spatially separated, so that the electrons have a high mobility. In the structure, the current from the source (source) to the drain (drain) can be controlled by changing the voltage of the gate (gate), and the HEMT structure has the advantages of high carrier concentration and high electron mobility. Therefore, a two-dimensional electron gas layer in the HEMT structure is adopted to replace a channel region below a grid electrode in a typical metal-oxide-semiconductor field effect transistor (MOSFET) device, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is adopted to greatly increase the channel carrier mobility, and the on-resistance of the device is reduced. After the device structure of the embodiment is adopted, the NPN latch-up effect of the SiC planar MOSFET can be avoided due to the fact that the on-resistance of the device is reduced. Meanwhile, as the device structure of the embodiment is not provided with the grid oxide layer, the influence of grid oxide failure on the reliability of the power semiconductor device is avoided, and the reliability of the power semiconductor device is improved.
In the power semiconductor device of the embodiment, the bias voltage is simultaneously applied to the gate and the drain, when the voltage applied to the gate is less than or equal to the threshold voltage, the two-dimensional electron gas channel is closed, no obvious current passes through, and when the voltage applied to the gate is greater than the threshold voltage, the two-dimensional electron gas channel DEG is opened, and a larger current can pass through.
The optimization point of the embodiment and the first embodiment is that the metal layer is arranged on the surface of the middle part of the epitaxial layer, the metal layer is in contact with the GaN channel layer and the AlGaN barrier layer, electrons enter the metal layer after entering the 2DEG channel of AlGaN/GaN of the HEMT structure from ohmic contact metal of the source electrode under the action of drain voltage, and then enter the SiC epitaxial layer and the SiC substrate to reach the drain metal to form a current loop. By arranging the metal layer, the complexity of surface etching patterns can be simplified, the overall process difficulty of the device is reduced, and the cost is reduced.
In the power semiconductor device structure of the embodiment, the P-type injection base region and the N-type drift region form a PN junction to bear blocking voltage, and the spaced P-type base regions can effectively shield an electric field for the upper structure, so that the voltage withstanding capability of the device is enhanced.
According to the embodiment, the device structure of the traditional MOSFET is optimized, so that the pitch of the cell structure of the device is reduced, and the cost of the device is reduced.
In summary, in the present embodiment, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is arranged, so that the channel carrier mobility is greatly increased, and the on-resistance is reduced; the MOSFET device structure is not provided with the grid oxide layer, so that the influence of grid oxide failure on the reliability of the device is avoided; the second conductive type base region with the appointed junction depth is arranged, so that the high-voltage-resistance LED lamp has higher voltage resistance. Meanwhile, due to the arrangement of the metal layer, the manufacturing cost of the device is reduced.
Third embodiment
Fig. 5 is a schematic cross-sectional structure of the power semiconductor device of the present embodiment 3;
the power semiconductor device of the present embodiment, as shown in fig. 5, includes: a drain metal 31, a first conductivity type substrate 32, a first conductivity type epitaxial layer 33, a second conductivity type base region 34, a channel layer 35, a barrier layer 36, a source metal 37, a second conductivity type dielectric layer 38, and a gate metal 39.
The conductivity type used in each part in this embodiment may be set to be a first conductivity type or a second conductivity type, and the first conductivity type and the second conductivity type are complementary conductivity types.
In this embodiment, the N-type is set to be the first conductivity type, and the P-type is set to be the second conductivity type.
The power semiconductor device includes a MOSFET or an IGBT, and the present embodiment is described with the MOSFET as an example. The substrate material includes semiconductor elements such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials such as silicon carbide, gallium nitride, gallium sesquioxide, alloy semiconductors, or combinations thereof, without limitation. The first conductive type substrate in this embodiment is a doped substrate, the substrate in this embodiment is preferably a silicon carbide substrate, and an N-type or P-type silicon carbide substrate may be used, and in this embodiment, the doped N-type substrate is taken as an example, and the resistivity of the N-type substrate 32 is in a range of 0.01 Ω · cm to 0.03 Ω · cm, and the thickness is in a range of 200 μm to 400 μm.
The embodiment provides a cell structure of a power semiconductor device, which comprises:
a first conductivity type epitaxial layer 33 on the surface of the first conductivity type substrate 32;
a second conductive type base region 34 located at two sides of the middle of the epitaxial layer 33 and having a preset junction depth;
a channel layer 35 located on the surface of the second conductivity-type base region 34 and in contact with the middle of the epitaxial layer 33;
a barrier layer 36 on the surface of the channel layer 35;
a dielectric layer 38 over the barrier layer 36 near the middle of the epitaxial layer 33 and a gate metal 39 over the dielectric layer 38;
a source metal 37 located on the barrier layer far from the middle of the epitaxial layer 33, wherein the source metal 37 is isolated from the gate metal 39 by an insulating layer;
a drain metal 31 at the bottom of the first conductive type substrate 32.
Specifically, in the present embodiment, the first conductivity type epitaxial layer 33 is disposed on the surface of the first conductivity type substrate 32, and the material of the first conductivity type epitaxial layer 33 includes, but is not limited to, silicon carbide, gallium nitride or gallium sesquioxideThe preferred embodiment is silicon carbide, the doping concentration of the first conductive type epitaxial layer 33 is 5e 14-5 e16cm-3。
Second conductive type base regions 34 with preset junction depths are arranged on two sides of the middle of the epitaxial layer 33, in the embodiment, the surface of the middle of the epitaxial layer 33 is flush with the surfaces of the second conductive type base regions 34 at two ends of the epitaxial layer 33, in order to improve the voltage endurance capability of the device, the preset junction depths of the second conductive type base regions 34 are increased, the preset junction depths are 0.6-1.5 micrometers, and the doping concentration of the second conductive type base regions 34 is 1e18cm-3～5e19cm-3。
A channel layer 35 is disposed on the surface of the second-conductivity-type base region 34, and in this embodiment, the channel layer 35 is located on the surface of the second-conductivity-type base region 34 and is in contact with the surface of the middle portion of the epitaxial layer 33, specifically, the bottom of the channel layer 35 is in contact with the upper surface of the second-conductivity-type base region 34 and the surface of the middle portion of the epitaxial layer 33 at the same time. In the present embodiment, the material of the channel layer is GaN, and the thickness of the channel layer 35 is 6nm to 14 nm. The upper surface of the second conductivity-type base region 34 is in contact with the second channel layer, and the left and lower surfaces are in contact with the epitaxial layer 33.
A barrier layer 36 is disposed over the surface of the channel layer 35. in this embodiment, the barrier layer 36 is disposed over the surface of the channel layer 35 and in contact with the surface of the middle portion of the epitaxial layer 33, specifically, the bottom portion of the barrier layer 36 is in contact with both the upper surface of the channel layer 35 and the surface of the middle portion of the epitaxial layer 33. In the present embodiment, the material of the barrier layer 36 is AlGaN, and the thickness of the barrier layer 36 is 10nm to 20 nm. The upper surface of the channel layer 35 is entirely in contact with the barrier layer 36, and the lower surface is simultaneously in contact with the upper surface of the second conductivity-type base region 34 and a part of the surface in the middle of the epitaxial layer 33.
Providing a dielectric layer 38 over the barrier layer 36 near the middle of the epitaxial layer 33 and a gate metal 39 over the dielectric layer 38; a source metal 37 is disposed over the barrier layer 36 away from the middle of the epitaxial layer 33, with an insulating layer separating the source metal 37 from the gate metal 39. Except for the bottom, the dielectric layer 38 is isolated from the barrier layer 36 by an insulating layer, and the gate metal 39 is isolated from the barrier layer 36 by an insulating layer. In the present embodiment, the dielectric layer 38 is a second conductivity type GaN dielectric layer. In the present embodiment, the barrier layer 36 is in full contact with the upper surface of the channel layer 35, wherein the bottom of the third barrier layer of the barrier layer 36 is also in contact with the surface of the middle of the epitaxial layer 33 except the surface covered by the channel layer 35.
A drain metal 31 is provided on the bottom of the first conductive type substrate 33.
The cell structure of the power semiconductor device of the embodiment extends a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on a silicon carbide (SiC) drift region, and generates a high-concentration two-dimensional electron gas at an interface through the polarization effect of a GaN/AlGaN heterojunction, wherein the two-dimensional electron gas (2DEG) refers to a quantum well with degenerate depth of electrons or holes, the quantum well is only 1-2 nm wide, and carriers can move in a two-dimensional plane parallel to the interface and are limited in the well in a direction perpendicular to the interface. HEMTs take advantage of the fact that impurities and electrons in a semiconductor heterostructure can be spatially separated, so that the electrons have a high mobility. In the structure, the current from the source (source) to the drain (drain) can be controlled by changing the voltage of the gate (gate), and the HEMT structure has the advantages of high carrier concentration and high electron mobility. Therefore, a two-dimensional electron gas layer in the HEMT structure is adopted to replace a channel region below a grid electrode in a typical metal-oxide-semiconductor field effect transistor (MOSFET) device, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is adopted to greatly increase the channel carrier mobility, and the on-resistance of the device is reduced. After the device structure of the embodiment is adopted, the NPN latch-up effect of the SiC planar MOSFET can be avoided due to the fact that the on-resistance of the device is reduced. Meanwhile, as the device structure of the embodiment is not provided with the grid oxide layer, the influence of grid oxide failure on the reliability of the power semiconductor device is avoided, and the reliability of the power semiconductor device is improved.
In the power semiconductor device of the embodiment, the bias voltage is simultaneously applied to the gate and the drain, when the voltage applied to the gate is less than or equal to the threshold voltage, the two-dimensional electron gas channel is closed, no obvious current passes through, and when the voltage applied to the gate is greater than the threshold voltage, the two-dimensional electron gas channel DEG is opened, and a larger current can pass through. Under the action of drain voltage, electrons enter the AlGaN/GaN 2DEG channel of the HEMT structure from the ohmic contact metal of the source electrode, and then enter the SiC epitaxial layer and the SiC substrate to reach the drain metal to form a current loop.
The optimization of the embodiment, compared with the first and second embodiments, is that etching is not performed on the surface of the substrate, so that the process steps of substrate etching are reduced, and the process flow is simplified. Compared with the second embodiment, the embodiment does not need to provide a metal layer, can save the process step of forming good ohmic contact, reduces the process difficulty, and also saves the manufacturing cost.
In the power semiconductor device structure of the embodiment, the P-type injection base region and the N-type drift region form a PN junction to bear blocking voltage, and the spaced P-type base regions can effectively shield an electric field for the upper structure, so that the voltage withstanding capability of the device is enhanced.
According to the embodiment, the device structure of the traditional MOSFET is optimized, so that the pitch of the cell structure of the device is reduced, and the yield of the device is improved.
In summary, in the present embodiment, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is arranged, so that the channel carrier mobility is greatly increased, and the on-resistance is reduced; the MOSFET device structure is not provided with the grid oxide layer, so that the influence of grid oxide failure on the reliability of the device is avoided; the second conductive type base region with the appointed junction depth is arranged, so that the high-voltage-resistance LED lamp has higher voltage resistance. Meanwhile, as the groove and the metal layer are not arranged, the process flow of the device is simplified, and the manufacturing cost of the device is further reduced.
Fourth embodiment
This embodiment provides a power semiconductor device comprising a plurality of cell structures of the power semiconductor device as described in any one of the first, second, and third embodiments above.
In the embodiment, the shape of the power semiconductor device cell structure comprises a strip shape, a quadrangle shape, a hexagon shape, an octagon shape, a circle shape, a lattice array shape, or a combination of the above shapes.
Fifth embodiment
Fig. 2 is a schematic sectional structure of a power semiconductor device of embodiment 1;
fig. 3 is a sectional schematic current path of the power semiconductor device of example 1;
fig. 4 is a schematic sectional structure of a power semiconductor device of embodiment 2;
fig. 5 is a schematic sectional structure of a power semiconductor device of embodiment 3;
FIG. 6 is a flow chart illustrating a manufacturing method of the present embodiment;
fig. 7 is a schematic cross-sectional view of the embodiment after S100 is implemented;
fig. 7 is a schematic cross-sectional view of the embodiment after S101 is implemented;
fig. 8 is a schematic cross-sectional view of the embodiment after S102 is implemented;
fig. 9 is a schematic cross-sectional structure diagram after S103 is implemented in this embodiment.
This embodiment mainly explains a manufacturing method of the power semiconductor device structure of the first embodiment, and as shown in fig. 2, the power semiconductor device of the first embodiment includes: a first conductivity type substrate 11, a first conductivity type epitaxial layer 12, a second conductivity type base region 13, a channel layer 14, a barrier layer 15, a source metal 16, a second conductivity type dielectric layer 17, a gate metal 18, and a drain metal 19.
The conductivity type used in each part in this embodiment may be set to be a first conductivity type or a second conductivity type, and the first conductivity type and the second conductivity type are complementary conductivity types.
In this embodiment, the N-type is set to be the first conductivity type, and the P-type is set to be the second conductivity type.
The power semiconductor device includes a MOSFET or an IGBT, and the present embodiment is described with the MOSFET as an example. The substrate material includes semiconductor elements such as silicon or silicon germanium in a single crystal, polycrystalline or amorphous structure, and also includes mixed semiconductor materials such as silicon carbide, gallium nitride, gallium sesquioxide, alloy semiconductors, or combinations thereof, without limitation. The first conductive type substrate in this embodiment is a doped substrate, the substrate in this embodiment is preferably a silicon carbide substrate, and an N-type or P-type silicon carbide substrate can be used, and in this embodiment, the doped N-type substrate is taken as an example, and the N-type substrate has a resistivity in a range of 0.01 Ω · cm to 0.03 Ω · cm and a thickness in a range of 200 μm to 400 μm.
The embodiment provides a manufacturing method of a cellular structure of a power semiconductor device, which comprises the following steps:
s100, a first conductive type epitaxial layer 12 is formed on a surface of the first conductive type substrate 11.
Specifically, a first conductivity type epitaxial layer 12 is formed on the surface of the silicon carbide first conductivity type substrate 11 by an epitaxial process. The material of the first conductive type epitaxial layer 12 includes, but is not limited to, silicon carbide, gallium nitride or gallium sesquioxide, preferably, silicon carbide in this embodiment, and the doping concentration of the first conductive type epitaxial layer 12 is 5e 14-5 e16cm-3。
In the present embodiment, after the step of forming the first conductivity type epitaxial layer 12 on the surface of the first conductivity type substrate 11, the following steps are further included:
photoetching and silicon carbide etching processes are adopted on two sides of the middle of the surface of the epitaxial layer 12, when the alignment mark is formed, etching is carried out on two sides of the middle of the surface of the epitaxial layer 12 to a preset depth, the preset depth is 0.2-0.5 microns, and the section structure after the step is implemented is shown in fig. 7.
S101, implanting ions into the upper surfaces of the two ends of the epitaxial layer 12 by photolithography to form a second conductive type base region 13 at a predetermined junction depth, and the cross-sectional structure after this step is implemented is shown in fig. 8.
Specifically, a required window is formed on the epitaxial layer 12 through a photolithography process, ion implantation is performed at positions corresponding to the upper surfaces of the two ends of the epitaxial layer 12, and second conductive type base regions 13 with preset doping concentrations are respectively formed at preset junction depths of the two ends of the epitaxial layer 12. In this embodiment, the middle surface of the epitaxial layer 12 is higher than the surfaces of the second conductive type base regions 13 at the two ends of the epitaxial layer 12, the preset junction depth of the second conductive type base region 13 is 0.2 μm to 1.0 μm, and the doping concentration of the second conductive type base region 13 is 1e18cm-3～5e19cm-3。
S102, forming a channel layer 14 on the surface of the second conductive type base region 13 by deposition and etching processes, wherein the channel layer 14 is in contact with the middle of the epitaxial layer 12, and the cross-sectional structure after the step is implemented is shown in fig. 9.
Specifically, a channel layer 14 is formed on the surface of the second conductive type base region 13 by deposition and etching processes, wherein the channel layer 14 is further contacted with the middle of the epitaxial layer 12 by covering the side walls on the two sides of the middle of the epitaxial layer 12 and the surface of the middle part of the epitaxial layer 12, in this embodiment, the two sides of the first channel layer covering the side walls on the two sides of the middle of the epitaxial layer 12 are connected to the second channel layer on the surface of the second conductive type base region 13 and the third channel layer on the surface of the middle part of the epitaxial layer 12, wherein the two sides of the first channel layer are connected to the second channel layer and the third channel layer, the first channel layer covers the side walls on the two sides of the middle of the epitaxial layer 12, the second channel layer is disposed on the surface of the second conductive type base region. In this embodiment, the material of the channel layer is GaN, and the thickness of the channel layer is 6nm to 14 nm. The upper surface of the second conductivity type base region 13 is in contact with the second channel layer, and the left surface and the lower surface are in contact with the epitaxial layer 12.
S103, a barrier layer 15 is formed on the surface of the channel layer 14 by deposition and etching processes, and the cross-sectional structure after this step is performed is as shown in fig. 10.
Specifically, the barrier layer 15 is formed on the surface of the channel layer 14 by deposition and etching processes, in this embodiment, two sides of a first barrier layer covered on the first channel layer are connected to a second barrier layer on the surface of the second channel layer and a third barrier layer covered on the surface of the third channel layer, wherein two sides of the first barrier layer are connected to the second barrier layer and the third barrier layer, the first barrier layer is covered on the first channel layer, the second barrier layer is disposed on the surface of the second channel layer, and the third barrier layer is covered on the surface of the third channel layer. In this embodiment, the material of the barrier layer 15 is AlGaN, and the thickness of the barrier layer 15 is 10nm to 20 nm. The first surface of the channel layer 14 is entirely in contact with the barrier layer 15, and a portion of the second surface is in contact with the upper surface of the second conductivity-type base region 13, a portion of the second surface is in contact with the side walls on both sides of the middle portion of the epitaxial layer 12, and a portion of the second surface is in contact with a portion of the surface of the middle portion of the epitaxial layer 12.
S104, forming a dielectric layer 17 on the barrier layer 15 close to the middle part of the epitaxial layer 12 and forming a gate metal 18 on the dielectric layer 17; a source metal 16 is formed over the barrier layer 15 away from the middle of the epitaxial layer 12.
Specifically, a GaN dielectric layer 17 of a second conductivity type is formed above the AlGaN barrier layer 15 near the middle of the epitaxial layer 12 by photolithography, deposition and etching processes; then, forming source metal 16 on the barrier layer 15 far away from the middle part of the epitaxial layer 12 by adopting photoetching, electron beam array method and stripping process, and simultaneously forming good ohmic contact by adopting a rapid thermal annealing process; and forming a gate metal 18 on the second conductive type dielectric layer 17 by adopting photoetching, electron beam array method and stripping process. The source metal 16 and the gate metal 18 are isolated by an insulating layer, the dielectric layer 17 except the bottom is isolated by insulating layers from the barrier layer 15 on other surfaces, and the gate metal 18 is isolated from the barrier layer 15 by an insulating layer. In the present embodiment, the dielectric layer 17 is a second conductivity type GaN dielectric layer. In the present embodiment, the barrier layer 15 is in full contact with the upper surface of the channel layer 14, wherein the bottom of the third barrier layer of the barrier layer 15 is also in contact with the surface of the middle portion of the epitaxial layer 12 except the surface covered by the channel layer 14.
And S105, forming a drain metal 19 at the bottom of the first conduction type substrate.
Specifically, by adopting deposition, laser annealing and metal thickening processes, drain metal 19 is formed on the back surface of the power semiconductor device at the bottom of the first conductive type substrate, and finally the power semiconductor device is manufactured, as shown in fig. 2, the structures such as a passivation dielectric layer and a protective layer are omitted in fig. 2.
The cell structure of the power semiconductor device of the embodiment extends a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on a silicon carbide (SiC) drift region, and generates a high-concentration two-dimensional electron gas at an interface through the polarization effect of a GaN/AlGaN heterojunction, wherein the two-dimensional electron gas (2DEG) refers to a quantum well with degenerate depth of electrons or holes, the quantum well is only 1-2 nm wide, and carriers can move in a two-dimensional plane parallel to the interface and are limited in the well in a direction perpendicular to the interface. HEMTs take advantage of the fact that impurities and electrons in a semiconductor heterostructure can be spatially separated, so that the electrons have a high mobility. In the structure, the current from the source (source) to the drain (drain) can be controlled by changing the voltage of the gate (gate), and the HEMT structure has the advantages of high carrier concentration and high electron mobility. Therefore, a two-dimensional electron gas layer in the HEMT structure is adopted to replace a channel region below a grid electrode in a typical metal-oxide-semiconductor field effect transistor (MOSFET) device, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is adopted to greatly increase the channel carrier mobility, and the on-resistance of the device is reduced. After the device structure of the embodiment is adopted, the NPN latch-up effect of the SiC planar MOSFET can be avoided due to the fact that the on-resistance of the device is reduced. Meanwhile, as the device structure of the embodiment is not provided with the grid oxide layer, the influence of grid oxide failure on the reliability of the power semiconductor device is avoided, and the reliability of the power semiconductor device is improved.
In the power semiconductor device of the embodiment, the bias voltage is simultaneously applied to the gate and the drain, when the voltage applied to the gate is less than or equal to the threshold voltage, the two-dimensional electron gas channel is closed, no obvious current passes through, and when the voltage applied to the gate is greater than the threshold voltage, the two-dimensional electron gas channel DEG is opened, and a larger current can pass through. Under the action of drain voltage, electrons enter the 2DEG channel of AlGaN/GaN from the ohmic contact metal of the source electrode, then enter the SiC epitaxial layer and the SiC substrate to reach the drain metal to form a current loop, and the current path is shown in FIG. 3.
In the power semiconductor device structure of the embodiment, the P-type injection base region and the N-type drift region form a PN junction to bear blocking voltage, and the spaced P-type base regions can effectively shield an electric field for the upper structure, so that the voltage withstanding capability of the device is enhanced.
According to the embodiment, the device structure of the traditional MOSFET is optimized, so that the pitch of the cell structure of the device is reduced, and the yield of the device is improved.
Further, based on the manufacturing method of this embodiment, a metal layer is formed above the middle surface of the epitaxial layer, and the metal layer is in contact with both the GaN channel layer and the AlGaN barrier layer, so that the power semiconductor device shown in fig. 4 is formed. Under the action of drain voltage, electrons enter the AlGaN/GaN 2DEG channel of the HEMT structure from the ohmic contact metal of the source electrode, then enter the metal layer, and then enter the SiC epitaxial layer and the SiC substrate to reach the drain metal to form a current loop. By arranging the metal layer, the complexity of surface etching patterns can be simplified, the overall process difficulty of the device is reduced, and the cost is reduced.
Further, on the basis of this embodiment, a power semiconductor device as shown in fig. 5 is formed without forming a trench structure on the surface of the substrate. Because no groove is formed, the process steps of etching the substrate are reduced, and the process flow is simplified. The manufacturing method does not need to arrange a metal layer, can save the process step of forming good ohmic contact, reduces the process difficulty and saves the manufacturing cost.
In summary, in the present embodiment, the two-dimensional electron gas transmission of the AlGaN/GaN heterojunction is arranged, so that the channel carrier mobility is greatly increased, and the on-resistance is reduced; according to the manufacturing method of the MOSFET device, the grid oxide layer is not arranged, so that the influence of grid oxide failure on the reliability of the device is avoided; the second conductive type base region with the appointed junction depth is arranged, so that the high-voltage-resistance LED lamp has higher voltage resistance.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as disclosed, and that the scope of the invention is not to be limited to the particular embodiments disclosed herein but is to be accorded the full scope of the claims.
Claims (10)
1. A cell structure of a power semiconductor device, comprising:
a first conductive type epitaxial layer on a surface of the first conductive type substrate;
the second conductive type base region is positioned at two sides of the middle part of the epitaxial layer and is preset with junction depth;
the channel layer is positioned on the surface of the second conduction type base region and is in contact with the middle of the epitaxial layer;
a barrier layer over a surface of the channel layer;
a dielectric layer over the barrier layer near the middle of the epitaxial layer and a gate metal over the dielectric layer;
a source metal located on the barrier layer away from the middle of the epitaxial layer, wherein the source metal is isolated from the gate metal by an insulating layer;
and the drain metal is positioned at the bottom of the first conduction type substrate.
2. The cell structure of a power semiconductor device according to claim 1,
the middle surface of the epitaxial layer is higher than the surfaces of the second conductive type base regions at the two ends of the epitaxial layer.
3. The cell structure of a power semiconductor device according to claim 2,
the channel layer comprises a first channel layer, a second channel layer and a third channel layer, wherein two sides of the first channel layer are connected with the second channel layer and the third channel layer, the first channel layer covers two side walls of the middle part of the epitaxial layer, the second channel layer covers the surface of the second conduction type base region, and the third channel layer covers part of the surface of the middle part of the epitaxial layer;
the barrier layers comprise a first barrier layer, a second barrier layer and a third barrier layer, wherein the second barrier layer and the third barrier layer are connected to two sides of the first barrier layer, the first barrier layer covers the surface of the first channel layer, the second barrier layer covers the surface of the second channel layer, and the third barrier layer covers the surface of the third channel layer.
4. The cell structure of a power semiconductor device according to claim 2,
a metal layer is arranged on the middle surface of the epitaxial layer;
the channel layer comprises a first channel layer and a second channel layer, two sides of the first channel layer are connected with the second channel layer and the metal layer, the first channel layer covers two side walls of the middle part of the epitaxial layer, and the second channel layer covers the surface of the second conduction type base region;
the barrier layers comprise the first barrier layer and the second barrier layer, two sides of the first barrier layer are connected with the second barrier layer and the metal layer, the first barrier layer covers the surface of the first channel layer, and the second barrier layer covers the surface of the second channel layer.
5. The cell structure of a power semiconductor device according to claim 1,
the middle surface of the epitaxial layer is flush with the surfaces of the second conduction type base regions at two ends of the epitaxial layer;
the channel layer is positioned on the surface of the second conduction type base region and is in contact with part of the surface of the middle part of the epitaxial layer;
the barrier layer is positioned above the surface of the channel layer and is in contact with a part of the surface of the middle part of the epitaxial layer.
6. The cell structure of a power semiconductor device according to claims 1 to 5,
the material of the channel layer is GaN;
the barrier layer is made of AlGaN;
the preset junction depth of the second conductive type base region is 0.2-1.5 microns;
the doping concentration of the base region of the second conduction type is 1e18cm-3～5e19cm-3；
The thickness of the channel layer is 6 nm-14 nm;
the thickness of the barrier layer is 10 nm-20 nm.
7. A power semiconductor device is characterized in that,
cell structure comprising several power semiconductor devices according to any of claims 1 to 6.
8. The power semiconductor device of claim 7,
the shapes of the cellular structures comprise strips, quadrangles, hexagons, octagons, circles, lattice arrays or combinations of the above shapes.
9. A method for manufacturing a cellular structure of a power semiconductor device is characterized by comprising the following steps:
forming a first conductive type epitaxial layer on a surface of a first conductive type substrate;
implanting ions into the upper surfaces of the two ends of the epitaxial layer through photoetching to form a second conductive type base region at a preset junction depth;
forming a channel layer on the surface of the second conductive type base region through deposition and etching processes, wherein the channel layer is in contact with the middle of the epitaxial layer;
forming a barrier layer on the surface of the channel layer by deposition and etching processes;
forming a dielectric layer over the barrier layer near the middle of the epitaxial layer and a gate metal over the dielectric layer;
forming a source metal over the barrier layer away from a middle portion of the epitaxial layer;
and forming drain metal at the bottom of the first conduction type substrate.
10. The method of manufacturing according to claim 9, further comprising, after the step of forming a first conductivity type epitaxial layer on the first conductivity type substrate surface, the steps of:
and etching the two sides of the middle part of the surface of the epitaxial layer to a preset depth, wherein the preset depth is 0.2-0.5 mu m.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004281950A (en) * | 2003-03-19 | 2004-10-07 | Hitachi Cable Ltd | Hetero-junction bipolar transistor |
| US20050224838A1 (en) * | 2004-04-13 | 2005-10-13 | Nissan Motor Co., Ltd. | Semiconductor device with heterojunction |
| US20080315211A1 (en) * | 2007-06-21 | 2008-12-25 | Denso Corporation | SIC semiconductor device with BPSG insulation film and method for manufacturing the same |
| US20150091055A1 (en) * | 2013-10-01 | 2015-04-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004281950A (en) * | 2003-03-19 | 2004-10-07 | Hitachi Cable Ltd | Hetero-junction bipolar transistor |
| US20050224838A1 (en) * | 2004-04-13 | 2005-10-13 | Nissan Motor Co., Ltd. | Semiconductor device with heterojunction |
| US20080315211A1 (en) * | 2007-06-21 | 2008-12-25 | Denso Corporation | SIC semiconductor device with BPSG insulation film and method for manufacturing the same |
| US20150091055A1 (en) * | 2013-10-01 | 2015-04-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
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