CN112151524A - Packaging structure and packaging method of fan-out type fingerprint identification chip - Google Patents

Packaging structure and packaging method of fan-out type fingerprint identification chip Download PDF

Info

Publication number
CN112151524A
CN112151524A CN201910571499.4A CN201910571499A CN112151524A CN 112151524 A CN112151524 A CN 112151524A CN 201910571499 A CN201910571499 A CN 201910571499A CN 112151524 A CN112151524 A CN 112151524A
Authority
CN
China
Prior art keywords
layer
chip
fingerprint
packaging
fan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910571499.4A
Other languages
Chinese (zh)
Inventor
吕娇
陈彦亨
林正忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SJ Semiconductor Jiangyin Corp
Original Assignee
SJ Semiconductor Jiangyin Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SJ Semiconductor Jiangyin Corp filed Critical SJ Semiconductor Jiangyin Corp
Priority to CN201910571499.4A priority Critical patent/CN112151524A/en
Publication of CN112151524A publication Critical patent/CN112151524A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02379—Fan-out arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the wire connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Human Computer Interaction (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The invention provides a packaging structure and a packaging method of a fan-out fingerprint identification chip, wherein the structure comprises the following steps: a circuit layer; the first surface of the fingerprint processing chip is provided with a rewiring layer, and the second surface of the fingerprint chip is adhered to the first surface of the circuit layer; the fingerprint acquisition chip is electrically connected to the second surface of the rewiring layer; the metal connecting wire is connected to the second surface of the rewiring layer and the first surface of the circuit layer; the packaging layer is covered on the fingerprint processing chip and the fingerprint acquisition chip; and the metal bump is formed in the opening in the second surface dielectric layer of the circuit layer. The fan-out type packaging fingerprint identification chip is adopted, the fingerprint acquisition chip and the fingerprint processing chip can be integrated in the same packaging structure and are vertically stacked, compared with the existing packaging of other fingerprint identification chips, the fan-out type packaging fingerprint identification chip has the advantages of low cost, small thickness and high yield, and the response speed of the packaging structure can be effectively improved.

Description

Packaging structure and packaging method of fan-out type fingerprint identification chip
Technical Field
The invention belongs to the field of semiconductor packaging, and particularly relates to a packaging structure and a packaging method of a fan-out type fingerprint identification chip.
Background
With the increasing functionality, performance and integration level of integrated circuits, and the emergence of new types of integrated circuits, packaging technology plays an increasingly important role in integrated circuit products, and accounts for an increasing proportion of the value of the entire electronic system. Meanwhile, as the feature size of the integrated circuit reaches the nanometer level, the transistor is developed to a higher density and a higher clock frequency, and the package is also developed to a higher density.
Because the fan-out wafer level package (fowlp) technology has the advantages of miniaturization, low cost, high integration, better performance, and higher energy efficiency, the fan-out wafer level package (fowlp) technology has become an important packaging method for high-demand electronic devices such as mobile/wireless networks, and is one of the most promising packaging technologies currently.
Fingerprint identification technology is the most mature and cheap biometric identification technology at present. At present, the technology of fingerprint identification is most widely applied, the figure of the fingerprint identification technology can be seen in an access control and attendance system, and more fingerprint identification applications are available in the market: such as notebook computer, mobile phone, automobile, bank payment can all apply the technology of fingerprint identification.
The existing packaging method of the fingerprint identification chip is to weld the fingerprint acquisition chip and the fingerprint processing chip on the PCB respectively, and the packaging mode needs to occupy larger packaging area, the thickness of the PCB circuit board is larger, and the packaging circuit is longer, which can cause the defects of large volume, slow response speed and the like of the packaging structure.
Based on the above, it is necessary to provide a package structure and a package method of a fingerprint identification chip with low cost, low volume and high response speed.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a package structure and a package method for a fan-out type fingerprint identification chip, which are used to solve the problems of high package cost, large size, slow response speed, etc. of the fingerprint identification chip in the prior art.
To achieve the above and other related objects, the present invention provides a package structure of a fan-out type fingerprint identification chip, the package structure comprising: the circuit board comprises a circuit layer and a circuit board, wherein the circuit layer comprises a first surface and a second surface which are electrically connected, the second surface of the circuit layer is provided with a dielectric layer, and an opening is formed in the dielectric layer; the first surface of the fingerprint processing chip is provided with a rewiring layer, the rewiring layer is used for electrically leading out the fingerprint processing chip, and the second surface of the fingerprint chip is adhered to the first surface of the circuit layer; the fingerprint acquisition chip is electrically connected to the second surface of the rewiring layer; the metal connecting wire is connected to the second surface of the rewiring layer and the first surface of the circuit layer; the packaging layer covers the fingerprint processing chip and the fingerprint acquisition chip; and the metal bump is formed in the opening.
Optionally, the fingerprint acquisition chip and the fingerprint processing chip are vertically stacked.
Optionally, the material of the encapsulation layer includes one of polyimide, silicone, and epoxy.
Optionally, the fingerprint acquisition chip is exposed on the top surface of the encapsulation layer.
Optionally, the metal bump comprises one of a tin solder, a silver solder, and a gold-tin alloy solder.
Optionally, the metal connection line includes one of a gold line and a silver line.
The invention also provides a packaging method of the fan-out type fingerprint identification chip, which comprises the following steps: 1) providing a fingerprint processing chip wafer, and forming a rewiring layer on the fingerprint processing chip wafer, wherein the first surface of the rewiring layer is connected with the fingerprint processing chip wafer, and the rewiring layer is used for electrically leading out a fingerprint processing chip; 2) cutting the fingerprint processing chip wafer and the rewiring layer to obtain an independent fingerprint processing chip; 3) providing a supporting substrate, forming a separation layer on the supporting substrate, forming the circuit layer on the separation layer, adhering the fingerprint processing chip to the first surface of the circuit layer, and enabling the rewiring layer to face away from the circuit layer; 4) providing a fingerprint acquisition chip, electrically connecting the fingerprint acquisition chip to the second surface of the rewiring layer, wherein the fingerprint acquisition chip and the fingerprint processing chip are vertically stacked; 5) connecting the second surface of the rewiring layer and the first surface of the circuit layer by using a metal connecting wire; 6) packaging the fingerprint processing chip and the fingerprint acquisition chip by using a packaging layer; 7) stripping the supporting substrate and the circuit layer based on the separation layer to expose the second surface of the circuit layer, and forming a metal bump on the second surface of the circuit layer; 8) and cutting the circuit layer to obtain an independent fan-out type fingerprint identification chip packaging structure.
Optionally, the support base comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.
Optionally, the separation layer comprises a light-to-heat conversion layer; and 7) irradiating the photothermal conversion layer with laser light to separate the photothermal conversion layer from the encapsulation layer and the supporting substrate, thereby peeling the encapsulation layer and the supporting substrate.
Optionally, the second surface of the circuit layer in step 3) has a dielectric layer, and step 7) forms an opening in the dielectric layer before forming the metal bump in the opening.
Optionally, the method for packaging the fingerprint processing chip and the fingerprint acquisition chip by using the packaging layer includes one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, and the material of the packaging layer includes one of polyimide, silica gel and epoxy resin.
Optionally, in step 6), after the fingerprint processing chip and the fingerprint acquisition chip are packaged by using a packaging layer, the fingerprint acquisition chip is exposed on the top surface of the packaging layer.
Optionally, in step 5), the metal connection line is formed between the second surface of the redistribution layer and the first surface of the circuit layer by using a wire bonding process.
Optionally, the metal connection line includes one of a gold line and a silver line.
Optionally, the metal bump comprises one of a tin solder, a silver solder, and a gold-tin alloy solder.
As described above, the packaging structure and the packaging method of the fan-out fingerprint identification chip of the present invention have the following beneficial effects:
1) the Fan-out type packaging (Fan out) fingerprint identification chip is adopted, the fingerprint acquisition chip and the fingerprint processing chip can be integrated in the same packaging structure, and the fingerprint acquisition chip and the fingerprint processing chip are vertically stacked.
2) The fingerprint acquisition chip and the fingerprint processing chip are vertically stacked, so that the response speed of the packaging structure can be effectively improved.
3) The invention adopts the supporting substrate for supporting in the packaging process, thereby effectively ensuring the process stability and improving the packaging yield.
Drawings
Fig. 1 to 14 are schematic structural diagrams of steps of a packaging method of a fan-out fingerprint identification chip according to the present invention, wherein fig. 14 is a schematic structural diagram of a packaging structure of the fan-out fingerprint identification chip.
Description of the element reference numerals
201 fingerprint processing chip wafer
202 rewiring layer
20 fingerprint processing chip
203 film
301 line layer
302 dielectric layer
303 open pore
304 separating layer
305 support substrate
401 fingerprint collecting chip
402 metal connection line
403 encapsulation layer
501 metal bump
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 14, the present embodiment provides a packaging method of a fan-out fingerprint identification chip, where the packaging method includes the following steps:
as shown in fig. 1-2, step 1) is firstly performed to provide a fingerprint processing chip wafer 201, a redistribution layer 202 is formed on the fingerprint processing chip wafer 201, a first surface of the redistribution layer 202 is connected to the fingerprint processing chip wafer 201, the redistribution layer 202 is used for electrical leading-out of the fingerprint processing chip 20, and the fingerprint processing chip 20 is used for performing feature extraction and feature ratio peer-to-peer processing on a fingerprint signal acquired by a fingerprint acquisition chip 401 to realize a fingerprint identification function.
The fingerprint processing chip wafer 201 is provided with a plurality of fingerprint processing chips 20 arranged in an array, each fingerprint processing chip 20 is provided with a corresponding electrode, a seed layer such as a Cu/Ti laminated layer is formed on the fingerprint processing chip wafer 201 firstly, then the seed layer is etched to form a graphical seed layer, the graphical seed layer is connected with the electrodes of the fingerprint processing chip 20, and then a rewiring layer 202 is formed on the fingerprint processing chip wafer 201 based on the graphical seed layer. The redistribution layer 202 may include a plurality of dielectric layers and a plurality of metal wiring layers arranged according to a pattern requirement, and two adjacent metal wiring layers are connected by a conductive plug. The dielectric layer can be formed by coating or deposition, and the material of the dielectric layer can be one or the combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the dielectric layer may be made of PI (polyimide), so as to further reduce the process difficulty and the process cost. The metal wiring layer can be formed by adopting a method such as electroplating or sputtering and an etching process, and can also be formed by adopting a metal stripping process, and the material of the metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium. In this embodiment, the metal wiring layer is made of copper.
As shown in fig. 3 to 5, step 2) is then performed to cut the fingerprint processing chip wafer 201 and the redistribution layer 202, so as to obtain the individual fingerprint processing chips 20.
Specifically, the back surface of the fingerprint processing chip wafer 201 is adhered to an adhesive film 203, such as a blue film, and then the fingerprint processing chip wafer 201 is cut by a mechanical cutter or a laser cutter, so as to obtain the independent fingerprint processing chip 20.
As shown in fig. 6 to 8, step 3) is performed next, a circuit layer 301 is provided, the fingerprint processing chip 20 is adhered to a first surface of the circuit layer 301, and the rewiring layer 202 faces away from the circuit layer 301.
For example, the step 3) of providing the line layer 301 includes the steps of:
3-1) providing a supporting substrate 305, and forming a separation layer 304 on the supporting substrate 305, as shown in fig. 6.
The support base 305 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate, for example. In this embodiment, the support base 305 is a glass substrate, which has a low cost, is easy to form the separation layer 304 on the surface thereof, and can reduce the difficulty of the subsequent stripping process. The separation layer 304 includes a light-to-heat conversion layer, and is formed on the support substrate 305 by a spin coating process and then cured by a curing process. The light-heat conversion Layer (LTHC) has stable performance and smooth surface, is beneficial to obtaining flatness subsequently, and has lower stripping difficulty in the subsequent stripping process.
3-2) forming the circuit layer 301 on the separation layer 304, as shown in fig. 7. The circuit layer 301 may include a plurality of dielectric layers and a plurality of metal wiring layers arranged according to a pattern requirement, and two adjacent metal wiring layers are connected through a conductive plug, wherein the second surface of the circuit layer is the dielectric layer 302, and the dielectric layer 302 on the second surface of the circuit layer can effectively protect metal at the bottom of the circuit layer, thereby improving stability of the circuit layer. The dielectric layer can be formed by coating or deposition, and the material of the dielectric layer can be one or the combination of more than two of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorosilicate glass and fluorine-containing glass. In this embodiment, the dielectric layer may be made of PI (polyimide), so as to further reduce the process difficulty and the process cost. The metal wiring layer can be formed by adopting a method such as electroplating or sputtering and an etching process, and can also be formed by adopting a metal stripping process, and the material of the metal wiring layer comprises one or the combination of more than two of copper, aluminum, nickel, gold, silver and titanium. In this embodiment, the metal wiring layer is made of copper.
After the circuit layer 301 is formed, the fingerprint processing chip 20 may be adhered to the first side of the circuit layer 301 by using an adhesive glue, the side of the fingerprint processing chip 20 having the redistribution layer 202 is placed upward, i.e. away from the circuit layer 301, and the surface of the redistribution layer 202 is exposed with a metal wiring layer, as shown in fig. 8.
As shown in fig. 9, step 4) is performed to provide a fingerprint acquisition chip 401, and the fingerprint acquisition chip 401 is electrically connected to the second surface of the redistribution layer 202, wherein the fingerprint acquisition chip 401 and the fingerprint processing chip 20 are vertically stacked. The fingerprint acquisition chip 401 is used for adopting human fingerprints and transmitting acquisition signals to the fingerprint processing chip 20 for processing.
For example, a soldering process may be used to bond the fingerprint acquisition chip 401 to the second surface of the redistribution layer 202, and the fingerprint acquisition chip 401 and the fingerprint processing chip 20 are vertically stacked.
As shown in fig. 10, step 5) is performed to connect the second surface of the redistribution layer 202 and the first surface of the circuit layer 301 by using metal wires 402.
For example, a wire bonding process may be used to form the metal connection 402 between the second surface of the redistribution layer 202 and the first surface of the circuit layer 301. The metal line 402 may be one of a gold line and a silver line.
As shown in fig. 11, step 6) is performed next, and the fingerprint processing chip 20 and the fingerprint acquisition chip 401 are packaged by using a packaging layer 403.
For example, the method for encapsulating the fingerprint processing chip 20 and the fingerprint acquisition chip 401 by the encapsulation layer 403 includes one of compression molding, transfer molding, liquid encapsulation molding, vacuum lamination and spin coating, and the material of the encapsulation layer 403 includes one of polyimide, silicone and epoxy resin. After the fingerprint processing chip 20 and the fingerprint acquisition chip 401 are packaged by the packaging layer 403, the fingerprint acquisition chip 401 is exposed on the top surface of the packaging layer 403, so that the acquisition precision of the fingerprint acquisition chip 401 is improved.
As shown in fig. 12 to 14, step 7) is performed to peel off the supporting substrate 305 and the circuit layer 301 based on the separation layer 304 to expose the second surface of the circuit layer 301, form an opening 303 in the dielectric layer 302 on the second surface of the circuit layer 301, and form a metal bump 501 in the opening 303 on the second surface of the circuit layer 301.
In the present embodiment, the photothermal conversion layer is irradiated with laser light to separate the photothermal conversion layer from the encapsulation layer 403 and the supporting substrate 305, thereby peeling the encapsulation layer 403 and the supporting substrate 305.
The metal bump 501 may be one of a tin solder, a silver solder, and a gold-tin alloy solder.
And finally, carrying out step 8), cutting the circuit layer 301 to obtain an independent fan-out type fingerprint identification chip packaging structure.
As shown in fig. 14, this embodiment further provides a package structure of a fan-out fingerprint identification chip, where the package structure includes: the circuit layer 301 comprises a first surface and a second surface which are electrically connected, the second surface of the circuit layer 301 is provided with a dielectric layer 302, and an opening 303 is formed in the dielectric layer; the fingerprint processing chip 20 is provided with a rewiring layer 202 on a first surface of the fingerprint processing chip 20, the rewiring layer 202 is used for electrically leading out the fingerprint processing chip 20, and a second surface of the fingerprint chip is adhered to the first surface of the circuit layer 301; a fingerprint acquisition chip 401, wherein the fingerprint acquisition chip 401 is electrically connected to the second surface of the redistribution layer 202; a metal line 402 connected to the second surface of the redistribution layer 202 and the first surface of the circuit layer 301; the packaging layer 403 covers the fingerprint processing chip 20 and the fingerprint acquisition chip 401; the metal bump 501 is formed in the opening 303 of the second dielectric layer 302 of the circuit layer 301.
Optionally, the fingerprint acquisition chip 401 and the fingerprint processing chip 20 are vertically stacked. The Fan-out type packaging (Fan out) fingerprint identification chip is adopted, the fingerprint acquisition chip 401 and the fingerprint processing chip 20 can be integrated in the same packaging structure, and the fingerprint acquisition chip 401 and the fingerprint processing chip 20 are vertically stacked.
The material of the encapsulation layer 403 includes one of polyimide, silicone, and epoxy resin. The metal bump 501 includes one of a tin solder, a silver solder, and a gold-tin alloy solder. The metal connection 402 includes one of a gold wire and a silver wire.
The fingerprint acquisition chip 401 is exposed on the top surface of the encapsulation layer 403, so as to improve the acquisition precision of the fingerprint acquisition chip 401.
As described above, the packaging structure and the packaging method of the fan-out fingerprint identification chip of the present invention have the following beneficial effects:
1) the Fan-out type packaging (Fan out) fingerprint identification chip is adopted, the fingerprint acquisition chip and the fingerprint processing chip can be integrated in the same packaging structure, and the fingerprint acquisition chip and the fingerprint processing chip are vertically stacked.
2) The fingerprint acquisition chip and the fingerprint processing chip are vertically stacked, so that the response speed of the packaging structure can be effectively improved.
3) In the packaging process, the supporting substrate 305 is adopted for supporting, so that the process stability can be effectively ensured, and the packaging yield is improved.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (15)

1. A packaging structure of fan-out fingerprint identification chip, characterized in that, packaging structure includes:
the circuit board comprises a circuit layer and a circuit board, wherein the circuit layer comprises a first surface and a second surface which are electrically connected, the second surface of the circuit layer is provided with a dielectric layer, and an opening is formed in the dielectric layer;
the first surface of the fingerprint processing chip is provided with a rewiring layer, the rewiring layer is used for electrically leading out the fingerprint processing chip, and the second surface of the fingerprint chip is adhered to the first surface of the circuit layer;
the fingerprint acquisition chip is electrically connected to the second surface of the rewiring layer;
the metal connecting wire is connected to the second surface of the rewiring layer and the first surface of the circuit layer;
the packaging layer covers the fingerprint processing chip and the fingerprint acquisition chip;
and the metal bump is formed in the opening.
2. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the fingerprint acquisition chip reaches the fingerprint processing chip is for piling up the setting perpendicularly.
3. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the material of the packaging layer comprises one of polyimide, silica gel and epoxy resin.
4. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the fingerprint acquisition chip is exposed on the top surface of the packaging layer.
5. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the metal bump comprises one of tin solder, silver solder and gold-tin alloy solder.
6. The package structure of the fan-out fingerprint identification chip of claim 1, wherein: the metal connecting wire comprises one of a gold wire and a silver wire.
7. A packaging method of a fan-out fingerprint identification chip is characterized by comprising the following steps:
1) providing a fingerprint processing chip wafer, and forming a rewiring layer on the fingerprint processing chip wafer, wherein the first surface of the rewiring layer is connected with the fingerprint processing chip wafer, and the rewiring layer is used for electrically leading out a fingerprint processing chip;
2) cutting the fingerprint processing chip wafer and the rewiring layer to obtain an independent fingerprint processing chip;
3) providing a supporting substrate, forming a separation layer on the supporting substrate, forming a circuit layer on the separation layer, adhering the fingerprint processing chip to the first surface of the circuit layer, and enabling the rewiring layer to face away from the circuit layer;
4) providing a fingerprint acquisition chip, electrically connecting the fingerprint acquisition chip to the second surface of the rewiring layer, wherein the fingerprint acquisition chip and the fingerprint processing chip are vertically stacked;
5) connecting the second surface of the rewiring layer and the first surface of the circuit layer by using a metal connecting wire;
6) packaging the fingerprint processing chip and the fingerprint acquisition chip by using a packaging layer;
7) stripping the supporting substrate and the circuit layer based on the separation layer to expose the second surface of the circuit layer, and forming a metal bump on the second surface of the circuit layer;
8) and cutting the circuit layer to obtain an independent fan-out type fingerprint identification chip packaging structure.
8. The packaging method of the fan-out fingerprint identification chip of claim 7, wherein: the support base includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate, and a ceramic substrate.
9. The packaging method of the fan-out fingerprint identification chip of claim 7, wherein:
the separation layer includes a light-to-heat conversion layer;
and 7) irradiating the photothermal conversion layer with laser light to separate the photothermal conversion layer from the encapsulation layer and the supporting substrate, thereby peeling the encapsulation layer and the supporting substrate.
10. The packaging method of the fingerprint identification chip of claim 7, wherein: and step 3) the connecting wiring layer comprises a dielectric layer and a connecting metal layer sunk into the dielectric layer, and step 7) an opening is formed in the dielectric layer, and then the metal bump is formed in the opening.
11. The packaging method of the fan-out fingerprint identification chip of claim 7, wherein: the method for packaging the fingerprint processing chip and the fingerprint acquisition chip by adopting the packaging layer comprises one of compression molding, transfer molding, liquid seal molding, vacuum lamination and spin coating, and the material of the packaging layer comprises one of polyimide, silica gel and epoxy resin.
12. The packaging method of the fan-out fingerprint identification chip of claim 7, wherein: and 6) after the fingerprint processing chip and the fingerprint acquisition chip are packaged by a packaging layer, the fingerprint acquisition chip is exposed on the top surface of the packaging layer.
13. The packaging method of the fan-out fingerprint identification chip of claim 7, wherein: and 5) forming the metal connecting line between the second surface of the rewiring layer and the first surface of the circuit layer by adopting a wire bonding process.
14. The packaging method of the fan-out fingerprint identification chip of claim 13, wherein: the metal connecting wire comprises one of a gold wire and a silver wire.
15. The packaging method of the fan-out fingerprint identification chip of claim 7, wherein: the metal bump comprises one of tin solder, silver solder and gold-tin alloy solder.
CN201910571499.4A 2019-06-28 2019-06-28 Packaging structure and packaging method of fan-out type fingerprint identification chip Pending CN112151524A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910571499.4A CN112151524A (en) 2019-06-28 2019-06-28 Packaging structure and packaging method of fan-out type fingerprint identification chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910571499.4A CN112151524A (en) 2019-06-28 2019-06-28 Packaging structure and packaging method of fan-out type fingerprint identification chip

Publications (1)

Publication Number Publication Date
CN112151524A true CN112151524A (en) 2020-12-29

Family

ID=73869035

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910571499.4A Pending CN112151524A (en) 2019-06-28 2019-06-28 Packaging structure and packaging method of fan-out type fingerprint identification chip

Country Status (1)

Country Link
CN (1) CN112151524A (en)

Similar Documents

Publication Publication Date Title
CN110277356B (en) Packaging structure and packaging method of antenna feeder
CN107146779B (en) Packaging structure and packaging method of fingerprint identification chip
CN111370385A (en) Fan-out type system-in-package structure and manufacturing method thereof
CN108336494B (en) Antenna packaging structure and packaging method
CN111370387A (en) Fan-out type system-in-package structure and manufacturing method thereof
CN111370386A (en) Fan-out type system-in-package structure and manufacturing method thereof
CN112289743A (en) Wafer system level fan-out package structure and manufacturing method thereof
CN212084995U (en) Wafer level package structure
CN212392240U (en) Fan-out type packaging structure
CN112289742A (en) Wafer system level three-dimensional fan-out type packaging structure and manufacturing method thereof
CN209880614U (en) Packaging structure of fan-out type fingerprint identification chip
CN114188226A (en) Fan-out type packaging structure and packaging method
CN209843707U (en) Packaging structure of fan-out type fingerprint identification chip
CN112151394A (en) Packaging structure and packaging method of three-dimensional fan-out type fingerprint identification chip
CN112151395A (en) Packaging structure and packaging method of three-dimensional fan-out type fingerprint identification chip
CN212303700U (en) System-in-package structure of LED chip
CN209880615U (en) Packaging structure of fan-out type fingerprint identification chip
CN211480019U (en) Fan-out type system-in-package structure
CN209880545U (en) Packaging structure of three-dimensional fan-out type fingerprint identification chip
CN209880546U (en) Packaging structure of three-dimensional fan-out type fingerprint identification chip
CN210692485U (en) Antenna packaging structure
CN210692484U (en) Antenna packaging structure
CN209804638U (en) Fan-out type antenna packaging structure
CN110060983B (en) Antenna packaging structure and packaging method
CN112151524A (en) Packaging structure and packaging method of fan-out type fingerprint identification chip

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province (place of business: No.9 Dongsheng West Road, Jiangyin City)

Applicant after: Shenghejing micro semiconductor (Jiangyin) Co.,Ltd.

Address before: No.78 Changshan Avenue, Jiangyin City, Wuxi City, Jiangsu Province

Applicant before: SJ Semiconductor (Jiangyin) Corp.

CB02 Change of applicant information