CN112134572B

CN112134572B - LDPC decoding method, LDPC decoder, chip and device

Info

Publication number: CN112134572B
Application number: CN202011022749.8A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-09-25
Filing date: 2020-09-25
Publication date: 2024-04-16
Anticipated expiration: 2040-09-25
Also published as: CN112134572A

Abstract

The embodiment of the application discloses an LDPC decoding method, an LDPC decoder, a chip and equipment, and belongs to the technical field of chips. The method comprises the following steps: acquiring an LDPC (low density parity check) base matrix corresponding to a code block, wherein the code block is positioned in a first memory; reading data from a first memory according to an ith indication row in the LDPC base matrix, and performing decoding calculation on the read data to obtain ith calculation data; and in response to the fact that the (i+1) th indication row and the valid indication bit in the (i) th indication row have intersections, the intersection data in the (i) th calculation data are reserved in the second memory, and data except the intersection data are written back to the first memory, wherein the intersection data are data corresponding to the intersection valid indication bit in the (i) th calculation data. In the embodiment of the application, repeated writing and reading of data corresponding to the intersection valid indication bits are avoided, and then the decoding efficiency of the LDPC decoder is improved.

Description

LDPC decoding method, LDPC decoder, chip and device

Technical Field

The embodiment of the application relates to the technical field of chips, in particular to an LDPC decoding method, an LDPC decoder, a chip and equipment.

Background

The Low-density Parity-check (LDPC) is a linear block code with a sparse check matrix, has the characteristics of Low decoding complexity, parallel decoding, decoding error detection and the like, and is widely applied to the fields of channel coding and the like.

In the related art, when decoding a code block, a serial processing mode is adopted, data of the code block is processed through each indicating line in the LDPC base matrix, and after all the indicating lines are processed, parity check and cyclic redundancy check (Cyclic Redundancy Check, CRC) check is performed, so that whether the next iteration is needed is determined according to a check result.

Disclosure of Invention

The embodiment of the application provides an LDPC decoding method, an LDPC decoder, a chip and equipment. The technical scheme comprises the following steps:

in one aspect, an embodiment of the present application provides an LDPC decoding method, where the method is used in an LDPC decoder, the method includes:

acquiring an LDPC (low density parity check) base matrix corresponding to a code block, wherein the code block is positioned in a first memory;

reading data from the first memory according to an ith indication row in the LDPC base matrix, and performing decoding calculation on the read data to obtain ith calculation data, wherein i is a positive integer, and the data read from the first memory is written into a second memory;

and in response to the fact that the (i+1) th indication row and the valid indication bit in the (i) th indication row have intersection, retaining intersection data in the (i) th calculation data in the second memory, and writing data except the intersection data back to the first memory, wherein the intersection data is data corresponding to the intersection valid indication bit in the (i) th calculation data.

In another aspect, embodiments of the present application provide an LDPC decoder, the LDPC decoder including: the logic operation unit is respectively connected with the second memory and the first memory;

the logic operation unit is used for acquiring an LDPC base matrix corresponding to a code block, and the code block is positioned in the first memory;

the logic operation unit is used for reading data from the first memory according to an i-th indication row in the LDPC base matrix, and performing decoding calculation on the read data to obtain i-th calculation data, wherein i is a positive integer, and the data read from the first memory is written into the second memory;

the logic operation unit is configured to, when an i+1 indication line and a valid indication bit in the i indication line have an intersection, keep intersection data in the i calculation data in the second memory, and write data other than the intersection data back to the first memory, where the intersection data is data corresponding to the intersection valid indication bit in the i calculation data.

In another aspect, an embodiment of the present application provides a communication chip, where the LDPC decoder described in the above aspect is disposed.

In another aspect, an embodiment of the present application provides a communication device, where the communication device includes a processor, a memory, and a transceiver, where the processor is connected to the transceiver and the memory, respectively;

the processor comprises a communication chip as described in the above aspect.

The technical scheme provided by the embodiment of the application at least comprises the following beneficial effects:

in the embodiment of the application, based on the characteristic that the effective indication bits exist between the adjacent indication lines in the LDPC base matrix, the LDPC carries out decoding calculation on the code block data based on the current indication line in the base matrix, after calculation data are obtained, data corresponding to the effective indication bits of the intersection between the next indication lines in the calculation data are reserved in the second memory and used for decoding calculation of the next indication lines, so that repeated writing and reading of the data corresponding to the effective indication bits of the intersection are avoided, and further the decoding efficiency of the LDPC decoder is improved.

Drawings

FIG. 1 is a schematic diagram of an LDPC base matrix shown in an exemplary embodiment;

FIG. 2 is a schematic diagram of a decoding process of an LDPC decoder;

FIG. 3 is a schematic diagram illustrating a decoding process of an LDPC decoder according to the related art;

FIG. 4 illustrates a method flow diagram of an LDPC decoding method provided by an exemplary embodiment of the present application;

FIG. 5 illustrates a method flow diagram of an LDPC decoding method provided by another exemplary embodiment of the present application;

FIG. 6 is a schematic diagram illustrating an implementation of the LDPC decoding method shown in FIG. 5;

FIG. 7 is a schematic diagram illustrating an implementation of an LDPC decoding process according to an exemplary embodiment;

FIG. 8 is a schematic diagram illustrating a decoding process of an LDPC decoder according to the related art;

FIG. 9 is a flowchart illustrating a method of LDPC decoding according to another exemplary embodiment of the present application;

FIG. 10 is a schematic diagram illustrating an implementation of the LDPC decoding method shown in FIG. 9;

FIG. 11 is a flowchart illustrating a method of LDPC decoding according to another exemplary embodiment of the present application;

FIG. 12 is a schematic diagram illustrating a structure of an LDPC decoder according to an exemplary embodiment of the present application;

fig. 13 shows a schematic structural diagram of a communication device according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

For ease of understanding, the terms referred to in the embodiments of the present application will be first described below.

LDPC check matrix: is a low density sparse matrix of 0,1 indicator bits for decoding data in a code block. If the data length of the code block to be decoded is N, and the data length of the check data is M (corresponding, the data length of the effective data in the code block is N-M, the code rate of the code block is (N-M)/N), the LDPC check matrix H for decoding the code block is an mxn matrix, where the number of "1" in each indicated row is the same in the mxn matrix, and both are N-M; the number of "1" s in each indicated column is the same.

When a large amount of valid data and check data are contained in a code block, the direct use of the LDPC check matrix occupies a large amount of storage space, and the LDPC base matrix (or called a base map) in the embodiment of the present application is a simplified representation of the LDPC check matrix. In the decoding stage, the LDPC decoder decodes the code block through the LDPC base matrix. An exemplary LDPC base matrix is shown in FIG. 1 and comprises m rows of indicator rows, each indicator row comprising n indicator bits.

In the LDPC base matrix, the indication bit of element 1 is referred to as a valid indication bit, and the indication bit of element 0 is referred to as an invalid indication bit. When decoding is performed by using the LDPC matrix, if the indication bit corresponding to the data is a valid indication bit, the LDPC decoder processes the data, and if the indication bit corresponding to the data is an invalid indication bit, the LDPC decoder does not process the data.

In the related art, an LDPC decoder performs decoding in an iterative manner. Illustratively, as shown in fig. 2, in each iteration, for each indication row in the LDPC base matrix, the LDPC decoder reads data corresponding to the valid indication bits from the memory 21 and performs calculation according to the valid indication bits in the current indication row. After the calculation is completed, the LDPC decoder writes the data back to the original position of the memory 21 so that the data is read from the position before the calculation is performed based on the next indicated line.

After the n-line indication line calculation is completed, the LDPC decoder reads data corresponding to the valid indication bits from the memory 21, and performs parity and CRC check. If the verification is correct, determining that decoding is completed and outputting data, and if the verification is incorrect, starting the next iteration until the upper limit of the iteration times or the verification is correct.

Illustratively, when decoding is performed using the LDPC base matrix shown in fig. 1, a process of performing data processing based on the first indication line and the second indication line in the LDPC base matrix is shown in fig. 3.

In fig. 3, the LDPC decoder first reads data from the memory according to a first indication line, where the numbers in the squares are used to represent storage locations of the data in the memory, and the squares corresponding to valid indication bits in the indication line include numbers. And according to the valid indication bits in the first indication row, the LDPC decoder performs decoding calculation on the data corresponding to the valid indication bits, and rewrites the data back into the memory after the decoding calculation is completed.

When performing decoding calculation according to the second indication line, similar to the first indication line, the LDPC decoder needs to read data from the memory again according to the second indication line, and perform decoding calculation on data corresponding to the valid indication bits according to the valid indication bits in the second indication line, so that after the decoding calculation is completed, the data is rewritten back into the memory.

Obviously, in the above process, the decoding calculation process between adjacent indication lines is completely independent and is performed in series, and there is an intersection between the data written back to the memory after the decoding calculation of the first indication line and the data read from the memory based on the second indication line (the data with storage positions of 1, 4, 6, 10, …, n in the memory), and repetition of this data writing back and reading process will result in an extended LDPC decoding delay.

The embodiment of the application provides an LDPC decoding method, when the LDPC decoding method is used for decoding, after decoding calculation of data is completed based on the current indication line in an LDPC base matrix, the data after the decoding calculation is not directly written back to a first memory, but the data corresponding to the overlapped effective indication bits are reserved in a second memory (i.e. not written back to the first memory) according to the overlapping condition (i.e. intersection condition) of the effective indication bits between the current indication line and the next indication line, so that the data corresponding to the overlapped effective indication bits need to be read from the first memory again when the decoding calculation is performed based on the next indication line, and the decoding time delay of an LDPC decoder is shortened. The LDPC decoding method is described using exemplary embodiments as follows.

Referring to fig. 4, a method flowchart of an LDPC decoding method according to an exemplary embodiment of the present application is shown. This embodiment will be described by taking the method for an LDPC decoder as an example, and the method may include the following steps.

Step 401, an LDPC base matrix corresponding to a code block is acquired, where the code block is located in a first memory.

In one possible implementation, the code block is encoded by an LDPC encoder, and the code block and the LDPC base matrix are provided by the LDPC encoder, so that the LDPC decoder decodes the data in the code block using the LDPC base matrix, thereby obtaining the original data.

The code block comprises effective data and check data, wherein the check data is used for checking the effective data and correcting errors when the check fails.

In some embodiments, in the communication system, the code block is encoded by an LDPC encoder of the access network device, and transmitted to the terminal device through an air interface, and decoded by an LDPC decoder of the terminal device; or the code block is obtained by encoding by an LDPC encoder of the terminal equipment, is transmitted to the access network equipment through an air interface, and is decoded by an LDPC decoder of the access network equipment.

Optionally, a random access memory (Random Access Memory, RAM) in the first memory.

Step 402, according to the i-th indication row in the LDPC base matrix, reading data from the first memory, and performing decoding calculation on the read data to obtain i-th calculation data, wherein i is a positive integer, and the data read from the first memory is written into the second memory.

When decoding calculation is carried out on data by utilizing the ith indication row in the LDPC base matrix, the LDPC decoder reads the data from the first memory and writes the read data into the second memory. Further, the computer equipment performs decoding calculation on the data written in the second memory to obtain ith calculation data. The ith calculation data may be the same as the data read from the first memory (the data transmission is correct), or may be different (the data transmission is error-corrected).

The second memory is different from the first memory, and optionally, the second memory is a register or a first-in first-out (First Input First Output, FIFO) memory, and the type of the second memory is not limited in this embodiment.

In step 403, in response to the intersection of the i+1th indication line and the valid indication bit in the i-th indication line, the intersection data in the i-th calculation data is retained in the second memory, and the data other than the intersection data is written back to the first memory, where the intersection data is the data corresponding to the intersection valid indication bit in the i-th calculation data.

Unlike the related art, after the i-th indication line processing is completed, the obtained i-th calculation data is directly written back to the first memory so as to perform the i+1-th indication line processing, in this embodiment of the present application, before writing back the data to the first memory, the LDPC decoder first determines whether an intersection exists between the i+1-th indication line and the valid indication bit in the i-th indication line, and if so, in order to avoid the data corresponding to the intersection valid indication bit from being rewritten back and read, the LDPC decoder retains the intersection data corresponding to the intersection valid indication bit in the second memory, and directly uses the intersection data for the i+1-th indication line processing. For other data than the intersection valid indicator bits, the LDPC decoder still writes the other data back into the first memory for reading when the i+1-th indicator row processing is performed.

In one possible implementation, the LDPC decoder performs the above method for each indicated row in the LDPC base matrix; in another possible implementation, since the LDPC base matrix is generally set to have the first k rows of valid indication bits overlap more, the LDPC decoder performs the above method for the first k indication rows in the LDPC base matrix, and the LDPC decoder directly writes the calculation data back to the first memory for the subsequent indication row processing in a conventional manner for the indication rows other than the first k indication rows. For example, k is 4.

In connection with the LDPC base matrix shown in fig. 1, in an illustrative example, after the LDPC decoder completes the first indication line processing to obtain the first calculated data, since there are intersection valid indication lines 1, 4, 6, 10,..and n between the first indication line and the second indication line, the LDPC decoder writes and holds data corresponding to valid indications 1, 6, 10,..and n in the first calculated data in the second memory, and writes the remaining data back in the first memory.

In another illustrative example, after the fourth indication line processing is completed to obtain fourth calculation data, since the intersection valid indication lines 5, 7, 9, … exist between the fourth indication line and the fifth indication line, the LDPC decoder writes and holds data corresponding to the valid indications 5, 7, 9, … in the fourth calculation data in the second memory, and writes the remaining data back in the first memory.

Obviously, by adopting the scheme provided by the embodiment of the application, the data corresponding to the intersection effective indication lines between the adjacent indication lines do not need to be written back to the first memory and then read, so that the time consumption for writing back and reading the data in the decoding process can be reduced, and the decoding time delay of LDPC decoding is reduced (especially under the condition of higher overlapping degree between the adjacent indication lines).

In summary, in this embodiment of the present application, based on the characteristic that an intersection exists between the valid indication bits of adjacent indication rows in the LDPC base matrix, the LDPC performs decoding calculation on the code block data based on the current indication row in the base matrix, after calculation data is obtained, data corresponding to the intersection valid indication bits between the next indication rows in the calculation data is retained in the second memory and used for decoding calculation of the next indication rows, thereby avoiding repeated writing and reading of the data corresponding to the intersection valid indication bits, and further improving decoding efficiency of the LDPC decoder.

In a possible implementation manner, in the process of reading data by the LDPC decoder, reading data (including valid indicating bits and invalid indicating bits) corresponding to each indicating bit in the indicating line, and in the process of decoding calculation, processing only the data corresponding to the valid indicating bits in the second memory; in another possible implementation manner, in the process of reading data, the LDPC decoder only reads data corresponding to valid indication bits in the indication rows, but does not read data corresponding to invalid indication bits, and correspondingly, in the process of decoding calculation, the LDPC decoder processes each data written in the second memory. The LDPC decoding method provided in the embodiment of the present application is applicable to both of the above two scenarios, and is described below using an exemplary embodiment.

Referring to fig. 5, a method flowchart of an LDPC decoding method according to another exemplary embodiment of the present application is shown. This embodiment will be described by taking the method for an LDPC decoder as an example, and the method may include the following steps.

In step 501, an LDPC base matrix corresponding to a code block is obtained, where the code block is located in a first memory.

For the implementation of this step, reference may be made to step 401 described above, and this embodiment will not be repeated here.

In one illustrative example, the LDPC decoder obtains an LDPC base matrix as shown in fig. 1.

Step 502, according to the ith indication row in the LDPC base matrix, reading the data corresponding to each indication bit from the first memory and writing the data into the second memory.

In this embodiment, the LDPC decoder reads data corresponding to the valid indicator bit and the invalid indicator bit from the first memory based on the i-th indicator row, and writes the read data into the second memory.

Illustratively, as shown in fig. 6, during the first indication line processing, the LDPC decoder reads data corresponding to n indication bits from the first memory according to the first indication line of the LDPC base matrix shown in fig. 1, and writes the data into the second memory.

And step 503, performing decoding calculation on the data corresponding to the valid indication bit in the ith indication row to obtain ith calculation data.

Although the data of the valid indicator bit and the invalid indicator bit are read in the data reading process, in the actual decoding calculation process, the LDPC decoder decodes only the data corresponding to the valid indicator bit, so that the LDPC decoder performs decoding calculation on the data corresponding to the valid indicator bit in the ith indicator row (i.e. the data corresponding to 1 in the indicator row) in the second memory, and obtains the ith calculation data.

Optionally, the ith calculation data includes data corresponding to all the indication bits.

Illustratively, as shown in fig. 6, in the decoding calculation process, the LDPC decoder performs decoding calculation on the data corresponding to the 1 st, 2 nd, 4 th, 6 th, 7 th, 9 th, 10 th, … th and n th indicating bits to obtain the i-th calculated data.

In step 504, in response to the i+1th indication line having an intersection with the valid indication bit in the i-th indication line, the intersection data in the i-th calculation data is retained in the second memory, and data other than the intersection data is written back to the first memory, where the intersection data is data corresponding to the intersection valid indication bit in the i-th calculation data.

The implementation of this step may refer to step 403, and this embodiment is not described herein.

Illustratively, as shown in fig. 6, when the first indication line processing is completed and the data writing back is performed, the LDPC decoder determines that the intersection valid indication bits between the second indication line and the first indication line include 1, 4, 6, 10, …, n, so that the data corresponding to the 1 st, 4 th, 6 th, 10 th, … th, n indication bits in the i-th calculation data are retained in the second memory and directly used for the second indication line processing without writing back to the first memory.

For data corresponding to the indicator bits (including 2, 3, 5, 7, 8, 9, …, n-1) other than the intersection valid indicator bits, the LDPC decoder writes the data back to the first memory.

The ldpc completes the i-th indicated line processing through the above steps 501 to 504, and further performs the i+1-th indicated line processing through steps 505 to 506.

In step 505, data is read from the first memory according to the i+1th indication row and the intersection valid indication bit.

Since the data corresponding to the intersection valid indication bits is retained in the second memory when the i-th indication line processing is performed, the LDPC decoder only needs to read the data corresponding to the indication bits other than the intersection valid indication bits when the i+1-th indication line processing is performed.

In one possible implementation, the LDPC decoder determines other indication bits except the intersection valid indication bit from the i+1th indication row, reads data corresponding to the other indication bits from the first memory, and writes the data to a corresponding storage location in the second memory.

Illustratively, as shown in fig. 6, since the data corresponding to the 1 st, 4 th, 6 th, 10 th, … th, and n-th indication bits are reserved in the second memory, the LDPC decoder reads the data corresponding to the 2 nd, 3 rd, 5 th, 7 th, 8 th, 9 th, … th, and n-1 th indication bits from the first memory when performing the second indication line processing.

Step 506, performing decoding calculation on the intersection data and the data corresponding to the other valid indication bits in the i+1th indication line to obtain i+1th calculation data.

Further, the LDPC decoder performs decoding calculation on the partial data written in the second memory according to the valid indication bit in the i+1 indication row to obtain i+1 calculation data.

Illustratively, as shown in fig. 6, the LDPC decoder performs decoding computation on data corresponding to bits 1, 3, 4, 5, 6, 8, 10, …, n in the second memory according to the valid indicator bits in the second indicator row.

In one possible embodiment, when the i+2-th indication line processing is performed, the LDPC decoder retains data corresponding to the intersection valid indication bit in the i+1-th calculation data in the second memory according to the intersection valid indication bit of the i+2-th indication line and the i+1-th indication line.

In another illustrative example, as shown in fig. 7, in the LDPC base matrix 71, the first indication row and the second indication row each include 19 valid indication bits. After the LDPC decoder performs the first indication line processing to obtain the first calculated data 72, data corresponding to the valid indication bits 0, 2, 3, 5, 9, 11, 12, 15, 16, 19, 21, 22, 23 in the first calculated data 72 is directly applied to the second indication line processing according to the intersection of the valid indication bits between the first indication line and the second indication line, so that the second calculated data 73 is obtained, and is not transferred through the first memory.

By adopting the scheme provided by the embodiment of the application, the decoding experiment of LDPC decoding can be reduced and the decoding performance of the LDPC decoder can be improved on the premise that the single-port first memory is still used (namely, the simultaneous reading and writing are not supported) and the capacity of the first memory is not increased.

Based on the LDPC matrix shown in fig. 1, as shown in fig. 8, in the process of reading data according to the first indication line, the LDPC decoder reads only data corresponding to valid indication bits in the first indication line (i.e. reads only data corresponding to indication bits 1, 2, 4, 6, 7, 9, 10, …, n), and correspondingly, the LDPC performs decoding calculation on each data written in the second memory, and writes the obtained first calculation data back to the first memory. When the second indication line processing is performed, the LDPC decoder reads data corresponding to valid indication bits in the second indication line (only reads indication bits 1, 3, 4, 5, 6, 8, 10, …, n), performs decoding calculation on each data written in the second memory, and writes the obtained second calculation data back to the first memory. Obviously, in the above process, the problem of repeated write-back reading of intersection output between adjacent indication rows also exists.

Referring to fig. 9, a method flowchart of an LDPC decoding method according to another exemplary embodiment of the present application is shown. This embodiment will be described by taking the method for an LDPC decoder as an example, and the method may include the following steps.

Step 901, an LDPC base matrix corresponding to a code block is obtained, where the code block is located in a first memory.

Step 902, according to the ith indication row in the LDPC base matrix, reading data corresponding to the valid indication bits from the first memory, and writing the data into the second memory.

Unlike the embodiment shown in fig. 6, the LDPC decoder reads the data corresponding to each indication bit from the first memory, and in this embodiment, the LDPC decoder reads only the data corresponding to the valid indication bit in the i-th indication row from the first memory.

Illustratively, as shown in fig. 10, the LDPC decoder writes data corresponding to the indicator bits 1, 2, 4, 6, 7, 9, 10, …, n into the second memory according to the valid indicator bits in the first indicator row.

And 903, performing decoding calculation on the data in the second memory to obtain ith calculation data.

Accordingly, since only the data corresponding to the valid indication bits are written into the second memory, the LDPC decoder performs decoding calculation on each data in the second memory to obtain the ith calculation data, where the ith calculation data includes data corresponding to the decoded valid indication bits.

In step 904, in response to the i+1th indication line having an intersection with the valid indication bit in the i-th indication line, the intersection data in the i-th calculation data is retained in the second memory, and data other than the intersection data is written back to the first memory, where the intersection data is data corresponding to the intersection valid indication bit in the i-th calculation data.

Illustratively, as shown in fig. 10, when the first indication line processing is completed and the data writing back is performed, the LDPC decoder determines that the intersection valid indication bits between the second indication line and the first indication line include 1, 4, 6, 10, …, n, so that the data corresponding to the 1 st, 4 th, 6 th, 10 th, … th, n indication bits in the i-th calculation data are retained in the second memory and directly used for the second indication line processing without writing back to the first memory.

For data corresponding to the indicator bits (including 2, 7, 9, …, n-1) other than the intersection valid indicator bits, the LDPC decoder writes the data back to the first memory.

The ldpc completes the i-th instruction line processing through the above steps 901 to 904, and further performs the i+1-th instruction line processing through steps 905 to 906.

In step 905, data is read from the first memory based on the valid indicator bit and the intersection valid indicator bit in the i+1-th indicator row.

Since the data corresponding to the intersection valid indication bit between the i+1th indication line and the i+1th indication line is reserved in the second memory, when the i+1th indication line processing is executed, the LDPC decoder determines other valid indication bits except the intersection valid indication bit from the valid indication bits of the i+1th indication line, and further reads the data corresponding to the other valid indication bits from the first memory.

Illustratively, as shown in FIG. 10, the LDPC decoder reads the data corresponding to the indicator bits 3, 5, 8, …, n-1 from the first memory.

Step 906, performing decoding calculation on the data in the second memory to obtain the i+1th calculation data.

Similar to step 903 described above, since only the data corresponding to the valid indication bit is stored in the second memory, the LDPC decoder performs decoding calculation on each data in the second memory.

Illustratively, as shown in fig. 10, the LDPC decoder performs decoding computation on data corresponding to bits 1, 3, 4, 5, 6, 8, 10, …, n indicated in the second memory.

As can be seen from the above embodiments, the higher the overlapping rate of the effective indicator bits between the adjacent indicator lines, the more remarkable the effect of reducing the LDPC decoding delay. Conversely, the higher the overlapping rate of the valid indicator bits between adjacent indicator rows, the less obvious the effect of reducing the LDPC decoding delay, and the more additional execution logic is added, which leads to an increase in power consumption. Thus, in order to compromise decoding delay and power consumption, in one possible implementation, as shown in fig. 11, the method may include the following steps.

Step 1101, obtaining an LDPC base matrix corresponding to the code block.

In step 1102, the number of matrix rows of the LDPC base matrix and the code rate of the code block are obtained.

In general, the overlapping rate of the front k indicating rows in the LDPC base matrix is higher, the overlapping rate between the indicating rows other than the front k indicating rows is lower, and the number of matrix rows of the LDPC base matrix is related to the code rate of the code block, where the higher the code rate of the code block is, the fewer the number of matrix rows of the code block corresponding to the LDPC base matrix is. Based on this feature of the LDPC base matrix, in one possible implementation, after the LDPC decoder acquires the LDPC base matrix, the number of matrix rows of the LDPC base matrix and the code rate of the code block are acquired.

Optionally, if the number of rows of the matrix is smaller than the number threshold, or the code rate is larger than the code rate threshold, step 1104 is executed after the i-th indicated row decoding calculation is completed; the matrix line number is greater than the line number threshold, and the code rate is less than the code rate threshold, and step 1105 is performed after the i-th indicated line decoding calculation is completed. In one illustrative example, the line number threshold is 20 lines and the code rate threshold is 0.75. The present embodiment is not limited to a specific number of rows and code rate threshold configuration.

Step 1103, reading data from the first memory according to the i-th indication row in the LDPC base matrix, and performing decoding calculation on the read data to obtain i-th calculation data, where i is a positive integer.

For the implementation of this step, reference may be made to step 402, and this embodiment is not described herein.

Step 1104, if the number of rows of the matrix is smaller than the number of rows threshold, or if the code rate of the code block is larger than the code rate threshold, in response to the intersection of the i+1th indication row and the valid indication bit in the i-th indication row, retaining the intersection data in the i-th calculation data in the second memory, and writing the data except the intersection data back to the first memory.

When the number of rows of the matrix is smaller than the number threshold, or the code rate of the code block is larger than the code rate threshold, the overlap rate of the adjacent indication rows in the LDPC base matrix is higher, and in order to shorten the decoding delay, the LDPC decoder decodes through the scheme provided by the embodiment.

In step 1105, if the number of rows of the matrix is greater than the number of rows threshold and the code rate of the code block is less than the code rate threshold, the ith calculation data is written back to the first memory.

When the number of rows of the matrix is larger than the number threshold and the code rate is smaller than the code rate threshold, the overlapping rate of adjacent indication rows in the LDPC base matrix is lower, and in order to save power consumption, the LDPC decoder decodes through a scheme provided by the related technology.

In this embodiment, the LDPC decoder determines the write-back mode of the decoded and calculated data according to the LDPC base matrix and the code rate of the code block, so as to improve the decoding efficiency of the code block with high code rate, and avoid the problem of excessive decoding power consumption caused by adopting the partial write-back mode for the code block with low code rate (less improvement of decoding efficiency).

In other possible embodiments, for low rate code blocks, the LDPC decoder may employ different decoding strategies for different indicated rows due to the higher overlap rate of the preceding indicated rows.

Optionally, if the number of rows of the matrix is greater than the number of rows threshold, and the code rate of the code block is less than the code rate threshold, and i is greater than k, writing the ith calculation data back to the first memory, where k is less than the number of rows of the matrix.

And in response to the matrix line number being greater than the line number threshold, and the code rate of the code block being less than the code rate threshold, and i being equal to or less than k, performing the steps of retaining intersection data in the i-th calculation data in the second memory and writing data other than the intersection data back to the first memory in response to the i+1th indication line having an intersection with a valid indication bit in the i-th indication line.

When decoding a low-code-rate code block, for the front k indicating rows in the LDPC base matrix, the LDPC decoder adopts the scheme provided by the embodiment to decode, and the decoding efficiency can be obviously improved because the overlapping rate between the front k indicating rows is higher.

For the indication lines other than the first k indication lines, the overlap rate is low, so that the LDPC decoder adopts a scheme provided by the related technology to decode, and the increase of power consumption is avoided.

In one illustrative example, the LDPC base matrix includes 100 rows, and the code rate of the code block is 0.45, and when decoding the code block, the LDPC decoder uses a non-intersection data write-back method when decoding the first 4 rows, and uses an all-data write-back method when decoding the rest of the rows.

In the foregoing embodiment, the LDPC decoder sequentially performs decoding computation according to the indication rows in the base matrix, so as to further improve decoding efficiency, in one possible implementation manner, after the LDPC base matrix corresponding to the code block is acquired, the LDPC decoder determines an overlapping rate of valid indication bits between the indication rows in the LDPC base matrix, so that an execution timing of the indication rows in the LDPC base matrix is adjusted according to the overlapping rate, and the overlapping rate between adjacent indication rows after the execution timing is adjusted is higher than the overlapping rate between adjacent indication rows before the execution timing is adjusted.

In one illustrative example, the LDPC decoder obtains an overlap ratio between the first indication line and the second indication line of 0.7, an overlap ratio between the first indication line and the third indication line of 0.8, and an overlap ratio between the second indication line and the third indication line of 0.7. Because the overlapping rate between the first indication line and the third indication line is higher than that between the first indication line and the second indication line, the LDPC adjusts the execution time sequence of the indication lines into the first indication line, the second indication line, the third indication line and the second indication line, and further improves the LDPC decoding efficiency.

Optionally, after the LDPC base matrix corresponding to the code block is acquired, the LDPC decoder acquires the number of rows of the matrix of the LDPC base matrix and the code rate of the code block, and executes the step of acquiring the adjustment instruction row execution timing sequence when the number of rows of the matrix is greater than the number threshold and the code rate of the code block is less than the code rate threshold. If the number of rows of the matrix is smaller than the number threshold value and the code rate of the code block is larger than the code rate threshold value, the LDPC decoder keeps the execution time sequence of the indication rows in the LDPC base matrix.

It should be noted that, the line number threshold, the code rate threshold and the overlapping rate in the foregoing embodiments may be set reasonably by those skilled in the art according to actual needs or experience, and the embodiments of the present application do not limit the value of the foregoing data.

Referring to fig. 12, a schematic diagram of an LDPC decoder according to an exemplary embodiment of the present application is shown. The LDPC decoder 1200 includes: a logic operation unit 1201, a second memory 1202 and a first memory 1203, the logic operation unit 1201 being connected to the second memory 1202 and the first memory 1203, respectively.

The logic operation unit 1201 is configured to obtain an LDPC base matrix corresponding to a code block, where the code block is located in the first memory 1203;

The logic operation unit 1201 is configured to read data from the first memory 1203 according to an i-th indication row in the LDPC base matrix, and perform decoding calculation on the read data to obtain i-th calculation data, where i is a positive integer, and the data read from the first memory 1203 is written into the second memory 1202;

the logic operation unit 1201 is configured to, when there is an intersection between the i+1-th indication line and the valid indication bit in the i-th indication line, hold intersection data in the i-th calculation data in the second memory 1202, and write data other than the intersection data back to the first memory 1203, where the intersection data is data corresponding to the intersection valid indication bit in the i-th calculation data.

Optionally, the logic operation unit 1201 is configured to read, from the first memory 1203, data corresponding to each indication bit according to the i-th indication row in the LDPC base matrix, and write the data into the second memory 1202;

and the logic operation unit 1201 is configured to perform decoding calculation on the data corresponding to the valid indication bit in the ith indication row to obtain the ith calculation data.

Optionally, a logic operation unit 1201 is configured to read data from the first memory 1203 according to the i+1th indication row and the intersection valid indication bit;

And the logic operation unit 1201 is configured to perform decoding calculation on the intersection data and data corresponding to other valid indication bits in the i+1th indication row to obtain i+1th calculation data.

Optionally, the logic operation unit 1201 is configured to read, from the first memory 1203, data corresponding to a valid indication bit according to the i-th indication row in the LDPC base matrix, and write the data into the second memory 1202;

a logic operation unit 1201, configured to perform decoding calculation on the data in the second memory 1202 to obtain the ith calculation data.

Optionally, a logic operation unit 1201 is configured to read data from the first memory 1203 according to the valid indicator bit in the i+1th indicator row and the intersection valid indicator bit;

the logic operation unit 1201 is configured to perform decoding calculation on the data in the second memory 1202 to obtain i+1th calculation data.

Optionally, the logic operation unit 1201 is configured to obtain a matrix row number of the LDPC base matrix and a code rate of the code block;

and in response to the matrix row number being smaller than a row number threshold, or the code rate of the code block being larger than a code rate threshold, executing the steps of responding to the fact that an intersection exists between an i+1th indication row and a valid indication bit in the i indication row, reserving intersection data in the i calculation data in the second memory, and writing data except the intersection data back to the first memory.

Optionally, the logic operation unit 1201 is configured to write the ith calculation data back to the first memory 1203 in response to the number of rows of the matrix being greater than the number threshold and the code rate of the code block being less than the code rate threshold.

Optionally, the logic operation unit 1201 is configured to write the ith calculation data back to the first memory 1203 in response to the number of rows of the matrix being greater than the number of rows threshold, and the code rate of the code block being smaller than the code rate threshold, and i being greater than k, where k is smaller than the number of rows of the matrix;

in response to the matrix row number being greater than the row number threshold, and the code rate of the code block being less than the code rate threshold, and i being less than or equal to k, the steps of responding to an i+1th indication row having an intersection with a valid indication bit in the i-th indication row, retaining intersection data in the i-th calculation data in the second memory 1202, and writing data other than the intersection data back to the first memory 1203 are performed.

Optionally, the logic operation unit 1201 is configured to determine an overlap ratio of valid indicator bits between the indicator rows in the LDPC base matrix; and adjusting the execution time sequence of the indication rows in the LDPC base matrix according to the overlapping rate, wherein the overlapping rate between adjacent indication rows after the execution time sequence is adjusted is higher than the overlapping rate between adjacent indication rows before the execution time sequence is adjusted.

Optionally, the logic operation unit 1201 is configured to obtain a matrix row number of the LDPC base matrix and a code rate of the code block; and determining the overlapping rate of effective indication bits between the indication rows in the LDPC base matrix in response to the matrix row number being greater than a row number threshold and the code rate of the code block being less than a code rate threshold.

The embodiment of the application also provides a communication chip, and the LDPC decoder in the embodiment is arranged in the communication chip. Alternatively, the communication chip may be a modem chip (modem) in the terminal.

Referring to fig. 13, a schematic structural diagram of a communication device according to an exemplary embodiment of the present application is shown. The communication device comprises a processor 1301, a memory 1302 and a transceiver 1303, and the processor 1301 is connected to the transceiver 1303 and the memory 1302 respectively. The processor 1301 includes a communication chip provided in the above embodiment.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The foregoing description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, since it is intended that all modifications, equivalents, improvements, etc. that fall within the spirit and scope of the invention.

Claims

1. A method of low density parity check code, LDPC, decoding, the method for an LDPC decoder, the method comprising:

2. The method of claim 1, wherein the reading data from the first memory according to the i-th indication row in the LDPC base matrix and performing decoding calculation on the read data to obtain i-th calculation data, includes:

reading data corresponding to each indication bit from the first memory according to the ith indication row in the LDPC base matrix, and writing the data into the second memory;

and decoding and calculating the data corresponding to the effective indication bit in the ith indication row to obtain the ith calculation data.

3. The method according to claim 2, wherein after the intersecting data in the i-th calculation data is held in the second memory and data other than the intersecting data is written back to the first memory, the method includes:

Reading data from the first memory according to the i+1th indication row and the intersection valid indication bit;

and decoding and calculating the intersection data and data corresponding to other valid indication bits in the (i+1) th indication row to obtain (i+1) th calculation data.

4. The method of claim 1, wherein the reading data from the first memory according to the i-th indication row in the LDPC base matrix and performing decoding calculation on the read data to obtain i-th calculation data, includes:

reading data corresponding to valid indication bits from the first memory according to the ith indication row in the LDPC base matrix, and writing the data into the second memory;

and decoding and calculating the data in the second memory to obtain the ith calculation data.

5. The method according to claim 4, wherein after the intersecting data in the i-th calculation data is held in the second memory and data other than the intersecting data is written back to the first memory, the method comprises:

reading data from the first memory according to the valid indicator bit in the i+1th indicator row and the intersection valid indicator bit;

And decoding and calculating the data in the second memory to obtain the i+1th calculation data.

6. The method according to any one of claims 1 to 5, wherein after the obtaining the LDPC base matrix corresponding to the code block, the method includes:

acquiring the matrix row number of the LDPC base matrix and the code rate of the code block;

7. The method of claim 6, wherein after the obtaining the matrix rows of the LDPC base matrix and the code rate of the code block, the method further comprises:

and writing the ith calculation data back to the first memory in response to the matrix row number being greater than the row number threshold and the code rate of the code block being less than the code rate threshold.

8. The method of claim 6, wherein after the obtaining the matrix rows of the LDPC base matrix and the code rate of the code block, the method further comprises:

Responding to the matrix line number being larger than the line number threshold, the code rate of the code block being smaller than the code rate threshold, and i being larger than k, writing the ith calculation data back to the first memory, k being smaller than the matrix line number, wherein k is a positive integer, and the overlapping rate of the effective indication bits corresponding to the front k indication lines in the LDPC base matrix is higher than the overlapping rate of the effective indication bits corresponding to the indication lines other than the front k indication lines;

and in response to the matrix row number being greater than the row number threshold, the code rate of the code block being less than the code rate threshold, and i being less than or equal to k, executing the steps of responding to the existence of an intersection of an i+1th indication row and a valid indication bit in the i-th indication row, retaining intersection data in the i-th calculation data in the second memory, and writing data except the intersection data back to the first memory.

9. The method according to any one of claims 1 to 5, wherein after the obtaining the LDPC base matrix corresponding to the code block, the method further comprises:

determining the overlapping rate of effective indication bits between indication rows in the LDPC base matrix;

and adjusting the execution time sequence of the indication rows in the LDPC base matrix according to the overlapping rate, wherein the overlapping rate between adjacent indication rows after the execution time sequence is adjusted is higher than the overlapping rate between adjacent indication rows before the execution time sequence is adjusted.

10. The method of claim 9, wherein after the obtaining the LDPC base matrix corresponding to the code block, the method comprises:

the determining the overlapping rate of the effective indication bits between the indication rows in the LDPC base matrix comprises the following steps:

and determining the overlapping rate of effective indication bits between the indication rows in the LDPC base matrix in response to the matrix row number being greater than a row number threshold and the code rate of the code block being less than a code rate threshold.

11. An LDPC decoder, the LDPC decoder comprising: the logic operation unit is respectively connected with the second memory and the first memory;

12. A communication chip, wherein the LDPC decoder of claim 11 is provided in the communication chip.

13. A communication device comprising a processor, a memory, and a transceiver, the processor being coupled to the transceiver and the memory, respectively;

the processor comprising the communication chip of claim 12.