CN110474647B - Decoding method, device, decoder and storage medium for LDPC code with finite field structure - Google Patents
Decoding method, device, decoder and storage medium for LDPC code with finite field structure Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
- H03M13/1125—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
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- H—ELECTRICITY
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- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6502—Reduction of hardware complexity or efficient processing
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Abstract
The embodiment of the application discloses a decoding method, a decoding device, a decoder and a computer readable storage medium of an LDPC code with a finite field structure, wherein the method comprises the following steps: obtaining channel information to be decoded; copying the information of the channel to be decoded to an LLR memory; performing iterative decoding flow to obtain decoding result; the iterative decoding process comprises the following steps: updating the variable nodes to obtain a first updating result, and storing the first updating result into a mapping memory corresponding to the submatrix; reading the first updating result from the mapping memory, updating the check node according to the first updating result to obtain a second updating result, and storing the second updating result into the mapping memory; judging whether the iterative updating is completed or not; and when the iterative updating is not completed, returning to the step of updating the variable nodes. According to the embodiment of the application, the consumption of the node memory is saved, and the demand for hardware memory resources is reduced.
Description
Technical Field
The application belongs to the technical field of communication, and particularly relates to a decoding method, a device, a decoder and a computer readable storage medium of an LDPC code with a finite field structure.
Background
The LDPC (Low Density Parity Check ) code is a block code, the check matrix of which only contains a small number of non-zero elements, and the sparsity of the check matrix H ensures that the decoding complexity and the minimum code distance only increase linearly with the code length.
The base matrix of the check matrix H of the LDPC code constructed in the finite field is calculated based on the galois field, and is generally implemented by a generating circuit, and the generating circuit of the base matrix corresponds to each sub-matrix and needs to be stored in each sub-processing unit. In the decoding process, intermediate results generated by the update of the VN (variable) node and the update of the CN (check) node are respectively required to be stored in different RAMs, namely, the intermediate results generated by the update of the VN node are stored in one RAM, and the intermediate results generated by the update of the CN node are stored in one RAM. The amount of memory RAM required for the VN node and CN node is proportional to the number of non-zero sub-matrices and the sub-matrix dimensions. In addition, in the iterative decoding process, different sub-matrices need to read channel information in parallel, and the channel information needs to be read in the whole iterative process, so that the channel information needs to be stored separately by taking the size of the sub-matrix as a unit, so that the requirement of parallel reading in updating nodes of different rows can be realized, and the quantity of the channel information storage RAM is increased.
In summary, for LDPC codes with finite field structure, the current decoding method requires a high amount of hardware storage resources.
Disclosure of Invention
In view of this, the embodiments of the present application provide a decoding method, apparatus, decoder and computer readable storage medium for LDPC codes with finite field structure, so as to solve the problem that the existing decoding method for LDPC codes has a high demand for hardware storage resources.
A first aspect of an embodiment of the present application provides a decoding method of an LDPC code of finite field construction, including:
obtaining channel information to be decoded;
copying the channel information to be decoded to an LLR memory;
performing iterative decoding flow to obtain decoding result;
the iterative decoding process comprises the following steps:
performing variable node update to obtain a first update result, and storing the first update result into a mapping memory corresponding to the submatrix;
reading the first updating result from the mapping memory, updating the check node according to the first updating result to obtain a second updating result, and storing the second updating result into the mapping memory;
judging whether the iterative updating is completed or not;
and when the iterative updating is not completed, returning to the step of updating the variable nodes.
With reference to the first aspect, in one possible implementation manner, the LLR memory is a memory including a first interface and a second interface, and channel information of sub-matrices corresponding to two different columns is stored in the same LLR memory;
the step of updating the variable node to obtain a first updating result comprises the following steps:
reading channel information to be decoded corresponding to two different columns of units from the same LLR memory through the first interface and the second interface respectively;
and updating according to the corresponding channel information to be decoded to obtain the first updating result.
With reference to the first aspect, in one possible implementation manner, the acquiring channel information to be decoded includes:
receiving the input channel information to be decoded;
and caching the channel information to be decoded into an input memory, wherein the input memory is a ping-pong memory.
With reference to the first aspect, in one possible implementation manner, before copying the channel information to be decoded to the LLR memory, the method further includes:
judging whether a decoder is empty and whether the input memory has data;
when the decoder is empty and the input memory has data, entering a step of copying the channel information to be decoded to an LLR memory later;
and returning to the step of acquiring the channel information to be decoded when the decoder is not empty and/or the input memory has no data.
With reference to the first aspect, in one possible implementation manner, the performing an iterative decoding process to obtain a decoding result includes:
performing iterative decoding flow to obtain hard decision data;
copying the hard decision data to an output memory, and outputting the decoding result.
A second aspect of embodiments of the present application provides a decoding apparatus for an LDPC code of finite field construction, including:
the acquisition module is used for acquiring channel information to be decoded;
a copying module for copying the channel information to be decoded to an LLR memory;
the iterative decoding module is used for performing an iterative decoding process to obtain a decoding result;
wherein the iterative decoding module comprises:
the variable node updating unit is used for updating the variable nodes to obtain a first updating result and storing the first updating result into a mapping memory corresponding to the submatrix;
the check node updating unit is used for reading the first updating result from the mapping memory, updating the check node according to the first updating result to obtain a second updating result, and storing the second updating result into the mapping memory;
a judging unit for judging whether the iterative updating is completed;
and the return unit is used for returning to the step of updating the variable nodes when the iterative updating is not completed.
With reference to the second aspect, in one possible implementation manner, the LLR memory is a memory including a first interface and a second interface, and channel information of sub-matrices corresponding to two different columns is stored in the same LLR memory;
the variable node updating unit includes:
the reading subunit is used for reading channel information to be decoded corresponding to two different columns of units from the same LLR memory through the first interface and the second interface respectively;
and the updating subunit is used for updating according to the corresponding channel information to be decoded to obtain the first updating result.
With reference to the second aspect, in one possible implementation manner, the acquiring module includes:
the receiving unit is used for receiving the input channel information to be decoded;
and the buffer unit is used for buffering the channel information to be decoded to an input memory, wherein the input memory is a ping-pong memory.
With reference to the second aspect, in one possible implementation manner, the method further includes:
the judging module is used for judging whether the decoder is empty and whether the input memory has data;
the execution module is used for entering the subsequent step of copying the channel information to be decoded to an LLR memory when the decoder is empty and the input memory has data;
and the return module is used for returning to the step of acquiring the channel information to be decoded when the decoder is not empty and/or the input memory has no data.
With reference to the second aspect, in one possible implementation manner, the iterative decoding module includes:
the iteration unit is used for carrying out an iterative decoding process to obtain hard decision data;
and the output unit is used for copying the hard decision data to an output memory and outputting the decoding result.
A third aspect of the embodiments of the present application provides a decoder comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the method according to any one of the first aspects described above when the computer program is executed.
A fourth aspect of the embodiments of the present application provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the method according to any one of the first aspects above.
Compared with the prior art, the embodiment of the application has the beneficial effects that: by carrying out the updating of the variable nodes and the check nodes in a time sharing manner in the decoding iteration process and storing the updating results of the variable nodes and the check nodes in the same mapping memory in a time sharing manner, compared with the traditional method of storing the intermediate data of the two nodes in different memories, the method saves half of the node memory consumption, and therefore the demand for hardware storage resources is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required for the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic block diagram of an LDPC code decoder according to an embodiment of the present application;
FIG. 2 is a schematic block diagram of a decoding method of LDPC codes with finite field structure according to an embodiment of the present application;
FIG. 3 is a schematic block diagram of an input memory according to an embodiment of the present application;
fig. 4 is a schematic block diagram of an LLR memory structure provided in an embodiment of the present application;
fig. 5 is a schematic block diagram of a decoding apparatus for an LDPC code with finite field structure according to an embodiment of the present application;
fig. 6 is a schematic diagram of a decoder according to an embodiment of the present application.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to illustrate the technical solutions described in the present application, the following description is made by specific examples.
Example 1
Before describing a specific flow of the decoding method, a decoder architecture according to an embodiment of the present application is described.
Referring to fig. 1, a schematic block diagram of an architecture of an LDPC code decoder according to an embodiment of the present application is provided, where the decoder includes a controller, a mapping memory, an LLR memory, a variable processing unit, a check processing unit, and an input memory.
The controller is used for executing a corresponding decoding flow, the variable processing unit is a variable node, and the diagram comprises n variable nodes; the check processing unit is check nodes, and the graph comprises m check nodes. n and m are positive integers. The LLR memory is used for storing channel information to be decoded copied from the input memory, the input memory is used for caching the channel information to be decoded which is input externally, and the output memory is used for storing the output decoding result.
The working flow of the decoder specifically comprises the following steps: and receiving externally input channel information, caching the channel information into an input memory, and copying data from the input memory to an LLR memory when a decoder is in a non-decoding state and channel data exists in the input memory, wherein the LLR memory corresponds to columns of a base matrix, and the depth of the LLR memory corresponds to the size of a submatrix of the base matrix. After copying is completed, entering an iterative decoding process, in the one-time iterative decoding process, firstly updating variable nodes to obtain updating results of the variable nodes, storing the updating results of the variable nodes into a mapping memory corresponding to the submatrices, then updating check nodes, and reading the updating results used for updating the check nodes from the mapping memory to obtain updating results of the check nodes. The updating result of the variable node and the updating result of the check node are stored in the same mapping memory. After finishing one iteration, judging whether the iteration number reaches the preset number, if not, performing the next iteration until the iteration number reaches the preset number. After iteration is completed, a hard decision result is obtained, and then the hard decision result is copied from the mapping memory to the decoding output memory to output a decoding result.
It should be noted that, based on the decoder provided in the embodiment of the present application, in a process of iterative decoding, an update result of a check node and an update result of a variable node are stored in the same mapping memory, so that half of node memory consumption can be saved.
In addition, in order to further reduce the demand of the decoding process for hardware storage resources, the LLR memory may be designed as a dual-port memory, and the channel information of the corresponding sub-matrices of two different columns may be stored in the same LLR memory. In the variable node updating process, channel information corresponding to two different column units is read from two interfaces respectively, so that half of LLR memories can be saved.
In order to further save hardware storage resources in the decoding process, the input memory in the decoder provided in the embodiment of the present application may be a ping-pong memory, which may perform the decoding process and the data receiving process simultaneously without increasing the number of frame memories.
Taking LDPC (374, 196) as an example, the number of RAM uses before and after optimization is compared with the number shown in table 1 below based on decoding by the decoder provided in the embodiment of the present application.
TABLE 1
| Type(s) | Prior Art | The application |
| Input memory | 1 number of | 2 pieces of |
| LLR memory | 24 pieces | 12 |
| Node memory | 208 | 104 pieces of |
| Output memory | 1 number of | 1 number of |
| Total memory quantity | 234 pieces of | 119 pieces of |
As can be seen from table 1, through the decoder and decoding method according to the embodiments of the present application, the number of memories can be effectively reduced, thereby reducing the amount of hardware memory resources required in the LDPC decoding process.
It should be noted that the LDPC code in the embodiments of the present application may be applied to various fields, including but not limited to aerospace, communication, deep sea exploration, smart storage, smart home, cloud storage, and the like.
After describing the decoder architecture provided in the embodiments of the present application, a decoding process based on the decoder will be described below.
Referring to fig. 2, a schematic flow diagram of a decoding method of an LDPC code with finite field structure according to an embodiment of the present application may include the following steps:
step S201, obtaining channel information to be decoded.
Specifically, the channel information to be decoded, which is input from the outside, is received, and the channel information is cached in the input memory. In order to further reduce the hardware memory resource requirement of the decoding process, the input memory may be a ping-pong memory, which is designed to be two frames of data, and when one frame of data is decoded, the other frame of data may be the newly input data.
In some embodiments, the process of obtaining the channel information to be decoded may include: receiving input channel information to be decoded; and caching the channel information to be decoded into an input memory, wherein the input memory is a ping-pong memory.
It should be noted that, the frame buffer is used in the input memory, and the ping-pong memory is used to complete the storage of two-frame channel information at the input interface of the decoder, so that the decoding process and the data receiving process can be performed simultaneously without increasing the number of the frame memories, so as to save the RAM usage.
Referring to the block diagram of the input memory shown in fig. 3, the input memory in_buf can store two frames of data, one frame is 6×n bits, 6 represents the bit number of soft information, the data of different frames are input into the storage units beginning at different offset addresses, and after the frame units beginning at the a address are fully written, the frame addresses beginning at the B address are written, and the units of the a address can be read at the same time, so that ping-pong switching is performed and continuous operation is performed. The English in the figure is a common symbol in the art, for example, offset A and Offset B respectively represent Offset address A and Offset address B, MUX represents a gate, dat_in [5:0] represents data input, dat_out [5:0] represents data output, and in_buf_radr and in_buf_wadr are respectively a read port and a write port of an input memory.
Of course, it is within the scope of embodiments of the present application to use existing input memory designs.
Step S202, the channel information to be decoded is copied to an LLR memory.
Specifically, after the channel information is buffered in the input memory, the data in the input memory may be copied to the LLR memory. The LLR memories correspond to columns of the base matrix, the depths of the LLR memories correspond to sub-matrices of the base matrix, and channel information is sequentially written into the LLR memories respectively until copying of frame data is completed.
The LLR memory according to the embodiment of the present application may refer to the schematic block diagram of the LLR memory structure shown in fig. 4, where the LLR memory may store two columns of corresponding channel information, and a multiplexing switch is set at an interface of the memory, where the multiplexing switch is used for performing time-sharing writing and reading, and when the channel information is written, a write port of the multiplexing switch is turned on, and after one frame of data is written, a read port of the multiplexing switch is turned on, and a decoding process is performed.
In particular applications, the decoder may be in a decoding state, or may have no data in the input memory, and in such cases the data copying process cannot be performed. Thus, in some embodiments, before the copying the channel information to be decoded to the LLR memory, the method may further include: judging whether the decoder is empty and whether the input memory has data; when the decoder is empty and the input memory has data, entering the following step of copying the channel information to be decoded to the LLR memory; and returning to the step of acquiring the channel information to be decoded when the decoder is not empty and/or the input memory has no data.
When the decoder is empty, the decoder is indicated to be in a non-decoding state, otherwise, when the decoder is not empty, the decoder is indicated to be in a decoding state.
Step S203, performing iterative decoding flow to obtain decoding result.
Specifically, in an iterative decoding process, firstly, variable node updating is performed, then check node updating is performed, then, whether the iteration number reaches the preset iteration number is judged, if so, the iterative process is exited to obtain a hard decision result, and hard decision data is copied from a mapping memory to an output memory and is output as a decoding result. Performing iterative decoding flow to obtain hard decision data; and copying the hard decision data to an output memory, and outputting a decoding result.
The iterative decoding process comprises the following steps:
step S2031, performing variable node update to obtain a first update result, and storing the first update result in a mapping memory corresponding to the submatrix.
The first updating result and the second updating result are intermediate data generated in the node updating process.
In some embodiments, the LLR memory is a memory including a first interface and a second interface, and channel information of sub-matrices corresponding to two different columns is stored in the same LLR memory. The specific structure of the LLR memory can be seen in fig. 4, where the LLR memory includes two interfaces, and both interfaces are provided with multiplexing switches for performing read/write gating. When both interfaces are read gates, channel information corresponding to two different column units can be read through the two interfaces respectively.
The process of updating the variable node to obtain the first updating result specifically includes: reading channel information to be decoded corresponding to two different columns of units from the same LLR memory through a first interface and a second interface respectively; and updating according to the corresponding channel information to be decoded to obtain a first updating result.
It should be noted that, the LLR memory is a dual-port memory, and in the data storage process, channel information of sub-matrices corresponding to different columns is written into the same mapping memory, and the channel information respectively corresponds to two different columns of the base matrix. In the variable node updating process, channel information corresponding to two different column units is read from two interfaces respectively, so that half of LLR memories can be saved, and the demand of the decoding process on hardware storage resources is further reduced.
Step S2032, reading the first update result from the mapping memory, updating the check node according to the first update result, obtaining a second update result, and storing the second update result in the mapping memory.
It should be noted that, the mapping memory in which the first updating result and the second updating result are stored is the same memory.
Step S2033, judging whether the iterative updating is completed; returning to the step S2031 when the iterative update is not completed; otherwise, when the iterative update is completed, the process advances to step S2034.
And judging whether the iteration update is finished or not by judging whether the iteration number reaches the preset iteration number, and when the iteration number reaches the preset iteration number, indicating that the iteration update is finished, otherwise, not finishing the iteration update.
Step S2034, outputting the decoding result.
According to the embodiment of the application, the variable nodes and the check nodes are updated in a time-sharing mode in the decoding iteration process, and the updating results of the variable nodes and the check nodes are stored in the same mapping memory in a time-sharing mode.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present application in any way.
Example two
Referring to fig. 5, a schematic block diagram of a decoding apparatus for an LDPC code with finite field structure according to an embodiment of the present application may include:
an obtaining module 51, configured to obtain channel information to be decoded;
a copying module 52, configured to copy the channel information to be decoded to the LLR memory;
the iterative decoding module 53 is configured to perform an iterative decoding process to obtain a decoding result;
wherein the iterative decoding module 53 includes:
the variable node updating unit 531 is configured to perform variable node updating to obtain a first updating result, and store the first updating result in a mapping memory corresponding to the submatrix;
the check node updating unit 532 is configured to read the first update result from the mapping memory, perform check node update according to the first update result, obtain a second update result, and store the second update result to the mapping memory;
a judging unit 533 for judging whether the iterative update is completed;
and a return unit 534, configured to return to the step of performing variable node update when the iterative update is not completed.
In one possible implementation, the LLR memory is a memory including a first interface and a second interface, and channel information of sub-matrices corresponding to two different columns is stored in the same LLR memory;
the variable node update unit may include:
the reading subunit is used for reading channel information to be decoded corresponding to two different column units from the same LLR memory through the first interface and the second interface respectively;
and the updating subunit is used for updating according to the corresponding channel information to be decoded to obtain a first updating result.
In one possible implementation manner, the acquiring module may include:
the receiving unit is used for receiving the input channel information to be decoded;
and the buffer unit is used for buffering the channel information to be decoded to the input memory, wherein the input memory is a ping-pong memory.
In one possible implementation manner, the apparatus may further include:
the judging module is used for judging whether the decoder is empty and whether the input memory has data;
the execution module is used for entering the subsequent step of copying the channel information to be decoded to the LLR memory when the decoder is empty and the input memory has data;
and the return module is used for returning to the step of acquiring the channel information to be decoded when the decoder is not empty and/or the input memory has no data.
In one possible implementation manner, the iterative decoding module may include:
the iteration unit is used for carrying out an iterative decoding process to obtain hard decision data;
and the output unit is used for copying the hard decision data to the output memory and outputting a decoding result.
It should be noted that, the decoding device of the LDPC code with the finite field structure provided in the embodiment of the present application corresponds to the decoding method of the LDPC code with the finite field structure in the first embodiment, and the relevant description is referred to the above corresponding content and is not repeated here.
According to the embodiment of the application, the variable nodes and the check nodes are updated in a time-sharing mode in the decoding iteration process, and the updating results of the variable nodes and the check nodes are stored in the same mapping memory in a time-sharing mode.
Example III
Fig. 6 is a schematic diagram of a decoder according to an embodiment of the present application. As shown in fig. 6, the decoder 6 of this embodiment includes: a processor 60, a memory 61 and a computer program 62 stored in said memory 61 and executable on said processor 60. The processor 60, when executing the computer program 62, implements the steps in the decoding method embodiment of the LDPC code of each finite field configuration described above, for example, steps S201 to S203 shown in fig. 2. Alternatively, the processor 60, when executing the computer program 62, performs the functions of the modules or units of the apparatus embodiments described above, such as the functions of the modules 51 to 53 shown in fig. 5.
By way of example, the computer program 62 may be divided into one or more modules or units, which are stored in the memory 61 and executed by the processor 60 to complete the present application. The one or more modules or units may be a series of computer program instruction segments capable of performing the specified functions, which instruction segments describe the execution of the computer program 62 in the decoder 6. For example, the computer program 62 may be divided into an acquisition module, a copy module, and an iterative decoding module, each of which functions as follows:
the acquisition module is used for acquiring channel information to be decoded; the copying module is used for copying the channel information to be decoded to the LLR memory; the iterative decoding module is used for performing an iterative decoding process to obtain a decoding result;
wherein, iterative decoding module includes: the variable node updating unit is used for updating the variable nodes to obtain a first updating result and storing the first updating result into a mapping memory corresponding to the submatrix; the check node updating unit is used for reading the first updating result from the mapping memory, updating the check node according to the first updating result to obtain a second updating result, and storing the second updating result into the mapping memory; a judging unit for judging whether the iterative updating is completed; and the return unit is used for returning to the step of updating the variable nodes when the iterative updating is not completed.
The decoder may include, but is not limited to, a processor 60, a memory 61. It will be appreciated by those skilled in the art that fig. 6 is merely an example of the decoder 6 and is not meant to be limiting as the decoder 6 may include more or fewer components than shown, or may combine some components, or may include different components, e.g., the decoder may further include input and output devices, network access devices, buses, etc.
The processor 60 may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 61 may be an internal storage unit of the decoder 6, such as a hard disk or a memory of the decoder 6. The memory 61 may be an external storage device of the decoder 6, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the decoder 6. Further, the memory 61 may also include both an internal memory unit and an external memory device of the decoder 6. The memory 61 is used for storing the computer program and other programs and data required by the decoder. The memory 61 may also be used for temporarily storing data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus, decoder, and method may be implemented in other manners. For example, the apparatus, decoder embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules or units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each method embodiment described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.
Claims (8)
1. A method for decoding an LDPC code of finite field construction, comprising:
obtaining channel information to be decoded;
copying the channel information to be decoded to an LLR memory;
performing iterative decoding flow to obtain decoding result;
the iterative decoding process comprises the following steps:
performing variable node update to obtain a first update result, and storing the first update result into a mapping memory corresponding to the submatrix;
reading the first updating result from the mapping memory, updating the check node according to the first updating result to obtain a second updating result, and storing the second updating result into the mapping memory;
judging whether the iterative updating is completed or not;
returning to the step of updating the variable nodes when the iterative updating is not completed;
the LLR memory is a memory comprising a first interface and a second interface, and channel information of sub-matrixes corresponding to two different columns is stored in the same LLR memory;
the step of updating the variable node to obtain a first updating result comprises the following steps:
reading channel information to be decoded corresponding to two different columns of units from the same LLR memory through the first interface and the second interface respectively;
and updating according to the corresponding channel information to be decoded to obtain the first updating result.
2. The decoding method of the finite field structured LDPC code of claim 1, wherein the obtaining channel information to be decoded comprises:
receiving the input channel information to be decoded;
and caching the channel information to be decoded into an input memory, wherein the input memory is a ping-pong memory.
3. The decoding method of the finite field structured LDPC code of claim 2, further comprising, before copying the channel information to be decoded to an LLR memory:
judging whether a decoder is empty and whether the input memory has data;
when the decoder is empty and the input memory has data, entering a step of copying the channel information to be decoded to an LLR memory later;
and returning to the step of acquiring the channel information to be decoded when the decoder is not empty and/or the input memory has no data.
4. The method for decoding an LDPC code of finite field construction according to claim 1, wherein performing an iterative decoding process to obtain a decoding result comprises:
performing iterative decoding flow to obtain hard decision data;
copying the hard decision data to an output memory, and outputting the decoding result.
5. A decoding apparatus for an LDPC code of finite field construction, comprising:
the acquisition module is used for acquiring channel information to be decoded;
a copying module for copying the channel information to be decoded to an LLR memory;
the iterative decoding module is used for performing an iterative decoding process to obtain a decoding result;
wherein the iterative decoding module comprises:
the variable node updating unit is used for updating the variable nodes to obtain a first updating result and storing the first updating result into a mapping memory corresponding to the submatrix;
the check node updating unit is used for reading the first updating result from the mapping memory, updating the check node according to the first updating result to obtain a second updating result, and storing the second updating result into the mapping memory;
a judging unit for judging whether the iterative updating is completed;
the return unit is used for returning to the step of updating the variable nodes when the iterative updating is not completed;
the LLR memory is a memory comprising a first interface and a second interface, and channel information of sub-matrixes corresponding to two different columns is stored in the same LLR memory;
the variable node updating unit includes:
the reading subunit is used for reading channel information to be decoded corresponding to two different columns of units from the same LLR memory through the first interface and the second interface respectively;
and the updating subunit is used for updating according to the corresponding channel information to be decoded to obtain the first updating result.
6. The decoding device of the finite field structured LDPC code of claim 5, wherein the acquisition module comprises:
the receiving unit is used for receiving the input channel information to be decoded;
and the buffer unit is used for buffering the channel information to be decoded to an input memory, wherein the input memory is a ping-pong memory.
7. A decoder comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 4 when executing the computer program.
8. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 4.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162965A (en) * | 2006-10-09 | 2008-04-16 | 华为技术有限公司 | Deletion-correcting coding method and system of LDPC code |
| CN102299719A (en) * | 2011-08-23 | 2011-12-28 | 电子科技大学 | Non-iterative type LDPC code decoder |
| KR20130118162A (en) * | 2012-04-19 | 2013-10-29 | 삼성전자주식회사 | Low density parity-check code decoder and decoding method |
| CN105024705A (en) * | 2015-08-19 | 2015-11-04 | 西安电子科技大学 | Low-complexity multivariate LDPC code decoding method and decoder |
| CN106230760A (en) * | 2016-07-25 | 2016-12-14 | 深圳市通创通信有限公司 | A kind of Soft Inform ation acquisition methods being applicable to pi/4_DQPSK and device |
| CN107124187A (en) * | 2017-05-05 | 2017-09-01 | 南京大学 | A kind of ldpc code decoder based on equal difference check matrix applied to flash memory |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100804793B1 (en) * | 2005-10-07 | 2008-02-20 | 삼성전자주식회사 | Method for updating Check Node in Low Density Parity Check Decoder |
| CN101834614B (en) * | 2010-04-02 | 2012-12-26 | 西安电子科技大学 | Multielement LDPC code coding method and device capable of saving storage resource |
| CN102195655B (en) * | 2011-02-25 | 2013-02-06 | 山东大学 | Quasi-cyclic LDPC (Low Density Parity Check) decoder and decoding method thereof |
| CN102394661B (en) * | 2011-11-08 | 2015-05-06 | 北京邮电大学 | LDPC (low density parity check) decoder and decoding method based on layer decoding processing |
| CN105846830B (en) * | 2015-01-14 | 2019-07-30 | 北京航空航天大学 | Data processing equipment |
-
2019
- 2019-07-03 CN CN201910594193.0A patent/CN110474647B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101162965A (en) * | 2006-10-09 | 2008-04-16 | 华为技术有限公司 | Deletion-correcting coding method and system of LDPC code |
| CN102299719A (en) * | 2011-08-23 | 2011-12-28 | 电子科技大学 | Non-iterative type LDPC code decoder |
| KR20130118162A (en) * | 2012-04-19 | 2013-10-29 | 삼성전자주식회사 | Low density parity-check code decoder and decoding method |
| CN105024705A (en) * | 2015-08-19 | 2015-11-04 | 西安电子科技大学 | Low-complexity multivariate LDPC code decoding method and decoder |
| CN106230760A (en) * | 2016-07-25 | 2016-12-14 | 深圳市通创通信有限公司 | A kind of Soft Inform ation acquisition methods being applicable to pi/4_DQPSK and device |
| CN107124187A (en) * | 2017-05-05 | 2017-09-01 | 南京大学 | A kind of ldpc code decoder based on equal difference check matrix applied to flash memory |
Non-Patent Citations (2)
| Title |
|---|
| 1 Gbit/s QC-LDPC码译码结构的设计;黄志成等;《桂林电子科技大学学报》;第38卷(第2期);92-96 * |
| Reliability-Based Iterative Decoding of LDPC Codes Using Likelihood Accumulation;Jiang Ming等;《IEEE COMMUNICATIONS LETTERS》;第11卷(第8期);677-679 * |
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