CN116648860A

CN116648860A - Decoding method of LDPC (Low Density parity check) code and decoder of LDPC code

Info

Publication number: CN116648860A
Application number: CN202180086272.6A
Authority: CN
Inventors: 张睦; 金晶; 张旭; 何杰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-03-29
Filing date: 2021-03-29
Publication date: 2023-08-25
Also published as: WO2022204900A1

Abstract

The embodiment of the application provides a decoding method of an LDPC code and a decoder of the LDPC code, which relate to the technical field of information processing and can solve the problem that the decoding resource of the LDPC code is too high. The decoding method comprises the steps of updating the minimum value and the next minimum value of the kth bit of the ith row effective block of the last iteration according to the first flag information and the second flag information of the kth bit of the ith row and jth column effective block of the check matrix; acquiring the minimum value of the kth bit of the ith row effective block; the minimum value of the kth bit of the ith row of effective blocks is the smaller one of the minimum value of the kth bit of the ith row of effective blocks of the iteration and the minimum value of the kth bit of the ith row of effective blocks of the last iteration after updating; acquiring a value transmitted to a check node by a variable node of the kth bit of the ith row and jth column effective blocks according to the minimum value of the kth bit of the ith row effective blocks; and updating the minimum value and the next minimum value of the k bit of the ith effective block of the iteration according to the value transmitted to the check node by the variable node, and the first mark information and the second mark information.

Description

Decoding method of LDPC (Low Density parity check) code and decoder of LDPC code

Technical Field

The present application relates to the field of information processing technologies, and in particular, to a decoding method of an LDPC code and a decoder of the LDPC code.

Background

The LDPC (low density parity check ) code is the error correction code with the longest code length and the strongest error correction capability under high code rate at present, and is widely applied to data protection in the scenes of communication, storage and the like so as to improve the reliability of the system. To obtain the strongest error correction capability, the LDPC code employs iterative decoding, which successively approximates the correct codeword through multiple iterations.

Currently, in the decoding process of the LDPC code, a minimum value min1, a next minimum value min2, minimum value position information min1 idx and next minimum value position information min2 idx corresponding to each bit of each row of effective blocks in a check matrix of the LDPC code are required to be stored. Whereas the storage of the min1 idx and the min2 idx requires a large bit number, for example, 4KB length LDPC codes commonly used in SSD (solid state drive, solid State disk) controllers, a matrix of QC256 is adopted, and the storage of the min1 idx and the min2 idx is 8 bits. In addition, the comparison of multi-bit position information is also needed in the decoding process. Thus, a large amount of resources are required for management of the min1 idx and the min2 idx, resulting in too high decoding resources of the LDPC code.

Disclosure of Invention

The embodiment of the application provides a decoding method of an LDPC code and a decoder of the LDPC code, which can solve the problem that the decoding resource of the LDPC code is too high.

In order to achieve the above purpose, the application adopts the following technical scheme:

in a first aspect, there is provided a decoding method of a low density parity check, LDPC, code, the decoding method comprising: firstly, updating the minimum value and the next minimum value of the kth bit of the ith row effective block of the last iteration according to first flag information and second flag information corresponding to the kth bit of the ith row and jth column effective block of the check matrix of the LDPC code; wherein the first flag information indicates whether the minimum value has been updated; the second flag information indicates whether the next-to-small value has been updated; next, the minimum value of the kth bit of the ith row effective block is acquired; the minimum value of the kth bit of the ith row of effective blocks is the smaller one of the minimum value of the kth bit of the ith row of effective blocks of the iteration and the minimum value of the kth bit of the ith row of effective blocks of the last iteration after updating; next, obtaining the value of the variable node of the kth bit of the ith row and jth column effective block transmitted to the check node according to the minimum value of the kth bit of the ith row effective block; and then updating the minimum value and the next minimum value of the k bit of the effective block of the ith row of the iteration and the first mark information and the second mark information corresponding to the k bit of the effective block of the jth row of the iteration according to the value transmitted to the check node by the variable node of the k bit of the effective block of the jth row of the iteration.

Compared with the existing decoding method of the LDPC code, when each column of the effective block is decoded, the minimum value min corresponding to each bit of each row of the effective block is required to be determined according to the minimum value min1, the sub-minimum value min2, the position information min1_idx of the minimum value and the position information min2_idx of the sub-minimum value, so that when the decoding method of the LDPC code is utilized for decoding, the minimum value min1, the sub-minimum value min2, the position information min1_idx of the minimum value and the position information min2_idx of the sub-minimum value corresponding to each bit of each row of the effective block in the check matrix of the LDPC code are required to be stored, and the storage of the position information min1_idx of the minimum value and the position information min2_idx of the sub-minimum value requires a large bit number, so that the decoding resource of the LDPC code is too high, and the power consumption of the occupied area for decoding is high is caused. In the decoding method of the LDPC code provided by the embodiment of the application, when each column of the effective block is decoded, the minimum value of the last iteration and the next minimum value of the last iteration can be updated according to the first flag information and the second flag information, and then the minimum value corresponding to each bit of each row of the effective block can be obtained according to the minimum value of the last iteration and the minimum value of the current iteration so as to carry out subsequent decoding, so that in the decoding process of the LDPC code, the position information min1_idx of the minimum value corresponding to each bit of each row of the effective block in the check matrix of the LDPC code and the position information min2_idx of the next minimum value are not required to be stored, the minimum value of the last iteration, the minimum value of the current iteration and the next minimum value of the current iteration in the check matrix of the LDPC code can be stored, and the first flag information and the second flag information corresponding to each bit of each effective block can be only stored, and the cost and the bandwidth of the LDPC code can be reduced, and the occupied area can be reduced.

In one possible implementation manner, updating the minimum value and the next minimum value of the kth bit of the ith row effective block of the last iteration according to the first flag information and the second flag information corresponding to the kth bit of the ith row and jth column effective block of the check matrix of the LDPC code includes: if the first mark information corresponding to the kth bit of the ith row and jth column effective block indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block is updated, updating the minimum value of the kth bit of the ith row effective block in the last iteration into the next minimum value of the kth bit of the ith row effective block in the last iteration; and if the second mark information corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, updating the next-smallest value of the kth bit of the ith row effective block in the last iteration into the decoding information maximum quantized value. If the first flag information indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block is updated, the minimum value corresponding to the kth bit of the ith row and jth column effective block in the last iteration is not the minimum value, so that the minimum value corresponding to the kth bit of the ith row and jth column effective block in the last iteration can be updated to be the next minimum value corresponding to the kth bit of the ith row and jth column effective block in the last iteration. If the second flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, the next-smallest value corresponding to the kth bit of the ith row and jth column effective block in the last iteration is not the next-smallest value, so that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block in the last iteration can be invalidated into the decoding information maximum quantized value.

In one possible embodiment, if the j-th column is not the last column of the current iteration, after updating the minimum value and the next minimum value of the k-th bit of the i-th row effective block of the current iteration and the first flag information and the second flag information corresponding to the k-th bit of the i-th row and j-th column effective block according to the value transferred to the check node by the variable node of the k-th bit of the i-th row and j-th column effective block, the decoding method further includes: and carrying out cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of the effective block, wherein the shift quantity is equal to the offset value of the row of the effective block in the check matrix of the LDPC code. After decoding the j-th column, before decoding the next column, the minimum value of the current iteration, the next minimum value of the current iteration, the minimum value of the last iteration and the next minimum value of the last iteration can be circularly shifted according to the check matrix, and then the next column is decoded.

In one possible implementation, the difference between the offset values of two adjacent active blocks in each row in the check matrix of the LDPC code is a fixed value. Therefore, the decoding method of the LDPC code can be simplified, and the number of shift registers required in the decoding process is greatly reduced, so that the complexity of the decoder of the LDPC code can be greatly reduced.

In one possible implementation manner, performing cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of valid block includes: if the iteration starts from the 1 st column, updating the minimum value of the k bit of the i-th row effective block of the iteration to the minimum value of the k+p bit of the i-th row effective block of the iteration, and updating the minimum value of the k bit of the i-th row effective block of the previous iteration to the minimum value of the k+p bit of the i-th row effective block of the previous iteration; if k is less than or equal to p from the last column, updating the minimum value of the kth bit of the ith row of effective blocks of the iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the iteration, and updating the minimum value of the kth bit of the ith row of effective blocks of the previous iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the previous iteration; when k is more than p, updating the minimum value of the k bit of the i-th effective block of the iteration to the minimum value of the k-p bit of the i-th effective block of the iteration, and updating the minimum value of the k bit of the i-th effective block of the previous iteration to the minimum value of the k-p bit of the i-th effective block of the previous iteration; wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block. The minimum value of the current iteration, the next minimum value of the current iteration, the minimum value of the last iteration and the next minimum value of the last iteration can be shifted left or right according to whether the current iteration starts from column 1 or from the last column, and the number of bits shifted left or right can be determined according to the check matrix.

In one possible implementation manner, if the jth column is the last column of the present iteration, after updating the minimum value and the next minimum value of the kth bit of the ith row effective block of the present iteration, the first flag information, and the second flag information according to the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, the decoding method further includes: the minimum value of the k bit of the effective block of the ith row of the last iteration is updated to be the minimum value of the k bit of the effective block of the ith row of the current iteration, the next-smallest value of the k bit of the effective block of the ith row of the last iteration is updated to be the next-smallest value of the k bit of the effective block of the ith row of the current iteration, and the minimum value and the next-smallest value of the k bit of the effective block of the ith row of the current iteration are both updated to be the maximum quantized value of decoding information.

In one possible implementation, before decoding from the valid block of column 1 and performing the first iteration on the valid block of column 1, or before decoding from the valid block of the last column and performing the first iteration on the valid block of the last column, the above decoding method further includes: initializing the sign bit of the value transmitted to the check node by the variable node corresponding to each bit of each effective block in the check matrix of the LDPC code, the first flag information and the second flag information corresponding to each bit of each effective block, the minimum value and the next minimum value of the current iteration corresponding to each bit of each row of effective block, and the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of effective block. The symbol bit, the first flag information, the second flag information, the minimum value of the last iteration, the minimum value of the current iteration and the minimum value of the current iteration of the variable node transmitted to the check node are initialized, so that the accuracy of decoding can be ensured.

In one possible implementation manner, if the absolute value of the first pair of log confidence coefficients corresponding to the check matrix of the LDPC code is constant, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of the effective block are both the maximum quantized value of the decoding information after initialization; if the absolute value of the first pair of confidence coefficients corresponding to the check matrix of the LDPC code is non-constant, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of effective block are both 0 after initialization. The minimum and next-minimum values of the last iteration are initialized to different values depending on whether the decoding is soft-decision decoding or hard-decision decoding. In one possible implementation manner, the minimum value and the next-smallest value of the iteration corresponding to each bit of each row of effective block are both the maximum quantized value of the decoding information after initialization; the first flag information and the second flag information corresponding to each bit of each effective block are both a first preset value after initialization. The first flag information and the second flag information are initialized to the first preset value, so that accuracy of the first decoding can be ensured.

In one possible implementation manner, updating the minimum value and the next minimum value of the kth bit of the ith row effective block of the present iteration and the first flag information and the second flag information corresponding to the kth bit of the ith row and the jth column effective block according to the value transmitted to the check node by the variable node of the kth bit of the ith row and the jth column effective block includes: if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is smaller than the minimum value of the kth bit of the ith row effective block of the iteration, updating the secondary small value of the kth bit of the ith row effective block of the iteration to the minimum value of the kth bit of the ith row effective block of the iteration, updating the minimum value of the kth bit of the ith row effective block of the iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block of the iteration, and updating the first flag information and the second flag information corresponding to the kth bit of the ith row and jth column effective block of the iteration to a second preset value; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the minimum value of the kth bit of the ith row effective block of the iteration and smaller than the secondary small value of the kth bit of the ith row effective block of the iteration, updating the secondary small value of the kth bit of the ith row effective block of the iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, updating the first flag information corresponding to the kth bit of the ith row and jth column effective block to a first preset value and updating the second flag information to a second preset value; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the next-smallest value of the kth bit of the ith row and jth column effective block of the iteration, updating the first mark information and the second mark information corresponding to the kth bit of the ith row and jth column effective block to be a first preset value.

In one possible implementation, the obtaining the value of the variable node transmitted to the check node according to the minimum value of the k bit of the i row effective block includes: updating the exclusive or value of the symbol bit of the decoding information corresponding to the kth bit of the ith row of effective blocks, and calculating the value transmitted to the variable node by the check node of the kth bit of the ith row of the jth column of effective blocks according to the updated exclusive or value of the symbol bit of the decoding information corresponding to the kth bit of the ith row of effective blocks and the minimum value of the kth bit of the ith row of effective blocks; calculating a second pair of log-confidence corresponding to the kth bit of the valid block in the jth column according to the first pair of log-confidence corresponding to the kth bit of the valid block in the jth column and the values transmitted to the variable nodes by the check nodes corresponding to all valid blocks in the jth column; and calculating the value of the variable node transmitted to the check node of the kth bit of the ith row and jth column effective block according to the value of the check node transmitted to the variable node of the kth bit of the ith row and jth column effective block and the second pair of confidence coefficients corresponding to the kth bit of the jth column effective block.

In one possible implementation, updating the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks includes: and carrying out exclusive OR on the exclusive OR value of the symbol bit of the decoding information corresponding to the kth bit of the ith row effective block and the symbol bit of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block to obtain the exclusive OR value of the symbol bit of the decoding information corresponding to the kth bit of the updated ith row effective block.

In one possible implementation manner, calculating a value of a check node of the kth bit of the ith row and jth column effective blocks transmitted to a variable node according to the updated xor value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective blocks and the minimum value of the kth bit of the ith row effective blocks includes: and mapping the exclusive OR value of the sign bit of the decoding information corresponding to the k bit of the updated i row effective block into a positive sign or a negative sign, and multiplying the exclusive OR value with the minimum value of the k bit of the i row effective block to obtain the value of the variable node transmitted to the check node of the k bit of the i row and j column effective block.

In one possible implementation, calculating the second pair of confidence levels corresponding to the kth bit of the valid block in the jth column according to the first pair of confidence levels corresponding to the kth bit of the valid block in the jth column and the values transmitted from the check nodes corresponding to all valid blocks in the jth column to the variable nodes includes: and adding the values transmitted to the variable nodes by the check nodes corresponding to all the effective blocks in the j-th row and the first pair of the confidence coefficients corresponding to the k-th bit of the effective block in the j-th row according to the bits to obtain the second pair of the confidence coefficients corresponding to the k-th bit of the effective block in the j-th row.

In one possible implementation, calculating the value of the variable node transmitted to the check node at the kth bit of the jth valid block of the ith row and the jth column according to the value of the check node transmitted to the variable node at the kth bit of the jth valid block and the second pair of confidence coefficients corresponding to the kth bit of the jth valid block includes: subtracting the value of the check node transmitted to the variable node of the kth bit of the jth effective block of the ith row from the second pair of the confidence coefficients corresponding to the kth bit of the jth effective block of the jth row to obtain the value of the variable node transmitted to the check node of the kth bit of the jth effective block of the ith row.

In one possible embodiment, after obtaining the value of the variable node of the kth bit of the ith row and jth column valid blocks from the minimum value of the kth bit of the ith row valid blocks, the decoding method further includes: and updating the exclusive or value of the symbol bit of the decoding information corresponding to the kth bit of the ith row effective block according to the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block.

In one possible implementation manner, updating the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks according to the value transmitted to the check node by the variable node includes: and carrying out exclusive or on the sign bit of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block and the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block to obtain the updated exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block.

In a second aspect, there is provided a decoder of an LDPC code, the decoder of the LDPC code comprising: the memory is used for storing the minimum value and the next minimum value of the last iteration, the minimum value and the next minimum value of the current iteration, the first mark information and the second mark information; wherein the first flag information indicates whether the minimum value has been updated, and the second flag information indicates whether the next-minimum value has been updated; a processor, configured to update a minimum value and a next minimum value of a kth bit of an ith row of an effective block of a last iteration according to first flag information and second flag information corresponding to the kth bit of the ith row and jth column of the effective block of a check matrix of the LDPC code; acquiring the minimum value of the kth bit of the ith row effective block; the minimum value of the kth bit of the ith row of effective blocks is the smaller one of the minimum value of the kth bit of the ith row of effective blocks of the iteration and the minimum value of the kth bit of the ith row of effective blocks of the last iteration after updating; acquiring a value transmitted to a check node by a variable node of the kth bit of the ith row and jth column effective blocks according to the minimum value of the kth bit of the ith row effective blocks; and updating the minimum value and the next minimum value of the k bit of the ith row effective block of the iteration and the first mark information and the second mark information corresponding to the k bit of the ith row and the jth column effective block according to the value transmitted to the check node by the variable node of the k bit of the ith row and the jth column effective block. The decoder of the LDPC code has the same technical effects as the decoding method of the LDPC code provided in the first aspect, and the foregoing may be referred to, and will not be described herein.

In one possible implementation manner, the processor is specifically configured to update the minimum value of the kth bit of the ith row effective block of the previous iteration to the next minimum value of the kth bit of the ith row effective block of the previous iteration if the first flag information corresponding to the kth bit of the jth row effective block of the ith row indicates that the minimum value corresponding to the kth bit of the jth row effective block of the ith row is updated; and if the second mark information corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, updating the next-smallest value of the kth bit of the ith row effective block in the last iteration into the decoding information maximum quantized value.

In one possible implementation manner, if the j-th column is not the last column of the current iteration, the processor is further configured to perform cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the next minimum value of the last iteration, which correspond to each bit of the valid block in each row, where the shift amount is equal to the offset value of the row where the valid block is located in the check matrix of the LDPC code.

In one possible implementation, the difference between the offset values of two adjacent active blocks in each row in the check matrix of the LDPC code is a fixed value.

In one possible implementation manner, the processor is specifically configured to update, if the iteration starts from column 1, a minimum value of a kth bit of the i-th line effective block of the iteration to a minimum value of a k+p bit of the i-th line effective block of the iteration, and update a minimum value of a kth bit of the i-th line effective block of the previous iteration to a minimum value of a k+p bit of the i-th line effective block of the previous iteration; if k is less than or equal to p from the last column, updating the minimum value of the kth bit of the ith row of effective blocks of the iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the iteration, and updating the minimum value of the kth bit of the ith row of effective blocks of the previous iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the previous iteration; when k is more than p, updating the minimum value of the k bit of the i-th effective block of the iteration to the minimum value of the k-p bit of the i-th effective block of the iteration, and updating the minimum value of the k bit of the i-th effective block of the previous iteration to the minimum value of the k-p bit of the i-th effective block of the previous iteration; wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block.

In one possible implementation manner, if the j-th column is the last column of the present iteration, the processor is further configured to update the minimum value of the k-th bit of the i-th row effective block of the previous iteration to the minimum value of the k-th bit of the i-th row effective block of the present iteration, update the next-smallest value of the k-th bit of the i-th row effective block of the previous iteration to the next-smallest value of the k-th bit of the i-th row effective block of the present iteration, and update both the minimum value and the next-smallest value of the k-th bit of the i-th row effective block of the present iteration to the maximum quantization value of the decoding information.

In one possible implementation manner, the processor is specifically configured to update the next-smallest value of the kth bit of the ith row of the effective block of the present iteration to the smallest value of the kth bit of the ith row of the present iteration if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the jth row of the effective block of the present iteration is smaller than the smallest value of the kth bit of the ith row of the present iteration, update the smallest value of the kth bit of the ith row of the effective block of the present iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the jth row of the effective block of the present iteration, and update both the first flag information and the second flag information corresponding to the kth bit of the jth row of the ith row of the effective block of the present iteration to the second preset value; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the minimum value of the kth bit of the ith row effective block of the iteration and smaller than the secondary small value of the kth bit of the ith row effective block of the iteration, updating the secondary small value of the kth bit of the ith row effective block of the iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, updating the first flag information corresponding to the kth bit of the ith row and jth column effective block to a first preset value and updating the second flag information to a second preset value; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the next-smallest value of the kth bit of the ith row and jth column effective block of the iteration, updating the first mark information and the second mark information corresponding to the kth bit of the ith row and jth column effective block to be a first preset value.

In a third aspect, there is provided a decoder of an LDPC code, the decoder of the LDPC code comprising: and the CNU logic calculation unit and the VNU logic calculation unit. The CNU logic calculating unit is used for updating the minimum value of the kth bit of the ith row effective block of the last iteration and the next minimum value of the kth bit of the ith row effective block of the last iteration according to the first flag information and the second flag information corresponding to the kth bit of the ith row and the jth column effective block of the check matrix of the LDPC code; acquiring the minimum value of the kth bit of the ith row effective block; the minimum value of the kth bit of the ith row of effective blocks is the smaller one of the minimum value of the kth bit of the ith row of effective blocks of the iteration and the minimum value of the kth bit of the ith row of effective blocks of the last iteration after updating. The VNU logic calculation unit is used for acquiring the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block according to the minimum value of the kth bit of the ith row effective block; the CNU logic calculating unit is further used for updating the minimum value of the k bit of the ith row effective block of the iteration, the next minimum value of the k bit of the ith row effective block of the iteration, the first mark information and the second mark information corresponding to the k bit of the ith row and the jth column effective block of the iteration according to the value transmitted to the check node by the variable node of the k bit of the ith row and the jth column effective block obtained by the VNU logic calculating unit.

In one possible implementation manner, the decoder of the LDPC code further includes a storage unit, where the storage unit is configured to store a minimum value of a previous iteration, a next minimum value of a previous iteration, a minimum value of a current iteration, a next minimum value of a current iteration, first flag information, and second flag information. Wherein the first flag information indicates whether the minimum value is updated or not, and the second flag information indicates whether the next-minimum value is updated or not.

In one possible implementation manner, if the first flag information corresponding to the kth bit of the jth column effective block in the ith row indicates that the minimum value corresponding to the kth bit of the jth column effective block in the ith row is updated, and the second flag information corresponding to the kth bit of the jth column effective block in the ith row indicates that the next minimum value corresponding to the kth bit of the jth column effective block in the ith row is updated, the CNU logic calculating unit is specifically configured to update the minimum value of the kth bit of the ith row effective block in the last iteration to the next minimum value of the kth bit of the ith row effective block in the last iteration, and update the next minimum value of the kth bit of the ith row effective block in the last iteration to the maximum quantized value of the decoding information; if the second flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, the first flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the smallest value corresponding to the kth bit of the ith row and jth column effective block is not updated, the CNU logic calculating unit is specifically configured to update the next-smallest value of the kth bit of the ith row and effective block in the last iteration to be the decoding information maximum quantized value.

In one possible implementation, if the j-th column is not the last column of the current iteration, the decoder of the LDPC code further includes an updating unit; the updating unit is used for circularly shifting the minimum value of the iteration, the minor value of the iteration, the minimum value of the last iteration and the minor value of the last iteration, which correspond to each bit of each row of effective blocks obtained by the CNU logic calculating unit, and the shift quantity is equal to the offset value of the row where the effective block is located in the check matrix of the LDPC code.

In one possible implementation manner, if the present iteration starts from column 1, the updating unit is specifically configured to update the minimum value of the kth bit of the i-th line effective block of the present iteration to the minimum value of the k+p bit of the i-th line effective block of the present iteration, and update the minimum value of the kth bit of the i-th line effective block of the last iteration to the minimum value of the k+p bit of the i-th line effective block of the last iteration; if k is less than or equal to p from the last column, the updating unit is specifically configured to update the minimum value of the kth bit of the ith row of effective blocks in the present iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks in the present iteration, and update the minimum value of the kth bit of the ith row of effective blocks in the last iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks in the last iteration; when k is more than p, the updating unit is specifically configured to update the minimum value of the kth bit of the i-th row effective block of the current iteration to the minimum value of the k-p bit of the i-th row effective block of the current iteration, and update the minimum value of the k-th bit of the i-th row effective block of the last iteration to the minimum value of the k-p bit of the i-th row effective block of the last iteration; wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block.

In one possible implementation, the decoder of the LDPC code further includes an updating unit; if the j-th column is the last column of the present iteration, the updating unit is configured to update the minimum value of the k-th bit of the i-th row effective block of the previous iteration to the minimum value of the k-th bit of the i-th row effective block of the present iteration, update the next-smallest value of the k-th bit of the i-th row effective block of the previous iteration to the next-smallest value of the k-th bit of the i-th row effective block of the present iteration, and update the minimum value of the k-th bit of the i-th row effective block of the present iteration to the maximum quantized value of the decoding information.

In one possible implementation, the decoder of the LDPC code further includes an initialization unit; the initialization unit is used for initializing the sign bit of the value transmitted to the check node by the variable node corresponding to each bit of each effective block in the check matrix of the LDPC code, the first mark information and the second mark information corresponding to each bit of each effective block, the minimum value of the last iteration corresponding to each bit of each row of effective block, the minor value of the last iteration, the minimum value of the current iteration and the minor value of the current iteration.

In one possible implementation manner, if the absolute value of the first pair of log confidence coefficients corresponding to the check matrix of the LDPC code is a constant, the initializing unit is specifically configured to initialize the minimum value of the last iteration and the next minimum value of the last iteration corresponding to each bit of each row of the valid block to be the maximum quantized value of the decoding information. If the absolute value of the first pair of confidence coefficients corresponding to the check matrix of the LDPC code is non-constant, the initialization unit is specifically configured to initialize the minimum value of the last iteration and the next minimum value of the last iteration corresponding to each bit of each row of the effective block to be 0.

In a possible implementation manner, the initializing unit is further specifically configured to initialize the minimum value of the current iteration and the sub-minimum value of the current iteration corresponding to each bit of each row of valid block to a maximum quantized value of the decoding information; and initializing the first flag information and the second flag information corresponding to each bit of each effective block to a first preset value.

In one possible implementation manner, if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is smaller than the minimum value of the kth bit of the ith row effective block of the present iteration, the CNU logic calculating unit is further specifically configured to update the next-smallest value of the kth bit of the ith row effective block of the present iteration to the minimum value of the kth bit of the ith row effective block of the present iteration, update the minimum value of the kth bit of the ith row effective block of the present iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block of the present iteration, and update both the first flag information and the second flag information corresponding to the kth bit of the ith row and jth column effective block of the present iteration to the second preset value; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is greater than the minimum value of the kth bit of the ith row effective block of the iteration and smaller than the next-smallest value of the kth bit of the ith row effective block of the iteration, the CNU logic calculating unit is further specifically configured to update the next-smallest value of the kth bit of the ith row effective block of the iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, update the first flag information corresponding to the kth bit of the ith row and jth column effective block to the first preset value and update the second flag information to the second preset value; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is greater than the next-smallest value of the kth bit of the ith row effective block in the iteration, the CNU logic calculating unit is further specifically configured to update both the first flag information and the second flag information corresponding to the kth bit of the ith row and jth column effective block to a first preset value.

In one possible implementation manner, the CNU logic calculating unit is specifically configured to update an exclusive or value of a sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks, and calculate a value transmitted from the check node of the kth bit of the ith row of jth column of valid blocks to the variable node according to the updated exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks and the minimum value of the kth bit of the ith row of valid blocks. The VNU logic calculating unit is specifically configured to calculate a second pair of log-confidence coefficients corresponding to the kth bit of the jth valid block according to the first pair of log-confidence coefficients corresponding to the kth bit of the jth valid block and the values of the check nodes corresponding to all the jth valid blocks acquired by the CNU logic calculating unit; and calculating the value of the variable node transmitted to the check node of the kth bit of the ith row and jth column effective block according to the value of the check node transmitted to the variable node of the kth bit of the ith row and jth column effective block and the second pair of confidence coefficients corresponding to the kth bit of the jth column effective block.

In one possible implementation manner, the CNU logic calculating unit is specifically configured to xored the xor value of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks with the sign bit of the value transmitted to the check node by the variable node of the kth bit of the ith row of valid blocks, and obtain the xor value of the sign bit of the decoding information corresponding to the kth bit of the updated ith row of valid blocks.

In one possible implementation manner, the CNU logic calculating unit is further specifically configured to map the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the updated ith row of valid blocks to positive sign or negative sign, and multiply the mapped positive sign or negative sign with the minimum value of the kth bit of the ith row of valid blocks to obtain the value that the check node of the kth bit of the ith row of valid blocks is transmitted to the variable node.

In one possible implementation manner, the VNU logic calculating unit is further specifically configured to add, by bit, a value of a check node corresponding to all valid blocks in the j-th column to a variable node and a first pair of confidence levels corresponding to the k-th bit of the valid blocks in the j-th column, to obtain a second pair of confidence levels corresponding to the k-th bit of the valid blocks in the j-th column.

In one possible implementation manner, the VNU logic calculating unit is further specifically configured to subtract the value of the check node of the kth bit of the ith row and jth column valid block from the second log confidence corresponding to the kth bit of the jth column valid block, to obtain the value of the variable node of the kth bit of the ith row and jth column valid block transferred to the check node.

In one possible implementation manner, the CNU logic calculating unit is further configured to update the xor value of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks according to the value transmitted to the check node by the variable node of the kth bit of the ith row of valid blocks.

In one possible implementation manner, the CNU logic calculating unit is further specifically configured to xored the sign bit of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column of the valid block with the xor value of the sign bit of the decoding information corresponding to the kth bit of the ith row of the valid block, so as to obtain the xor value of the sign bit of the decoding information corresponding to the kth bit of the ith row of the updated valid block.

In a fourth aspect, a communication device is provided, the communication device comprising a decoder, a transceiver, and a demodulator; the decoder is provided in the second aspect or the third aspect; a transceiver for receiving an analog signal; a demodulator for converting the analog signal into a digital signal so that the decoder decodes the digital signal; the digital signal includes an LDPC code.

In a fifth aspect, a communication device is provided, the communication device comprising a decoder and a memory; the decoder is provided in the second aspect or the third aspect; the memory is used for storing the data decoded by the decoder.

In a sixth aspect, a computer readable storage medium is provided for storing a computer program comprising instructions for performing the decoding method in any one of the possible implementations of the first aspect.

In a seventh aspect, there is provided a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the decoding method in any of the possible implementations of the first aspect.

Drawings

FIG. 1a is a schematic diagram of a storage application according to an embodiment of the present application;

fig. 1b is a schematic diagram of a network architecture according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a storage application according to another embodiment of the present application;

FIG. 3 is a schematic diagram of a check matrix according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a check matrix according to another embodiment of the present application;

FIG. 5 is a schematic diagram of a check matrix according to another embodiment of the present application;

FIG. 6 is a schematic diagram of a check matrix according to another embodiment of the present application;

fig. 7 is a schematic structural diagram of a decoder of an LDPC code according to an embodiment of the present application;

fig. 8 is a flowchart of a decoding method of an LDPC code according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a check matrix according to another embodiment of the present application;

Fig. 10 is a flowchart illustrating a decoding method of an LDPC code according to another embodiment of the present application;

FIG. 11 is a flow chart illustrating a decoding method of LDPC codes;

fig. 12 is a schematic structural diagram of a decoder of an LDPC code according to another embodiment of the present application.

Reference numerals:

a 10-decoder; 11-a processor; 12-memory; 13-communication lines; 14-a communication interface; a 100-CNU logic calculation unit; 200-VNU logic computation unit; 300-memory cell; 400-updating unit; 500-initializing unit.

Detailed Description

The following description of the technical solutions according to the embodiments of the present application will be given with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

The embodiment of the application can be used for all devices which apply NAND as a storage medium, such as CF (compact flash) cards, eMMC (embedded multi media card ), UFS (universal flash storage, universal flash memory storage), SSD (solid state drive, solid state disk), flash (flash memory) arrays and the like.

An embodiment of the present application provides an architecture of a storage application, as shown in fig. 1a, where the architecture of the storage application may include a host, a controller, and a memory. The controller and the memory may be in the same device or may be separate devices. The controller may be a NAND controller and the memory may be a NAND memory. NAND memory includes grains that employ NAND as a storage medium. The host may be connected to the front end of the NAND controller through various interfaces such as non-volatile memory protocol (non-volatile memory express, NVMe), serial SCSI (SAS), high-speed serial computer expansion bus standard (peripheral component interconnect express, PCIe), eMMC (embedded multi media card ), and UFS (universal flash storage, universal flash storage). The host may be, for example, a CPU (central processing unit ). The back end of the NAND controller may be connected to the NAND memory through an open NAND flash memory interface (open nAND flash interface, ONFI) or Toggle interface. The host can perform operations such as reading, writing, erasing and the like on data in the NAND memory through the NAND controller. Wherein the data can be encoded and decoded by ECC (error correction code ) in the NAND controller to ensure that the data read from the NAND memory is correct.

The NAND controller may include, among other things, an interface to communicate with a host, a decoder, a processor, and an interface to communicate with a NAND memory. It should be noted that only a part of the sub-modules related to the decoder are shown in the architecture 30 of fig. 1a, and the NAND controller may further include other sub-modules.

Correspondingly, the NAND controller can also comprise an encoder, and the host can write the data in the NAND memory through the encoder. The memory may store data decoded by the decoder and data encoded by the encoder.

The embodiment of the application also provides a network architecture, as shown in fig. 1b, which may include a transmitting end, a channel and a receiving end. The transmitting end transmits a signal onto the channel and the receiving end receives the signal from the channel. The transmitting end comprises an encoder, a modulator and a transceiver, and the receiving end comprises a transceiver, a decoder and a demodulator. The transceiver is used for receiving the analog signal, the modulator is used for converting the digital signal into the analog signal, and the demodulator is used for converting the analog signal into the digital signal so that the decoder decodes the digital signal.

The transmitting end and the receiving end may be, for example, computers, switches, routers, hubs, gateways, and the like. The channels may be wireless or may be wired links, such as coaxial cables.

Taking the network architecture shown in fig. 1b as an example, since the signal received by the receiving end is affected by channel fading, interference, noise, etc., and the information transmission is distorted, coding technology is generally adopted to improve the reliability of the information transmission. The transmitting end may encode the information sequence (i.e., the user data) by an encoder, and then the modulator may modulate the encoded data, and transmit the modulated data through the transceiver. The receiving end can receive the data transmitted by the channel through the transceiver, demodulate the received data through the demodulator, send the received data to the decoder again, according to the encoding method of the information sequence by the transmitting end, the decoder can decode the received data, so as to reliably recover the original information sequence, and store the recovered original information sequence in the memory. The coding method must be visible to both transceiver ends. In general, the encoding process is based on forward error correction encoding, in which some redundant information (i.e., the test data obtained by encoding) is added to the information sequence, which can be used by the receiving end to reliably recover the original information sequence.

Since the LDPC code in the forward error correction coding is a linear block code which can be defined by a very sparse parity check matrix, the low-complexity coding and decoding can be realized only by utilizing the sparsity of the parity check matrix, and the LDPC code is the channel coding with the best performance at present, and the performance is very close to the Shannon limit. Thus, the encoder may be an encoder of an LDPC code, and the decoder may be a decoder of an LDPC code. In this way, when the transmitting end encodes the information sequence, the encoder in the transmitting end can encode the information sequence according to the check matrix of the LDPC code to obtain the codeword of the LDPC code, the codeword of the LDPC code comprises the information sequence and the check data, and when the receiving end decodes the codeword of the received LDPC code, the receiving end can decode the codeword of the received LDPC code according to the check matrix of the LDPC code.

As an example, as shown in fig. 2, codewords of the LDPC code stored in the nand_flash may be transmitted to a decoder of the LDPC code through an NFI interface, the decoder of the LDPC code restores an original information sequence using the received codewords of the LDPC code and a check matrix of the stored LDPC code, and transmits the restored original information sequence to a front end (the front end may be an interface, for example) through which the original information sequence may be transmitted to a host to perform a subsequent operation.

The check matrix of the LDPC code is a check matrix which is pre-agreed according to the specific requirement of the receiving end, namely, the check matrix which is pre-arranged between the receiving end and the transmitting end.

The check matrix (may also be referred to as a decoding matrix) corresponding to the LDPC code is a sparse matrix, and the check matrix H includes a plurality of submatrices. Among them, the QC-LDPC (quasi-cyclic-LDPC) code is a sub-class of LDPC codes. At present, an MP (message passing) algorithm based on QC-LDPC codes is generally adopted for iterative decoding of the LDPC codes. The size of QC determines the size of each sub-matrix in the check matrix H, and if qc=z, the size of each sub-matrix in the check matrix H is zxz. For example, if qc=256, the size of each sub-matrix in the check matrix is 256×256. Further, if qc=z, each sub-matrix includes z bits or z bits.

Taking qc=256 as an example, a check matrix H of a typical QC-LDPC code is shown in fig. 3. In the check matrix shown in fig. 3, -1 represents an invalid block, i.e., represents an all-zero matrix, and the other numbers represent an effective block having an offset value equal to the value, i.e., represent a non-all-zero matrix, the effective block (or non-all-zero matrix) being a matrix obtained by circularly right-shifting the number of bits of the offset value by a unit matrix having a size of 256×256.

It should be noted that, the check matrix H of the QC-LDPC code provided in the embodiment of the present application may be a matrix in which the difference value of the offset values of two adjacent effective blocks in each row is not a fixed value, for example, fig. 3 is a check matrix H with qc=256, in which the difference value of the offset values of two adjacent effective blocks in the first row is 253, 87, 4, respectively, and the difference value of the offset values of two adjacent effective blocks in the second row is 43, 121, 232, 0, respectively.

The check matrix H of the QC-LDPC code provided in the embodiment of the present application may also be a matrix in which the difference between the offset values of two adjacent effective blocks in each row is a fixed value, for example, fig. 4 is a check matrix with qc=256, where the difference between the offset values of two adjacent effective blocks in each row in the check matrix H is the same, and in the check matrix H, the difference between the offset values of two adjacent effective blocks in each row from the first row to the sixth row is 5, 2, 1, 4, 6, and 3, respectively. For another example, fig. 5 shows a check matrix with qc=7, where the difference between the offset values of two adjacent effective blocks in each of the first row to the third row is 0, 1, and 2, respectively.

Based on the two types of check matrices H provided above, whether the difference value of the offset values of the two adjacent effective blocks in each row is a check matrix H with no fixed value or a check matrix H with the difference value of the offset values of the two adjacent effective blocks in each row is a fixed value, invalid blocks may exist in the two types of check matrices H or may not exist in the two types of check matrices H. For example, an invalid block exists in the check matrix H provided in fig. 3 and 4. For another example, no invalid block exists in the check matrix H provided in fig. 5.

Taking the check matrix H shown in fig. 5 as an example, each sub-matrix in the check matrix H shown in fig. 5 is represented by 0 and 1, and then, as shown in fig. 6, each sub-matrix blank in fig. 6 represents 0.

The following describes in detail a decoding method of an LDPC code and a decoder of the LDPC code according to embodiments of the present application with reference to the accompanying drawings. The decoding method of the LDPC code and the decoder of the LDPC code provided by the embodiment of the application are applied to a communication device, and the communication device can be the NAND controller or the receiving end.

The decoder of the LDPC code is described in detail below.

Fig. 7 is a schematic structural diagram of a decoder of an LDPC code according to an embodiment of the present application. As shown in fig. 7, the decoder 10 of the LDPC code includes a processor 11, a memory 12, a communication line 13, and a communication interface 14.

The processor 11 may be a central processing unit, but may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. In addition, the decoder 10 of the LDPC code may include one or more processors 11.

The communication line 13 may be a circuit that connects the memory 12 and the processor 11 to each other and transfers information between the memory 12 and the processor 11.

The communication interface 14 is used for communication with other devices. In an embodiment of the present application, the communication interface 14 may be a module, a circuit, a bus, an interface, a transceiver, or other device capable of implementing a communication function for communicating with other apparatuses. Alternatively, when the communication interface 14 is a transceiver, the transceiver may be a separately configured transmitter that may be used to transmit information to other devices, or a separately configured receiver that may be used to receive information from other devices. The transceiver may also be a component that integrates the functions of transmitting and receiving information, and embodiments of the present application are not limited to the specific implementation of the transceiver. In addition, decoder 10 of the LDPC code may include one or more communication interfaces 14.

The memory 12 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), direct RAM (DR RAM), or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer.

The memory 12 may be independent, and in this case, the memory 12 and the processor 11 may communicate with each other through the communication line 13. The memory 12 may also be integrated with the processor 11. Fig. 7 is a schematic diagram illustrating an example in which the memory 12 and the processor 11 are independent of each other.

The memory 12 is used for storing computer-executable instructions for implementing the solution of the present application, and is controlled to be executed by the processor 11. The processor 11 is configured to execute computer instructions stored in the memory 12, thereby implementing a decoding method of an LDPC code according to the following embodiment of the present application.

It should be understood that the memory 12 described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

Alternatively, the computer-executable instructions in the embodiments of the present application may be referred to as application code, instructions, computer programs, or other names, and the embodiments of the present application are not limited in detail.

In a particular implementation, as one embodiment, processor 11 may include one or more CPUs, such as CPU0 and CPU1 of FIG. 7.

In a specific implementation, as an embodiment, the decoder 10 may include a plurality of processors, such as the processor 11a and the processor 11b in fig. 7. Each of these processors may be a single-core (single-CPU) processor or may be a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).

It should be noted that, the decoder of the LDPC code may be a general device or a special device, and the embodiment of the present application is not limited to the type of the decoder of the LDPC code. The structure of the decoder of the LDPC code shown in fig. 7 does not constitute a limitation of the decoder of the LDPC code, and an actual decoder of the LDPC code may include more or less components than illustrated, or may combine some components, or may be different in arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The following describes in detail the decoding method of the LDPC code provided in the embodiment of the present application. The decoding method of the LDPC code provided by the embodiment of the application, as shown in FIG. 8, comprises the following steps:

s10, initializing the decoding parameters and the decoding information.

The decoding parameters include maximum iteration number MAX_ITR, current iteration number q, column j where the current decoding effective block is located, and row i where the current decoding effective block is located.

The decoding information comprises a first log-likelihood ratio LLR (log-likelihood ratio), an exclusive OR value CN_sgn of sign bits of the decoding information, a sign bit V2C_sgn of a value transmitted to a check node by a variable node, a minimum value min1_old of a last iteration, a minimum value min2_old of a last iteration, a minimum value min1_new of a current iteration, a minimum value min2_new of the current iteration, first flag information bitmap1 and second flag information bitmap2. Wherein, bitmap1 indicates whether the minimum value is updated; bitmap2 indicates whether the next-smallest value has been updated.

In the embodiment of the present application, for example, if the minimum value is updated, the first flag information bitmap1 is recorded as a second preset value, for example, "1"; if the minimum value is not updated, the first flag information bitmap1 is recorded as a first preset value, for example, "0". If the next smaller value is updated, the second flag information bitmap2 is recorded as a second preset value, for example, "1"; if the next smallest value is not updated, the second flag information bitmap2 is recorded as a first preset value, for example, "0".

In some embodiments of the present application, the sign bit of a positive number may be represented by a "0" and the sign bit of a negative number may be represented by a "1", so that the exclusive or represented by sign bits 0 and 1 is equivalent to the product represented by the signs "+" and "-".

When the decoding parameters are initialized, the maximum iteration number max_itr can be set according to the requirement. For example, the maximum number of iterations max_itr may be set to 10. In some examples, the current iteration number q may be initialized to 1, the current decoding column j may be initialized to 1, or, when the check matrix H includes n columns of valid blocks, the current decoding column j may be initialized to n, and the row i in which the current valid block is located may be initialized to 1.

The initializing of the decoding information includes initializing a first log confidence coefficient LLR corresponding to each bit (i.e., each bit) of each column of the effective block in the check matrix of the LDPC code, an exclusive or value cn_sgn of a sign bit of the decoding information corresponding to each bit of each row of the effective block, a sign bit v2c_sgn of a value transmitted to the check node by a variable node corresponding to each bit of each effective block, first flag information bitmap1 and second flag information bitmap2 corresponding to each bit of each effective block, a minimum value min1_old of a last iteration corresponding to each bit of each row of the effective block, a minor value min2_old of a last iteration, a minimum value min1_new of a current iteration, and a minor value min2_new of a current iteration.

For convenience of explanation, the first pair of log confidence LLRs corresponding to the kth bit of the jth row of valid blocks are represented by llr_j (k), the second pair of log confidence LLRs corresponding to the kth bit of the jth row of valid blocks are represented by llr_new_j (k), the exclusive or value cn_sgn of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks is represented by cn_sgn_ { i (k), the variable node corresponding to the kth bit of the ith row of valid blocks is transmitted to the sign bit v2c_sgn of the value of the check node and is represented by v2c_sgn_ i, j (k), the first sign information corresponding to the kth bit of the ith row of valid blocks is represented by bit 1_ i, j } (k), the second sign bit corresponding to the kth bit of the ith row of valid blocks is represented by bit 1_ i_, and the second sign bit corresponding to the kth bit of the ith row of valid blocks is represented by value of bit 1_ k, and the value of the (k) is represented by iteration 2c_sgn_ j_ j { i, and the value of the (k) is smaller than the value of the (k) is represented by iteration 2 m_ 1_ k) corresponding to the kth bit of the value of the current iteration (k 2_ 1).

How the decoding information is initialized is described in detail below.

In some examples, when initializing the LLR corresponding to each bit of each column of the valid block in the check matrix of the LDPC code, the LLR corresponding to each column of the valid block in the check matrix of the LDPC code may be initialized to codeword information of a column corresponding to the check matrix received by the channel, where the codeword information of the column corresponding to the check matrix received by the channel includes QC bits, and each column of the valid block includes QC bits. Since each bit of the codeword information corresponds to each bit of the valid block one by one, for example, the first bit of the codeword information corresponds to the first bit of the valid block, and the second bit of the codeword information corresponds to the second bit of the valid block, which are not listed here one by one, the LLR corresponding to each bit of each column of the valid block in the check matrix of the LDPC code can be initialized to the information of the corresponding bit in the codeword information of the corresponding column of the check matrix received by the channel.

In some examples, when initializing the xor value cn_sgn of the sign bit of the decoding information corresponding to each bit of each row of valid block, the initialized cn_sgn may be obtained by calculating the initialized LLR, specifically, the cn_sgn is obtained by performing the cyclic left shift of the valid block offset for each row of the sign (may be represented by "0" or "1") of the LLR corresponding to all valid blocks.

A specific example is provided below to describe in detail the initialization process of cn_sgn. It is assumed that the LLR for each bit of each column of valid block in the check matrix H is initialized as shown in fig. 9.

For the first row of effective blocks, the offset of each effective block is 0, and the calculating process of CN_sgn corresponding to the first row of effective blocks is as follows:

the corresponding cn_sgn {1} (1) of bit 1 of the first row of valid blocks (i.e., i=1, k=1) is:

where sgn (llr_1 (1)) represents the sign bit of llr_1 (1), and sgn (llr_1 (1))=0 if llr_1 (1) =7; if llr_ {1} (1) = -7, sgn (llr_ {1} (1)) =1,representing exclusive or.

Taking the LLR for each bit of each column of valid blocks in the check matrix H shown in figure 9 as an example,

the corresponding cn_sgn_ {1} (2) of bit 2 of the first row of valid blocks (i.e., i=1, k=2) is:

the corresponding cn_sgn_ {1} (3) of the 3 rd bit (i.e., i=1, k=3) of the first row of valid blocks is:

and so on, and will not be described in detail herein.

For the second row of effective blocks, the offset of each effective block is 1, and the calculating process of CN_sgn corresponding to the second row of effective blocks is as follows:

the corresponding cn_sgn_ {2} (1) of bit 1 of the second row of valid blocks (i.e., i=2, k=1) is:

the cn_sgn {2} (2) corresponding to bit 2 of the second row of active blocks (i.e., i=2, k=2) is:

The corresponding cn_sgn {2} (3) of bit 3 of the second row of active blocks (i.e., i=2, k=3) is:

and so on, and will not be described in detail herein.

For the third effective block, the offset of each effective block is 2, and the calculating process of cn_sgn corresponding to the third row effective block is as follows:

the corresponding cn_sgn_ {3} (1) of bit 1 of the third row of valid block (i.e., i=3, k=1) is:

the corresponding cn_sgn {3} (2) of bit 2 of the third row of active block (i.e., i=3, k=2) is:

the corresponding cn_sgn {3} (3) of bit 3 of the third row of active block (i.e., i=3, k=3) is:

and so on, and will not be described in detail herein.

In some examples, when initializing the sign bit v2c_sgn of the value transmitted to the check node by the variable node corresponding to each bit of each valid block, if the decoding is soft-decision decoding, the sign bit v2c_sgn of the value transmitted to the check node by the variable node corresponding to each bit of each valid block is initialized to 0; if the decoding is hard decision decoding, the sign bit v2c_sgn of the value transmitted from the variable node corresponding to each bit of all valid blocks in each column to the check node is initialized to the sign bit of the LLR of the corresponding bit in the column, i.e., v2c_sgn_ { i, j } (k) =sgn (llr_ { j } (k)).

It should be understood that the codeword information received by the channel is divided into soft decision information and hard decision information according to the type of channel detection, and if the soft decision information received by the channel, that is, the LLR received by the channel is a non-fixed value, that is, the absolute value of the LLR received by the channel is a non-constant value, the decoding is soft decision decoding; if the channel received is hard decision information, that is, the LLR received by the channel is a fixed value, that is, the absolute value of the LLR is a constant, the decoding is hard decision decoding. If the decoding is hard decision decoding, for example, the variable node corresponding to the 1 st bit of the 1 st column and 1 st row of the valid block transmits the sign bit v2c_sgn_ 1,1} (1) =sgn (llr_ 1} (1)) of the value of the check node; the 1 st bit of the valid block of the 1 st column and the 2 nd row corresponds to the sign bit v2c_sgn_ {2,1} (1) =sgn (llr_ {1} (1)) of the value that the variable node transmits to the check node. For another example, the variable node corresponding to the 1 st bit of the valid block of the 3 rd row and 5 th column transmits the sign bit v2c_sgn_ {3,5} (1) =sgn (llr_ {5} (1)) of the value of the check node.

In some examples, the first flag information bitmap1 and the second flag information bitmap2 corresponding to each bit of each valid block may be initialized to a first preset value "0".

In some examples, when initializing the minimum value min1 new of the current iteration and the minor value min2 new of the current iteration corresponding to each bit of each row of the valid block, the minimum value min1 new of the current iteration and the minor value min2 new of the current iteration corresponding to each bit of each row of the valid block may be initialized to the decoding information maximum quantization value max. For example, if the decoding information includes 3 bits, the maximum quantization value of the decoding information is 7.

In some examples, when initializing the minimum value min1_old of the last iteration and the next minimum value min2_old of the last iteration corresponding to each bit of each row of the valid block, if the decoding is soft-decision decoding, initializing each of min1_old and min2_old corresponding to each bit of each row of the valid block to be 0; if the decoding is hard decision decoding, initializing the min1_old and the min2_old corresponding to each bit of each row of effective block as the maximum quantization value max of the decoding information.

It should be noted that the step S10 is performed only before the current decoding column j is initialized to 1 (i.e., decoding starts from the valid block of column 1) and the first iteration is performed on the valid block of column 1, or before the current decoding column j is initialized to n (n is the last column, i.e., decoding starts from the valid block of the last column) and the first iteration is performed on the valid block of column n, and otherwise, the step S10 is not performed.

It should be understood that, when decoding, the LDPC code is decoded sequentially according to the check matrix H by columns, and the decoding process of the LDPC code will be described in detail below by taking the kth bit of the ith row effective block of the jth column as an example, and the decoding process of other columns is the same as the decoding process of the jth column, and reference may be made to the decoding process of the jth column.

S11, updating the minimum value min1_old_ { i (k) of the kth bit of the ith row effective block of the last iteration and the next minimum value min2_old_ { i (k) of the kth bit of the ith row effective block of the last iteration according to the first flag information bit1_ { i, j (k) and the second flag information bit2_ { i, j (k) corresponding to the kth bit of the ith row and jth column effective block of the check matrix of the LDPC code. Wherein, bitmap1_ { i, j } (k) represents whether the minimum value of the kth bit of the jth column effective block of the ith row is updated; bitmap2_ { i, j } (k) indicates whether the next smallest value of the kth bit of the jth column active block of the ith row has been updated.

In some examples, updating the min 1_old_i (k) and the min 2_old_i (k) according to the bitmapped 1_i, j (k) and bitmapped 2_i, j (k) corresponding to the kth bit of the ith row and jth column active block of the check matrix of the LDPC code specifically includes: if the first flag information bitma1_i, j (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block is updated, and the second flag information bitma2_i, j (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the next-small value corresponding to the kth bit of the ith row and jth column effective block is updated, that is, if bitma1_i, j (k) = = bit2_i, j (k) = 1, then the min 1_old_i (k) and the min 2_old_i (k) are updated, the update result is that the min 1_old_i (k) is updated to the min 2_old_i (k), and the min2_old (k) is updated to the min 2_old_i (k) = 2_max (k) = 1; wherein max is the maximum quantization value of the decoding information.

If the second flag information bitmap2_i, j (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the next smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, the first flag information bitmap1_i, j (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the smallest value corresponding to the kth bit of the ith row and jth column effective block is not updated, that is, bitmap1_i, j (k) =0 (i.e., bitmap1_i, j (k) |=1), bitmap2_i, j (k) = =1, the min 1_old_i (k) is not updated, and the min 2_old_i (k) is updated, with the result that the min 2_d_old i (k) is updated to the min 2_old_i (k) = { max (k) { 2_max (k) { 1).

If the first flag information bitmap1_i, j (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block is not updated, and the second flag information bitmap2_i, j (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is not updated, that is, bitmap1_i, j (k) = { bitmap2_i, j } (k) = = 0 (i.e., bitmap1_i, j (k) = 1, bitmap2_i, j } (k) = 1), then the second flag information bitmap1_old_i (k) and min2_old { i (k) are not updated.

When decoding the j-th column valid block, the min1_old and the min2_old corresponding to each row of valid blocks may be updated at the same time, or the min1_old and the min2_old corresponding to each row of valid blocks may be updated sequentially row by row. In addition, for each valid block, the corresponding min1_old and min2_old of each bit may be updated simultaneously or may be updated sequentially.

S12, obtaining a minimum value min_ { i } (k) of a kth bit of an ith row effective block; the smallest value min_ { i } (k) of the kth bit of the ith row of effective block is the smaller one of the smallest value min1_new_ { i } (k) of the kth bit of the ith row of effective block of the present iteration and the smallest value min1_old_ { i } (k) of the kth bit of the last iteration after updating, namely min_ { i } (k) =minimum (min 1_old_ { i } (k), min1_new_ { i } (k)), and min1_new_ { i } (k) represent the smallest value of the kth bit of the ith row of effective block of the present iteration; minimum () represents taking the minimum value.

When decoding the j-th column of valid blocks, the min corresponding to each row of valid blocks may be calculated simultaneously, or the min sequence corresponding to each row of valid blocks may be calculated row by row. In addition, for each valid block, the min corresponding to each bit may be calculated at the same time, or may be calculated sequentially.

After step S12, the decoding method further includes obtaining a value V2c_ { i, j } (k) of the variable node of the kth bit of the ith row and jth column valid block transmitted to the check node according to the minimum value min_ { i } (k) of the kth bit of the ith row and valid block. The following steps S13 to S16 describe in detail the process of obtaining the value V2c_ { i, j } (k) of the variable node at the kth bit of the ith row and jth column effective block to the check node from the minimum value min_ { i } (k) at the kth bit of the ith row effective block.

S13, updating an exclusive OR value CN_sgn_ { i } (k) of sign bits of decoding information corresponding to the kth bit of the ith row of effective blocks.

In some examples, the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks is updated, which may specifically be:

and carrying out exclusive OR on the exclusive OR value CN_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block and the sign bit V2C_sgn_ { i, j } (k) of the value transmitted to the check node by the variable node of the kth bit of the ith row effective block, so as to obtain the exclusive OR value CN_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the updated ith row effective block. That is, cn_sgn_2{i (k) can be calculated according to the formula cn_sgn_2{i (k) =cn_sgn_ 1{i (k) v2c_sgn_ { i, j } (k); wherein, CN_sgn_1{i } (k) represents the exclusive OR value of the sign bit of the decoding information corresponding to the kth bit of the ith row of effective blocks before updating; cn_sgn_2{i } (k) represents an exclusive or value of sign bits of decoding information corresponding to a kth bit of the updated ith row effective block; representing exclusive or.

For example, if cn_sgn_1{1} (1) =1, v2c_sgn_ {1,1} (1) =0, cn_sgn_2{i } (k) =1 +_0=1.

When decoding the j-th column effective block, updating the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the k-th bit of the i-th row effective block, the exclusive or value cn_sgn of the sign bit of the decoding information corresponding to each row of effective block may be updated simultaneously; the exclusive or value cn_sgn of the sign bit of the decoding information corresponding to each row of valid blocks may also be updated sequentially row by row. In addition, for an effective block, the cn_sgn corresponding to each bit in the effective block may be updated at the same time, or the cn_sgn corresponding to each bit in the effective block may be acquired sequentially.

In addition, the step S12 and the step S13 may be performed in the order in which the step S12 and the step S13 are performed first; step S13 may be performed first, and then step S12 may be performed.

S14, calculating the value C2V_ { i, j } (k) of the check node transmission to the variable node of the kth bit of the ith row and jth column effective block according to the minimum value min_ { i } (k) of the kth bit of the ith row effective block calculated in the step S12 and the exclusive OR value CN_ sgn_ { i (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block updated in the step S13.

In some examples, the value c2v_ i, j (k) that the check node at the kth bit of the jth valid block transmits to the variable node is calculated according to the minimum value min_ { i (k) of the kth bit of the ith valid block and the exclusive or value cn_sgn_ { i (k) of the sign bit of the decoding information corresponding to the kth bit of the updated ith valid block, which may specifically be:

firstly, mapping an exclusive OR value CN_sgn_ { i } (k) of sign bits of decoding information corresponding to a kth bit of the updated ith row effective block into a positive sign or a negative sign, namely, mapping CN_sgn_ { i } (k) into mapping (CN_sgn_ { i }); where mapping () means taking a positive or negative sign.

For example, if cn_sgn_j_i (k) =0, mapping (cn_sgn_j_i (k)) represents a positive sign "+". If cn_sgn_i (k) =1, mapping (cn_sgn_i (k)) represents a negative sign "-".

Next, the positive sign or negative sign mapped is multiplied by the minimum value min_ { i } (k) of the kth bit of the ith row effective block to obtain the value c2v_ { i, j } (k) of the kth bit check node transfer to variable node of the ith row jth column effective block, that is, c2v_ { i, j } (k) =mapping (cn_sgn_ { i } (k)) ×min_ { i } (k) is calculated according to the formula c2v_ { i, j }.

For example, if mapping (cn_sgn_ { i } (k)) represents "-", min_ { i } (k) is 1, then c2v_ { i, j } (k) = -1.

When decoding the valid blocks in the j-th column, the C2V corresponding to each valid block in the j-th column may be calculated at the same time; the C2V corresponding to all valid blocks of the j-th column may also be calculated in a row-by-row order. In addition, for a valid block, the C2V corresponding to each bit in the valid block may be calculated at the same time, or the C2V corresponding to each bit in the valid block may be calculated sequentially.

S15, calculating a second pair of the confidence coefficient LLR_new_j (k) corresponding to the kth bit of the jth column of effective blocks according to the first pair of the confidence coefficient LLR_j (k) corresponding to the kth bit of the jth column of effective blocks and the value C2V of the variable nodes transmitted to the check nodes corresponding to all the jth column of effective blocks.

In some examples, calculating the second pair of log-confidence llr_new_j (k) corresponding to the kth bit of the jth column of valid blocks from the first pair of log-confidence llr_j (k) corresponding to the kth bit of the jth column of valid blocks and the value C2V of the check nodes corresponding to all the jth column of valid blocks transferred to the variable nodes specifically includes:

and adding the value C2V of the check node corresponding to all the valid blocks in the j-th row to the variable node and the first pair of confidence coefficient LLR_ { j } (k) corresponding to the k-th bit of the valid blocks in the j-th row according to the bits to obtain a second pair of confidence coefficient LLR_new_ { j } (k) corresponding to the k-th bit of the valid blocks in the j-th row.

For example, llr_new_j (k) =llr_j (k) +c2v_1, j (k) +c2v_2, j (k) +c2v_3, j (k).

S16, calculating a value V2 V_ { i, j } (k) of the variable node of the kth bit of the ith row and jth column effective block transmitted to the check node according to a value C2V_ { i, j } (k) of the check node of the kth bit of the ith row and jth column effective block transmitted to the variable node and a second pair of confidence coefficient LLR_new_ { j } (k) corresponding to the kth bit of the jth column effective block.

In some examples, calculating the value v2v_ { i, j } (k) of the variable node of the kth bit of the jth valid block of the ith row and the jth valid block from the value c2v_ { i, j } (k) of the variable node of the kth bit of the jth valid block and the second pair of log confidence values llr_new_ { j } (k) corresponding to the kth bit of the jth valid block, specifically includes: subtracting the value C2v_ { i, j } (k) of the variable node transmission to the check node of the kth bit of the jth row and jth column effective block from the second pair of log confidence values llr_new_ { j } (k) corresponding to the kth bit of the jth row and jth column effective block to obtain the value V2c_ { i, j } (k) of the variable node transmission to the check node of the kth bit of the jth row and jth column effective block, namely calculating V2c_ { i, j } (k) according to the formula V2c_ { i, j } (k) =llr_new_ j (k) -C2v_ { i, j }).

It should be noted that, when decoding the valid block in the j-th column, V2C corresponding to each valid block in the j-th column may be calculated at the same time; V2C for each valid block in column j may also be calculated in row-by-row order. In addition, for a valid block, V2C corresponding to each bit in the valid block may be calculated simultaneously; the V2C corresponding to each bit in the valid block may also be calculated sequentially.

S17, updating an exclusive OR value CN_sgn_ i (k) of sign bits of decoding information corresponding to the kth bit of the ith row effective block, a minimum value min1_new_ i (k) of the kth bit of the ith row effective block of the iteration, a next small value min2_new_ i (k) of the kth bit of the ith row effective block of the iteration, first sign information bitmap1_ i, j (k) corresponding to the kth bit of the ith row and jth column effective block, and second sign information bitmap2_ i, j (k) corresponding to the kth bit of the ith row and jth column effective block according to a value V2C_ i, j (k) of the kth bit of the ith row and jth column effective block, which is transmitted to a check node by a variable node of the kth bit of the ith row and jth column effective block of the ith row.

In some examples, updating the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row valid block according to the value V2c_ { i, j } (k) of the variable node of the kth bit of the ith row and jth column valid block transferred to the check node, specifically includes:

and carrying out exclusive or on the variable node of the kth bit of the ith row and the jth column of the effective block and the exclusive or value CN_sgn_ { i (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row and the variable node of the kth bit of the ith row and the effective block to obtain an exclusive or value CN_sgn_ { i (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row and the effective block after updating. That is, according to the formula v2c_sgn_ i, j } (k) =sgn (v2c_ { i, j } (k)) and the formula Updating CN_sgn_ { i } (k); where v2c_sgn_ { i, j } (k) represents the sign bit of v2c_ { i, j } (k), sgn () represents the sign bit.

In some examples, updating the minimum value min1_new_i (k) of the kth bit of the ith row of valid blocks in this iteration, the next minimum value min2_new_i (k) of the kth bit of the ith row of valid blocks in this iteration, the first flag information bitmap1_i, j (k) corresponding to the kth bit of the ith row of valid blocks, and the second flag information bitmap2_i, j (k) corresponding to the kth bit of the ith row of valid blocks according to the value v2c_i, j (k) of the kth bit of the ith row of valid blocks transferred to the check node by the variable node of the kth bit of the jth row of valid blocks in the ith row of valid blocks, specifically includes:

if the absolute value of the variable node of the kth bit of the ith row and jth column effective block transmitted to the check node is smaller than the minimum value of the kth bit of the ith row and effective block, namely, MIN1_new_i (k), the next-smallest value of the kth bit of the ith row and effective block, namely, MIN2_new_i (k), is updated to the minimum value of the kth bit of the ith row and effective block, namely, MIN1_new_i (k), and the minimum value of the kth bit of the ith row and effective block, namely, MIN1_new_i (k), is updated to the value of the variable node of the kth bit of the ith row and effective block transmitted to the check node, namely, V2C_i, j (k), and the first flag information corresponding to the kth bit of the ith row and jth column effective block, namely, is set to the preset value of the first flag information, namely, MIN1_new_new_i (k) and the second flag information, namely, the value of the kth bit is set to be equal to the value of the first flag information. That is, ABS (v2c_ { i, j } (k)) < min1_new_ { i } (k), then min2_new_ { i } (k) is updated to min1_new_ { i } (k), min1_new_ { i } (k) is updated to ABS (v2c_ { i, j } (k)), both bitmap1_ { i, j } (k) and bitmap2_ { i, j } (k) are updated to "1", that is, min2_new_ { i } (k) =min 1_new_ { i } (k), min1_new_ { i } (k) =abs (V2 c_ { i, j } (k)), bitmap1_ { i, j } (k) =bitmap 2 { i, j } =1.

If the absolute value V2C_ { i, j } (k) of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is greater than the minimum value min1_new_ { i (k) of the kth bit of the ith row and less than the next-small value min2_new_ { i (k) of the kth bit of the ith row and effective block, the next-small value min2_new_ { i (k) of the kth bit of the ith row and effective block of the present iteration is updated to the absolute value of the value V2C_ i, j } (k) transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, and the first flag information bit 1_ i, j } (k) corresponding to the kth bit of the ith row and jth column effective block of the present iteration is updated to the first preset value "0", and the second flag information bit 2_ i is updated to the second preset value of { 1_. That is, if min1_new_i (k) < ABS (v2c_ { i, j (k)) < min2_new_i (k), then min2_new_i (k) is updated to ABS (v2c_ { i, j (k)), min1_new_i (k) is unchanged, bitmap1_i, j (k) is updated to "0", bitmap2_i, j (k) is updated to "1", that is, min2_new_i (k) =abs (v2c_i, j (k)), bitmap1_i, j (k) =0, bitmap2_i, j (k) =1.

If the absolute value of the value V2C_ { i, j } (k) transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the next-smallest value min2_new_ { i } (k) of the kth bit of the ith row and jth column effective block in the iteration, the first flag information bitmap1_ { i, j } (k) and the second flag information bitmap2_ { i, j } (k) corresponding to the kth bit of the ith row and jth column effective block are updated to a first preset value of 0. That is, if ABS (v2c_ { i, j } (k)) > min2_new_ { i } (k), min1_new_ { i } (k) and min2_new_ { i } (k) are unchanged, both bitmap1_ { i, j } (k) and bitmap2_ { i, j } (k) are updated to 0, that is, bitmap1_ { i, j } (k) =bitmap2_ { i, j } (k) =0.

The ABS () described above represents taking an absolute value.

The min 1_new_i (k), the min 2_new_i (k), the bitmap 1_i, the j (k), and the bitmap 2_i, the j (k) corresponding to each row of valid blocks may be updated simultaneously according to v2c_i, j (k), or the min 1_new_i (k), the min 2_new_i (k), the bitmap 1_i, the j (k) corresponding to each row of valid blocks may be updated sequentially according to v2c_i, j (k). For an effective block, the corresponding min1_new_ { i } (k), min 2_new_i } (k), bitmap 1_i, j } (k), bitmap 2_i, j } (k) of each bit of the effective block may be updated simultaneously, or the corresponding min 1_new_i } (k), min 2_new_i { (k), bitmap 1_i, j } (k), bitmap 2_i, j } (k) of each bit of the effective block may be updated sequentially.

Based on the above, in the case that the check matrix H of the LDPC code includes n columns of valid blocks, if the j-th column is not the last column of the current iteration, that is, if the number of iterations is odd, the iteration starts from the 1 st column, if the number of iterations is even, the iteration starts from the n-th column, if the current iteration is odd, j is not equal to n, or if the current iteration is even, j is not equal to 1, the following step S18 is executed after S17; if the j-th column is the last column of the present iteration, that is, if the iteration number is odd, the iteration is started from the 1 st column, and if the iteration number is even, the iteration is started from the n-th column, and if the present iteration is odd, j=n, or if the present iteration is even, j=1, the following step S19 is executed after S17.

S18, carrying out cyclic shift on the minimum value min1_new of the current iteration, the next minimum value min2_new of the current iteration, the minimum value min1_old of the last iteration and the next minimum value min2_old of the last iteration, which correspond to each bit of each row of the effective block, wherein the shift quantity is equal to the offset value of the row of the effective block in the check matrix.

When decoding the j-th column of valid block, the minimum value min1_new of the current iteration, the minimum value min2_new of the current iteration, the minimum value min1_old of the last iteration, and the minimum value min2_old of the last iteration corresponding to each row of valid block may be cyclically shifted at the same time, or the minimum value min1_new of the current iteration, the minimum value min2_new of the current iteration, the minimum value min1_old of the last iteration, and the minimum value min2_old of the last iteration corresponding to the valid block may be cyclically shifted in sequence. In addition, for each effective block, the minimum value min1_new of the current iteration, the next minimum value min2_new of the current iteration, the minimum value min1_old of the last iteration and the next minimum value min2_old of the last iteration corresponding to each bit may be subjected to cyclic shift at the same time, or may be subjected to cyclic shift sequentially.

In the case that the difference value between the offset values of two adjacent effective blocks in each row of the check matrix of the LDPC code is a fixed value, in some examples, performing cyclic shift on the minimum value min1_new of the current iteration, the next minimum value min2_new of the current iteration, the minimum value min1_old of the last iteration, and the next minimum value min2_old of the last iteration corresponding to each bit of each row of the effective block specifically includes:

If the iteration starts from column 1, and if the iteration number is odd, iteration starts from column 1, and if the iteration number is even, iteration starts from column n as an example, that is, if the iteration number is odd, for example, the iteration number is 1, 3, 5, etc., the minimum value of the kth bit of the ith row of effective blocks in this iteration, min1_new_ { i } (k), is updated to the minimum value of the kth+p bit of the ith row of effective blocks in this iteration, min1_new_ { i } (k+p), and the minimum value of the kth bit of the last iteration, min1_old_ i } (k), is updated to the minimum value of the kth+p bit of the last iteration, min2_old_ i } (k+p), that is, min1_new { i } (k) _min 1_new { i } (k+p), and min1_old } = i (k+p) { i }; if the iteration starts from the last column (i.e. the nth column), and the iteration number is odd, the iteration starts from the 1 st column, and if the iteration number is even, the iteration starts from the nth column as an example, that is, if the iteration number is even, for example, 2, 4, 6, etc., when k is less than or equal to p, the minimum value min1_new_ i (k) of the kth bit of the ith row effective block of the iteration is updated to the minimum value min1_ i (t+k-p) of the (t+k) bit of the ith row effective block of the iteration, the minimum value min1_ old (k) of the kth bit of the ith row effective block of the iteration is updated to the minimum value min2_ i (t+k-p) of the (t+k-p) bit of the last iteration, that is also the minimum value min1_ k_ k-p (k) of the kth bit of the (k) th row effective block of the iteration is updated to the (k+k-p) of the (k-p) th row of the last iteration is the (k-1_ k-p) bit of the (k) th row of the iteration, that is, min1_new_i (k) =min1_new_i (k-p), min1_old_i (k) =min2_old_i (k-p); wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block.

For example, as shown in fig. 9, when the iteration starts from column 1 and the number of iterations is odd, t=7, the iteration starts from column 1 and the number of iterations starts from column n as an example, that is, when the number of iterations is odd, p=0, min1_new_1 } (1) =min1_new_1 } (1), min1_new_1 {1} (2) =min1_new_1 {1} (2), min1_new_1 {1} (3) =min1_new_1 {1} (3), and so on for the 1 st row effective block, the details are not repeated here.

min2_old_1 (1) =min 2_old_1 (1), min2_old_1 (2) =min 2_old_1 (2), min2_old_1 (3) =min 2_old_1 (3), and so on, and will not be described in detail herein.

For the 2 nd row effective block, p=1, min1_new_1 (1) =min1_new_1 (2), min1_new_1 (2) =min1_new_1 (3), min1_new_1 (3) =min1_new_1 (4), and so on, and will not be described again here.

min2_old_1 (1) =min 2_old_1 (2), min2_old_1 (2) =min 2_old_1 (3), min2_old_1 (3) =min 2_old_1 (4), and so on, and will not be described again here.

For the 3 rd row effective block, p=2, min1_new_1 (1) =min1_new_1 (3), min1_new_1 (2) =min1_new_1 (4), min1_new_1 (3) =min1_new_1 (5), and so on, and will not be described again here.

min2_old_1 (1) =min 2_old_1 (3), min2_old_1 (2) =min 2_old_1 (4), min2_old_1 (3) =min 2_old_1 (5), and so on, and will not be described again here.

When the number of iterations is even, for the 1 st row effective block, p=0, min1_new_ {1} (1) =min1_new_ {1} (1), min1_new_ {1} (2) =min1_new_ {1} (2), min1_new_ {1} (3) =min1_new_1 } (3), and so on, and will not be described in detail herein.

min2_old_1 (1) =min 2_old_1 (1), min2_old_1 (2) =min 2_old_1 (2), min2_old_1 (3) =min 2_old_1 (3), and so on, and will not be described again here.

For the 2 nd row effective block, p=1, min1_new_1 (1) =min1_new_1 (7), min1_new_1 (2) =min1_new_1 (1), min1_new_1 (3) =min1_new_1 (2), and so on, and will not be described again here.

min2_old_1 (1) =min 2_old_1 (7), min2_old_1 (2) =min 2_old_1 (1), min2_old_1 (3) =min 2_old_1 (2), and so on, and will not be described in detail herein.

For the 3 rd row effective block, p=2, min1_new_1 (1) =min1_new_1 (6), min1_new_1 (2) =min1_new_1 (7), min1_new_1 (3) =min1_new_1 (1), and so on, and will not be described again here.

min2_old_1 (1) =min 2_old_1 (6), min2_old_1 (2) =min 2_old_1 (7), min2_old_1 (3) =min 2_old_1 (1), and so on, and will not be described in detail herein.

S19, updating the minimum value of the kth bit of the last iteration ith row effective block, namely MIn1_old_ i (k), to the minimum value of the kth bit of the last iteration ith row effective block, namely MIn1_new_ i (k), namely MIn1_old_ i (k) =1_new_ i (k), and updating the minimum value of the kth bit of the current iteration ith row effective block, namely MIn1_new_ i (k), namely MIn1_old_ i (k) =2_ i (k), to the maximum quantization value of the decoding information, namely MIn1_old_ i (k) =1_new_ i (k), and updating the minimum value of the kth bit of the current iteration ith row effective block, namely MIn1_new_ i (k) and the next_ of the kth bit of the current iteration ith row effective block, namely MIn2_new_ i (k), respectively.

When decoding the j-th column of valid blocks, the min1_new, the min2_new, the min1_old, and the min2_old corresponding to each row of valid blocks may be updated simultaneously, or the min1_new, the min2_new, the min1_old, and the min2_old corresponding to the valid blocks may be updated sequentially row by row. In addition, for each valid block, the update may be performed simultaneously for the corresponding min1_new, min2_new, min1_old, and min2_old of each bit, or may be performed sequentially.

It can be understood that, when the decoding method of the LDPC code provided by the embodiment of the present application is adopted for decoding, the used check matrix H can be a matrix with the offset value difference value of two adjacent effective blocks in each row being a non-fixed value; or a matrix in which the difference between the offset values of two adjacent active blocks in each row is a fixed value. When the check matrix H is a matrix in which the difference value between the offset values of two adjacent effective blocks in each row is a fixed value, not only the decoding method can be simplified, but also the number of shift registers required in the decoding process can be greatly reduced, so that the complexity of the decoder of the LDPC code can be greatly reduced.

For example, when decoding each column of valid blocks, in step S18, the minimum value min1_new of the current iteration, the next minimum value min2_new of the current iteration, the minimum value min1_old of the last iteration, and the next minimum value min2_old of the last iteration corresponding to each bit of each row of valid blocks are circularly shifted, if the check matrix H is a matrix in which the difference value between the offset values of two adjacent valid blocks in each row is a fixed value, the shift amount of the circular shift is the same, so that the algorithm in the decoding process is simpler, and the number of the required shift registers is smaller, thereby reducing the complexity of the decoder of the LDPC code. If the check matrix H is a matrix in which the difference between the offset values of two adjacent active blocks in each row is a non-fixed value, the shift amounts of the cyclic shifts may be different, which may result in complex algorithm in the decoding process, and a large number of shift registers, i.e., a large shift register network, are required to increase the complexity of the decoder of the LDPC code.

In the embodiment of the present application, when the current decoding column is not the last column of the current iteration, the iteration is started from the 1 st column when the number of iterations is odd, and when the number of iterations is even, the iteration is started from the nth column (i.e., the last column), and if the number of iterations (which may also be referred to as the current iteration number) is odd, j=j+1; if the number of iterations is even, j=j-1. In the case where the current decoding column is the last column of the current iteration, i.e., if the number of the current iteration is odd, j=n, or if the number of the current iteration is even, j=1, the current iteration number q=q+1.

In the embodiment of the present application, there are two cases of terminating decoding, and in the first case, if the current iteration number q is greater than the maximum iteration number max_itr, decoding is terminated. Second, if the second pair of confidence coefficient llr_new corresponding to each bit of each column of the valid block is correct, that is, the exclusive or value cn_sgn of the sign bit of the decoding information corresponding to each bit of each row of the valid block is 0, the decoding is terminated. After termination of decoding, the second log-confidence level LLR_new is output as the decoding.

It is understood that after decoding the j-th column, if decoding is not terminated, steps S11 to S17 and S18 are executed again, or steps S11 to S17 and S19 are executed again.

In summary, the LDPC code is decoded according to the check matrix by columns, and each column performs VNU (variable node update ) calculation and CNU (check node update, check node update) calculation on all valid blocks in the column. The VNU calculates a first pair of confidence coefficient LLRs corresponding to column information, namely a current decoding column of the check matrix, and the CNU calculates a minimum value min 1-new of the current iteration, a second minimum value min 2-new of the current iteration, first flag information bitmap1 and second flag information bitmap2 corresponding to each bit of the row corresponding to all the effective blocks. The decoding process for each bit of each valid block is mainly: as shown in fig. 10, a value C2V of a check node transmitted to a variable node is calculated according to a minimum value min1_old of a previous iteration, a minimum value min2_old of a previous iteration, a minimum value min1_new of a current iteration, first flag information bitmap1 and second flag information bitmap 2; then, according to the value C2V of the variable node transmitted to the check node and the first pair of confidence coefficient LLRs, calculating to obtain the value V2C of the variable node transmitted to the check node and the second pair of confidence coefficient LLRs_new through VNU; next, according to the value V2C transmitted to the check node by the variable node, the minimum value min1 new of the current iteration and the sub-minimum value min2 new of the current iteration, the minimum value min1 new of the current iteration, the sub-minimum value min2 new of the current iteration, the first flag information bitmap1 and the second flag information bitmap2 are obtained through CNU calculation and updating according to the offset of the current effective block in the check matrix.

The iterative decoding of the LDPC code is complex in calculation, a large amount of data needs to be calculated and stored, and a large amount of area and power consumption cost are occupied when the LDPC code is realized by hardware. Taking SSD as an example, with the evolution of interface standard, the data bandwidth defined by PCIE (peripheral component interconnectexpress, high-speed serial computer expansion bus standard) of each generation is doubled compared with the previous generation, and the area and power consumption of LDPC modules in the controller of SSD are doubled as an adaptation protocol. And the LDPC module occupies nearly half of the power consumption of the SSD digital part, and excessive power consumption of the LDPC module can cause the exceeding of the power consumption of the SSD disk as a whole.

At present, a common decoding method of an LDPC code is similar to the decoding method of the LDPC code provided by the embodiment of the application, and the common decoding method of the LDPC code is also carried out according to the check matrix in columns during decoding, and each column carries out VNU calculation and CNU calculation on all effective blocks in the column. The VNU calculates LLR information corresponding to the column information, i.e., the current decoding column of the check matrix, and the CNU calculates row information. The difference is that, as shown in fig. 11, when decoding each column of valid blocks by using a common decoding method of the LDPC code, the CNU calculates updated row information to refer to a minimum value min1 value, a next-minimum value min1 value, minimum value position information min1_idx, and next-minimum value position information min2_idx corresponding to each bit of the row corresponding to all valid blocks. When decoding each column of valid blocks by using a common decoding method of the LDPC code, the minimum value min corresponding to each bit of each row of valid blocks is determined according to the minimum value min1, the sub-minimum value min2, the position information of the minimum value min1_idx and the position information of the sub-minimum value min2_idx, so that when decoding by using the common decoding method of the LDPC code, the minimum value min1, the sub-minimum value min2, the position information of the minimum value min1_idx and the position information of the sub-minimum value min2_idx corresponding to each bit of each row of valid blocks in a check matrix of the LDPC code are required to be stored. However, the storage of the minimum position information min1_idx and the next-minimum position information min2_idx requires a large bit number, which is far greater than the bit number required for storing the minimum position information min1 and the next-minimum position information min2, for example, the 4KB length LDPC code commonly used in the controller of the SSD, and the minimum position information min1_idx and the next-minimum position information min2-idx both require 8bit storage by adopting the matrix of QC256, so that a large amount of resources are required for performing the management of the position information min_idx, thereby resulting in too high decoding resources of the LDPC code and further resulting in large power consumption overhead of the area required for decoding.

According to the decoding method of the LDPC code provided by the embodiment of the application, when each column of effective blocks is decoded, the minimum value min1_old of the last iteration and the next minimum value min2_old of the last iteration can be updated according to the first mark information bitmap1 and the second mark information bitmap2, then the minimum value min corresponding to each bit of each row of effective blocks can be obtained according to the minimum value min1_old of the last iteration and the minimum value min1_new of the current iteration, so that subsequent decoding can be performed, therefore, in the decoding process of the LDPC code, the position information min1_idx of the minimum value corresponding to each bit of each row of effective blocks in a check matrix of the LDPC code and the position information min2_idx of the next minimum value do not need to be stored, the minimum value min1_old of each bit of each row of effective blocks in the LDPC code, the current iteration 2_old of the second mark information bitmap 2_idx can be stored, and the cost of the first bit of the first row of effective blocks can be reduced, and the current iteration 2 bit of the LDPC code can be reduced, and the cost of the first bit of the second bit of the LDPC code can be reduced, and the current iteration 1_new of the first bit of the LDPC code can be decoded, and the cost of the first bit of the LDPC code can be reduced, and the cost of the first bit of the LDPC code can be reduced, and the cost of the first bit of the bit can be reduced.

It will be appreciated that the decoder of the LDPC code described above, in order to implement the above-described functions, includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the present application may be implemented in hardware or a combination of hardware and computer software, as a unit and algorithm operations described in connection with the embodiments disclosed herein. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

The embodiment of the application can divide the functional modules of the decoder of the LDPC code according to the method example, for example, each functional module can be divided corresponding to each function, and two or more functions can be integrated in one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

For example, in the case where the respective functional blocks are divided in an integrated manner, fig. 12 shows a schematic diagram of a decoder of an LDPC code. The decoder of the LDPC code may be a chip or a system on a chip in the receiving end, or other combination devices, components, etc. capable of implementing the decoding function, and the decoder of the LDPC code may be used to perform the functions of the decoder of the LDPC code referred to in the foregoing embodiments.

As a possible implementation, the decoder 10 of the LDPC code shown in fig. 12 includes: CNU logic computation unit 100 and VNU logic computation unit 200. The CNU logic calculating unit 100 is configured to update, according to first flag information bitmap1_i, j (k) and second flag information bitmap2_i, j (k) corresponding to a kth bit of an ith row and a jth column of an effective block of a check matrix of the LDPC code, a minimum value min1_old_i (k) of the kth bit of the ith row effective block of the last iteration and a next minimum value min2_old_i (k) of the kth bit of the ith row effective block of the last iteration; obtaining a minimum value min_ { i } (k) of a kth bit of an ith row of effective blocks; the minimum value min_ { i } (k) of the kth bit of the ith row of effective blocks is the smaller one of the minimum value min1_new_ { i } (k) of the kth bit of the ith row of effective blocks of the present iteration and the minimum value min1_old_ { i } (k) of the kth bit of the ith row of effective blocks of the last iteration after updating. The VNU logic calculating unit 200 is configured to obtain, according to a minimum value min_ { i } (k) of a kth bit of the ith row of valid blocks, a value V2c_ { i, j } (k) that a variable node of the kth bit of the ith row of jth column of valid blocks passes to a check node; the CNU logic calculating unit 100 is further configured to update, according to the value V2c_ { i, j } (k) transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block obtained by the VNU logic calculating unit 200, the minimum value min1_new_ { i } (k) of the kth bit of the ith row and effective block in this iteration, the next minimum value min2_new_ { i } (k) of the kth bit of the ith row and effective block in this iteration, the first flag information bitmap1_ { i, j } (k) corresponding to the kth bit of the ith row and jth column effective block, and the second flag information bitmap2_ { i, j } (k) corresponding to the kth bit of the ith row and jth column effective block in this iteration.

Optionally, the decoder 10 of the LDPC code further includes a storage unit 300, where the storage unit 300 is configured to store a minimum value of a last iteration, a minimum value of a current iteration, a first flag information bitmap1, and a second flag information bitmap2. Wherein, the first flag information bitmap1 indicates whether the minimum value is updated, and the second flag information bitmap2 indicates whether the next-minimum value is updated.

It should be understood that the storage unit 300 may also be used to store other parameters or information directly or indirectly calculated by the CNU logic calculation unit 100 and the VNU logic calculation unit 200.

Optionally, if the first flag information bitmap1_ { i, j } (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block is updated, and the second flag information bitmap2_i, j } (k) corresponding to the kth bit of the ith row and jth column effective block indicates that the next minimum value corresponding to the kth bit of the ith row and jth column effective block is updated, the CNU logic calculating unit 100 is specifically configured to update the minimum value min1_old_i } (k) of the kth bit of the ith row effective block in the last iteration to the next minimum value min2_old_i } (k) of the kth bit of the ith row effective block in the last iteration, and update the next minimum value min2_old { i (k) of the kth bit of the ith row effective block in the last iteration to the maximum value of the decoding information max; if the second flag information bitmap2_ { i, j } corresponding to the kth bit of the ith row and jth column effective block (k) indicates that the next smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, the first flag information bitmap1_ { i, j } corresponding to the kth bit of the ith row and jth column effective block (k) indicates that the smallest value corresponding to the kth bit of the ith row and jth column effective block is not updated, the CNU logic calculating unit 100 is specifically configured to update the next smallest value min2_old_ { i } (k) of the kth bit of the ith row and jth column effective block in the last iteration to the decoding information maximum quantization value max.

Optionally, if the j-th column is not the last column of the current iteration, the decoder 10 of the LDPC code further includes an updating unit 400; the updating unit 400 is configured to perform cyclic shift on the minimum value min1_new of the current iteration, the minor value min2_new of the current iteration, the minimum value min1_old of the last iteration, and the minor value min2_old of the last iteration, which are corresponding to each bit of each row of the effective block obtained by the CNU logic calculating unit 100, where the shift amount is equal to the offset value of the row where the effective block is located in the check matrix of the LDPC code.

Optionally, the difference value of the offset values of two adjacent effective blocks in each row in the check matrix of the LDPC code is a fixed value.

Optionally, if the iteration starts from column 1, the updating unit 400 is specifically configured to update the minimum value min1_new_ { i } of the kth bit of the ith row of effective blocks in the iteration to the minimum value min1_new_ { i } of the kth+p bit of the ith row of effective blocks in the iteration (k+p), and update the minimum value min1_old_ { i } of the kth bit of the ith row of effective blocks in the previous iteration to the minimum value min2_old_ { i } of the kth+p bit of the ith row of effective blocks in the previous iteration (k+p); if k is less than or equal to p from the last column of the present iteration, the updating unit 400 is specifically configured to update the minimum value min1_new_ { i } (k) of the kth bit of the present iteration ith row of effective blocks to the minimum value min1_new_ { i } (t+k-p) of the t+k-p bit of the present iteration ith row of effective blocks, and update the minimum value min1_old_ { i } (k) of the kth bit of the last iteration ith row of effective blocks to the minimum value min2_old_ { i } (t+k-p) of the t+k-p bit of the last iteration ith row of effective blocks; when k > p, the updating unit 400 is specifically configured to update the minimum value min1_new_ { i } (k) of the kth bit of the ith row of effective blocks in the current iteration to the minimum value min1_new_ { i } (k-p) of the kth-p bit of the ith row of effective blocks in the current iteration, and update the minimum value min1_old_ { i } (k) of the kth bit of the ith row of effective blocks in the last iteration to the minimum value min2_old_ { i } (k-p) of the kth-p bit of the ith row of effective blocks in the last iteration; wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block.

Optionally, decoder 10 of the LDPC code further comprises updating unit 400; if the j-th column is the last column of the present iteration, the updating unit 400 is configured to update the minimum value min1_old_i (k) of the kth bit of the ith row of valid blocks of the previous iteration to the minimum value min1_new_i (k) of the kth bit of the ith row of valid blocks of the present iteration, update the next minimum value min2_old_i (k) of the kth bit of the ith row of valid blocks of the previous iteration to the next minimum value min2_new_i (k) of the kth bit of valid blocks of the present iteration, and update the minimum value min1_new_i (k) of the kth bit of the ith row of valid blocks of the present iteration to the next minimum value min2_new_i (k) of the kth bit of valid blocks of the present iteration to the maximum quantized value of decoding information.

Optionally, the decoder 10 of the LDPC code further includes an initialization unit 500; the initialization unit 500 is configured to initialize a sign bit v2c_sgn of a value transmitted to the check node by a variable node corresponding to each bit of each valid block in the check matrix of the LDPC code, first flag information bitmap1 and second flag information bitmap2 corresponding to each bit of each valid block, a minimum value min1_old of a last iteration corresponding to each bit of each row of valid block, a minor value min2_old of a last iteration, a minimum value min1_new of a current iteration, and a minor value min2_new of a current iteration.

Optionally, if the absolute value of the first logarithmic confidence coefficient LLR corresponding to the check matrix of the LDPC code is a constant, the initializing unit 500 is specifically configured to initialize the minimum value min1_old of the last iteration and the next minimum value min2_old of the last iteration corresponding to each bit of each row of the effective block to be the maximum quantization value max of the decoding information. If the absolute value of the first pair of confidence coefficient LLRs corresponding to the check matrix of the LDPC code is non-constant, the initializing unit 500 is specifically configured to initialize the minimum value min1_old of the last iteration and the minimum value min2_old of the last iteration corresponding to each bit of each row of the valid block to be 0.

Optionally, the initializing unit 500 is further specifically configured to initialize the minimum value min1_new of the current iteration and the minor value min2_new of the current iteration corresponding to each bit of each row of valid blocks to a maximum quantization value max of decoding information; and initializing the first flag information bitmap1 and the second flag information bitmap2 corresponding to each bit of each effective block to a first preset value of 0.

Optionally, if the absolute value ABS (v2c_ { i, j } (k)) of the value of the variable node of the kth bit of the kth row effective block transferred to the check node is smaller than the minimum value min1_ _ { i (k) of the kth bit of the kth row effective block of this iteration, the CNU logic calculation unit 100 is further specifically configured to update the next small value min2_ _ { i } (k) of the kth bit of the kth row effective block of this iteration to the minimum value min1_ _ new { i } (k) of the kth bit of the kth row effective block of this iteration, update the minimum value min1_ _ new { i } (k) of the kth bit of the kth row effective block of this iteration to the absolute value ABS (v2c_ _, j }) of the variable node of the kth bit of the kth row effective block of this iteration to the check node, and set the corresponding value of the kth bit of the kth row effective block of this iteration to the second bit 1_, and the value of the kth bit of the kth row effective block of this iteration to be equal to the value 1_; if the absolute value ABS (v2c_ { i, j } (k)) of the value of the kth bit variable node of the ith row and jth column valid block transferred to the check node is greater than the minimum value min1_ new_ { i } (k) of the kth bit of the ith row valid block of this iteration and less than the next-smallest value min2_ new_ { i } (k) of the kth bit of the ith row valid block of this iteration, i.e., min1 new_ { i } (k) < ABS (v2c_ { i, j } (k)) < min2_ new_ { i } (k), the CNU logic calculating unit 100 is further specifically configured to update the next smallest value min2_new_i (k) of the kth bit of the ith row of valid blocks in the present iteration to an absolute value ABS (v2c_i, j (k)) of a value that the variable node of the kth bit of the ith row of valid blocks transmits to the check node, update the first flag information bitmap1_i, j (k) corresponding to the kth bit of the ith row of valid blocks to a first preset value "0", and update the second flag information bitmap2_i, j (k) to a second preset value "1"; if the absolute value ABS (v2c_ { i, j } (k)) of the value transmitted from the variable node of the kth bit of the ith row and jth column effective block to the check node is greater than the next-smallest value min2_new_ { i } (k) of the kth bit of the ith row and effective block in this iteration, that is, ABS (v2c_ { i, j } (k)) > min2_new_ { i } (k), the CNU logic calculating unit 100 is further specifically configured to update the first flag information bitmap1_ { i, j } (k)) and the second flag information bitmap2_ { i, j } (k) corresponding to the kth bit of the ith row and jth column effective block to a first preset value "0"; wherein ABS () represents taking absolute value.

Optionally, the CNU logic calculating unit 100 is specifically configured to update the xor value cn_sgn_ { i } of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks, and calculate the value c2v_ { i, j } of the check node transfer to the variable node of the kth bit of the ith row of jth column of valid blocks according to the updated xor value cn_sgn_ { i } of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks and the minimum value min_ { i } of the kth bit of the ith row of valid blocks. The VNU logic calculating unit 200 is specifically configured to calculate, according to the first pair of confidence levels llr_new_j (k) corresponding to the kth bit of the jth column of valid blocks and the values C2V of the check nodes corresponding to all the jth column of valid blocks obtained by the CNU logic calculating unit 100 and transmitted to the variable nodes, a second pair of confidence levels llr_new_j (k) corresponding to the kth bit of the jth column of valid blocks; and calculating the value V2C_ { i, j } (k) of the variable node of the kth bit of the ith row and jth column effective block transmitted to the check node according to the value C2V_ { i, j } (k) of the check node of the kth bit of the ith row and jth column effective block transmitted to the variable node and the second pair of log confidence coefficient LLR_new_ { j } (k) corresponding to the kth bit of the jth column effective block.

Optionally, the CNU logic calculating unit 100 is specifically configured to xored the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row of effective blocks with the sign bit v2c_sgn_ { i, j } (k) of the value that the variable node of the kth bit of the ith row of effective blocks transmits to the check node, to obtain the updated exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row of effective blocks.

Optionally, the CNU logic calculating unit 100 is further specifically configured to map the updated exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks to a positive sign or a negative sign, and multiply the mapped positive sign or negative sign with the minimum value min_ { i } (k) of the kth bit of the ith row of valid blocks to obtain a value c2v_ { i, j } (k) that is transmitted from the check node of the kth bit of the ith row of jth column of valid blocks to the variable node.

Optionally, the VNU logic calculating unit 200 is further specifically configured to add the value C2V of the check node corresponding to all valid blocks in the j-th column to the variable node and the first logarithmic confidence coefficient llr_j (k) corresponding to the k-th bit of the valid block in the j-th column according to the bits, to obtain the second logarithmic confidence coefficient llr_new_j (k) corresponding to the k-th bit of the valid block in the j-th column.

Optionally, the VNU logic calculating unit 200 is further specifically configured to subtract the value c2v_ { i, j } (k) of the variable node transmitted to the variable node by the check node of the kth bit of the jth row and jth column of valid blocks from the second pair of confidence coefficients llr_new_ { j } (k) corresponding to the kth bit of the jth row and jth column of valid blocks, to obtain the value v2c_ { i, j } (k) of the variable node transmitted to the check node of the kth bit of the jth row and jth column of valid blocks, that is, calculate v2c_ { i, j } (k) according to the formula v2c_ { i, j } (k) =llr_new_j (k) -c2v_ { i, j } (k).

Optionally, the CNU logic calculating unit 100 is further configured to update the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row valid block according to the value V2c_ { i, j } (k) transmitted to the check node by the variable node of the kth bit of the jth row valid block.

Optionally, the CNU logic calculating unit 100 is further specifically configured to transfer the variable node of the kth bit of the jth row and jth column of the valid block to the sign bit v2c_sgn_ { i, j } (k) of the value of the check node, and perform exclusive or on the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row of the valid block, so as to obtain the exclusive or value cn_sgn_ { i } (k) of the sign bit of the decoding information corresponding to the kth bit of the ith row of the updated ith row of the valid block.

All relevant content of each operation related to the above method embodiment may be cited to the functional description of the corresponding functional module, which is not described herein.

In this embodiment, the decoder of the LDPC code is presented in a form that divides the respective functional blocks in an integrated manner. A "module" herein may refer to a particular ASIC, an electronic circuit, a processor and memory that execute one or more software or firmware programs, an integrated logic circuit, and/or other device that can provide the described functionality. In a simple embodiment, one skilled in the art will appreciate that the decoder of the LDPC code may take the form shown in FIG. 7.

For example, the processor 11 in fig. 7 may cause the decoder of the LDPC code to perform the method in the above-described method embodiment by calling computer-executable instructions stored in the memory 12.

By way of example, the functions/implementation of CNU logic calculation unit 100, VNU logic calculation unit 200, update unit 400, and initialization unit 500 in fig. 12 may be implemented by processor 11 in fig. 7 invoking computer-executed instructions stored in memory 12.

Since the decoder of the LDPC code provided in this embodiment can perform the above method, the technical effects that can be obtained by the decoder of the LDPC code can be referred to the above method embodiments, and will not be described herein.

The embodiment of the present application may exemplarily divide the functional modules of the decoder 10 of the LDPC code according to the above-described method, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules may be implemented in hardware or in software functional modules. It should be noted that, in the embodiment of the present application, the division of the modules is schematic, which is merely a logic function division, and other division manners may be implemented in actual implementation.

Optionally, an embodiment of the present application further provides a decoder of an LDPC code (for example, the decoder of the LDPC code may be a chip or a system-on-chip), where the decoder of the LDPC code includes a processor and an interface, and the processor is configured to read the instructions to perform the method in any of the method embodiments described above. In one possible design, the decoder of the LDPC code further includes a memory. The memory is used for storing necessary program instructions and data, and the processor can call the program code stored in the memory to instruct the wireless screen projection device to execute the method in any of the method embodiments. Of course, the memory may not be in the decoder of the LDPC code. When the decoder of the LDPC code is a chip system, the decoder may be formed by a chip, or may include a chip and other discrete devices, which is not particularly limited in the embodiment of the present application.

When the decoder of the LDPC code is a chip, the CNU logic calculating unit 100, the VNU logic calculating unit 200, the updating unit 400, and the initializing unit 500 may execute computer-executable instructions stored in the storage unit 300, so that the chip in the decoder of the LDPC code performs a method according to the embodiment of the method. Alternatively, the storage unit 300 is a storage unit in the chip, such as a register, a cache, etc., and the storage unit may also be a storage unit in the terminal device or the network device, which is located outside the chip, such as a Read Only Memory (ROM) or other type of static storage device that may store static information and instructions, a random access memory (random access memory, RAM), etc.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), etc. In an embodiment of the present application, the computer may include the apparatus described above.

Although the application is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Although the application has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the application. Accordingly, the specification and drawings are merely exemplary illustrations of the present application as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof. The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A method for decoding a low density parity check, LDPC, code, comprising:

updating the minimum value and the next minimum value of the kth bit of the ith row of effective blocks of the last iteration according to the first flag information and the second flag information corresponding to the kth bit of the ith row and the jth column of effective blocks of the check matrix of the LDPC code; wherein the first flag information indicates whether a minimum value has been updated; the second flag information indicates whether the next-to-small value has been updated;

acquiring the minimum value of the kth bit of the ith row effective block; the minimum value of the kth bit of the ith row effective block is the smaller one of the minimum value of the kth bit of the ith row effective block of the iteration and the updated minimum value of the kth bit of the ith row effective block of the previous iteration;

acquiring a value transmitted to a check node by a variable node of the kth bit of the ith row and jth column effective blocks according to the minimum value of the kth bit of the ith row effective blocks;

and updating the minimum value and the next minimum value of the k bit of the i-th row effective block of the iteration and the first mark information and the second mark information corresponding to the k bit of the j-th row effective block of the iteration according to the value transmitted to the check node by the variable node of the k bit of the i-th row and the j-th column effective block.
The decoding method according to claim 1, wherein updating the minimum value and the next smallest value of the kth bit of the ith row effective block of the last iteration according to the first flag information and the second flag information corresponding to the kth bit of the jth column effective block of the ith row of the check matrix of the LDPC code, comprises:

if the first flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block is updated, updating the minimum value of the kth bit of the ith row effective block of the last iteration into the next minimum value of the kth bit of the ith row effective block of the last iteration;

and if the second flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, updating the next-smallest value of the kth bit of the ith row effective block of the last iteration into a decoding information maximum quantized value.
The decoding method according to claim 1, wherein if the j-th column is not the last column of the present iteration, after updating the minimum value and the next-smallest value of the k-th bit of the i-th row effective block of the present iteration and the first flag information and the second flag information corresponding to the k-th bit of the i-th row and j-th column effective block according to the value transferred to the check node by the variable node of the k-th bit of the i-th row and j-th column effective block, the decoding method further comprises:

And carrying out cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of the effective block, wherein the shift quantity is equal to the offset value of the row of the effective block in the check matrix of the LDPC code.
A decoding method according to claim 3, wherein the difference between the offset values of two adjacent active blocks in each row in the check matrix of the LDPC code is a fixed value.
The decoding method according to claim 4, wherein the performing the cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the next minimum value of the last iteration, which correspond to each bit of each row of the valid block, includes:

if the iteration starts from the 1 st column, updating the minimum value of the k bit of the i-th row effective block of the iteration to the minimum value of the k+p bit of the i-th row effective block of the iteration, and updating the minimum value of the k bit of the i-th row effective block of the previous iteration to the minimum value of the k+p bit of the i-th row effective block of the previous iteration;

if k is less than or equal to p from the last column, updating the minimum value of the kth bit of the ith row of effective blocks of the iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the iteration, and updating the minimum value of the kth bit of the ith row of effective blocks of the previous iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the previous iteration; when k is more than p, updating the minimum value of the k bit of the i-th effective block of the current iteration to the minimum value of the k-p bit of the i-th effective block of the current iteration, and updating the minimum value of the k bit of the i-th effective block of the last iteration to the minimum value of the k-p bit of the i-th effective block of the last iteration;

Wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block.
The decoding method according to claim 1, wherein if the j-th column is the last column of the present iteration, after updating the minimum value and the next-smallest value of the k-th bit of the i-th row effective block of the present iteration, the first flag information, the second flag information, according to the value transferred from the variable node of the k-th bit of the i-th row and j-th column effective block to the check node, the decoding method further comprises:

and updating the minimum value of the k bit of the ith effective block of the last iteration to the minimum value of the k bit of the ith effective block of the current iteration, updating the secondary minimum value of the k bit of the ith effective block of the last iteration to the secondary minimum value of the k bit of the ith effective block of the current iteration, and updating the minimum value and the secondary minimum value of the k bit of the ith effective block of the current iteration to the maximum quantized value of decoding information.
The coding method of claim 1, wherein before coding starts from a column 1 valid block and performs a first iteration on the column 1 valid block, or before coding starts from a last column valid block and performs a first iteration on the last column valid block, the coding method further comprises:

Initializing the sign bit of the value transmitted to the check node by the variable node corresponding to each bit of each effective block in the check matrix of the LDPC code, the first flag information and the second flag information corresponding to each bit of each effective block, the minimum value and the next minimum value of the current iteration corresponding to each bit of each row of effective block, and the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of effective block.
The decoding method according to claim 7, wherein if the absolute value of the first logarithmic confidence coefficient corresponding to the check matrix of the LDPC code is constant, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of the effective blocks are both the maximum quantization value of the decoding information after initialization;

if the absolute value of the first pair of logarithmic confidence coefficients corresponding to the check matrix of the LDPC code is non-constant, the minimum value and the next minimum value of the last iteration corresponding to each bit of each row of effective block are both 0 after initialization.
The decoding method according to claim 7 or 8, wherein the minimum value and the next-smallest value of the current iteration corresponding to each bit of each row of the valid block are both the maximum quantization value of the decoding information after initialization;

The first flag information and the second flag information corresponding to each bit of each effective block are both a first preset value after initialization.
The decoding method according to any one of claims 1 to 9, wherein the updating the minimum value and the next minimum value of the kth bit of the ith row valid block of the present iteration and the first flag information and the second flag information corresponding to the kth bit of the ith row and jth column valid block according to the value transferred to the check node by the variable node of the kth bit of the ith row and jth column valid block includes:

if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is smaller than the minimum value of the kth bit of the ith row effective block of the current iteration, updating the next-smallest value of the kth bit of the ith row effective block of the current iteration to the minimum value of the kth bit of the ith row effective block of the current iteration, updating the minimum value of the kth bit of the ith row effective block of the current iteration to the absolute value of the value transmitted to the check node by the variable node of the kth bit of the jth row and jth column effective block of the current iteration, and updating the first mark information and the second mark information corresponding to the kth bit of the jth row and jth column effective block of the current iteration to a second preset value;

If the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the minimum value of the kth bit of the ith row effective block of the iteration and smaller than the next-smallest value of the kth bit of the ith row effective block of the iteration, updating the next-smallest value of the kth bit of the ith row effective block of the iteration to be the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, updating the first mark information corresponding to the kth bit of the ith row and jth column effective block to be a first preset value, and updating the second mark information to be the second preset value;

and if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the next-smallest value of the kth bit of the ith row and jth column effective block of the iteration, updating the first mark information and the second mark information corresponding to the kth bit of the ith row and jth column effective block to be the first preset value.
The method according to any one of claims 1 to 10, wherein the obtaining the value of the variable node of the kth bit of the ith row and jth column valid block to the check node according to the minimum value of the kth bit of the ith row valid block includes:

Updating the exclusive or value of the symbol bit of the decoding information corresponding to the kth bit of the ith row of effective blocks, and calculating the value transmitted to the variable node by the check node of the kth bit of the ith row of the jth column of effective blocks according to the updated exclusive or value of the symbol bit of the decoding information corresponding to the kth bit of the ith row of effective blocks and the minimum value of the kth bit of the ith row of effective blocks;

calculating a second pair of confidence coefficients corresponding to the kth bit of the jth effective block according to the first pair of confidence coefficients corresponding to the kth bit of the jth effective block and the values transmitted to the variable nodes by the check nodes corresponding to all the jth effective blocks;

and calculating the value of the variable node transmitted to the check node of the kth bit of the ith row and jth column effective block according to the value of the check node transmitted to the variable node of the kth bit of the ith row and jth column effective block and the second pair of confidence coefficients corresponding to the kth bit of the jth column effective block.
The decoding method of claim 11, wherein updating the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row of valid blocks comprises:

and carrying out exclusive OR on the exclusive OR value of the symbol bit of the decoding information corresponding to the kth bit of the ith row effective block and the symbol bit of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block to obtain the updated exclusive OR value of the symbol bit of the decoding information corresponding to the kth bit of the ith row effective block.
The decoding method according to claim 11 or 12, wherein the calculating the value of the check node of the kth bit of the ith row and jth column effective blocks transferred to the variable node based on the updated xor value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective blocks and the minimum value of the kth bit of the ith row effective blocks includes:

and mapping the exclusive OR value of the sign bit of the decoding information corresponding to the k bit of the updated i-th row effective block into a positive sign or a negative sign, and multiplying the exclusive OR value with the minimum value of the k bit of the i-th row effective block to obtain the value of the variable node transmitted to the check node of the k bit of the i-th row and j-th column effective block.
The method according to any one of claims 11 to 13, wherein the calculating the second pair of the confidence coefficients corresponding to the kth bit of the valid block in the jth column based on the first pair of the confidence coefficients corresponding to the kth bit of the valid block in the jth column and the values of the check nodes transmitted to the variable nodes corresponding to all valid blocks in the jth column includes:

and adding the values transmitted to variable nodes by the check nodes corresponding to all the effective blocks in the j-th row and the first pair of confidence coefficients corresponding to the k-th bit of the effective blocks in the j-th row according to the bits to obtain the second pair of confidence coefficients corresponding to the k-th bit of the effective blocks in the j-th row.
The method according to any one of claims 11 to 14, wherein calculating the value of the variable node at the kth bit of the jth valid block in the ith row and the jth column to the check node based on the value of the check node at the kth bit of the jth valid block to the variable node and the second logarithmic confidence corresponding to the kth bit of the jth valid block includes:

subtracting the value of the check node transmitted to the variable node of the kth bit of the ith row and jth column effective block from the second pair of log confidence corresponding to the kth bit of the jth column effective block to obtain the value of the variable node transmitted to the check node of the kth bit of the ith row and jth column effective block.
The decoding method according to any one of claims 11 to 15, wherein after the value of the variable node of the kth bit of the ith row and jth column effective blocks transferred to the check node is obtained from the minimum value of the kth bit of the ith row effective blocks, the decoding method further comprises:

and updating the exclusive OR value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block according to the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block.
The decoding method according to claim 16, wherein the updating the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row valid block according to the value transferred to the check node by the variable node of the kth bit of the ith row and jth column valid block includes:

And carrying out exclusive or on the sign bit of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block and the exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block to obtain the updated exclusive or value of the sign bit of the decoding information corresponding to the kth bit of the ith row effective block.
A decoder for an LDPC code, comprising:

the memory is used for storing the minimum value and the next minimum value of the last iteration, the minimum value and the next minimum value of the current iteration, the first mark information and the second mark information; wherein the first flag information indicates whether a minimum value has been updated, and the second flag information indicates whether a next-minimum value has been updated;

a processor, configured to update a minimum value and a next minimum value of a kth bit of an ith row of an effective block of a last iteration according to first flag information and second flag information corresponding to the kth bit of the ith row and jth column of the effective block of a check matrix of the LDPC code; acquiring the minimum value of the kth bit of the ith row effective block; the minimum value of the kth bit of the ith row effective block is the smaller one of the minimum value of the kth bit of the ith row effective block of the iteration and the updated minimum value of the kth bit of the ith row effective block of the previous iteration; acquiring a value transmitted to a check node by a variable node of the kth bit of the ith row and jth column effective blocks according to the minimum value of the kth bit of the ith row effective blocks; and updating the minimum value and the next minimum value of the k bit of the i-th row effective block of the iteration and the first mark information and the second mark information corresponding to the k bit of the j-th row effective block of the iteration according to the value transmitted to the check node by the variable node of the k bit of the i-th row and the j-th column effective block.
The decoder according to claim 18, wherein the processor is configured to update the minimum value of the kth bit of the ith row effective block of the previous iteration to the next minimum value of the kth bit of the ith row effective block of the previous iteration if the first flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the minimum value corresponding to the kth bit of the ith row and jth column effective block of the previous iteration is updated; and if the second flag information corresponding to the kth bit of the ith row and jth column effective block indicates that the next-smallest value corresponding to the kth bit of the ith row and jth column effective block is updated, updating the next-smallest value of the kth bit of the ith row effective block of the last iteration into a decoding information maximum quantized value.
The decoder according to claim 18 or 19, wherein if the j-th column is not the last column of the current iteration, the processor is further configured to perform cyclic shift on the minimum value and the next minimum value of the current iteration, the minimum value and the next minimum value of the last iteration, which correspond to each bit of each row of the valid block, where the shift amount is equal to the offset value of the row in which the valid block is located in the check matrix of the LDPC code.
The decoder of claim 20, wherein a difference between offset values of two adjacent active blocks of each row in a check matrix of the LDPC code is a fixed value.
The decoder of claim 21, wherein the processor is specifically configured to update a minimum value of a kth bit of the i-th line valid block of the current iteration to a minimum value of a k+p-th bit of the i-th line valid block of the current iteration and update a minimum value of a k bit of the i-th line valid block of the previous iteration to a minimum value of a k+p-th bit of the i-th line valid block of the previous iteration if the current iteration starts from column 1; if k is less than or equal to p from the last column, updating the minimum value of the kth bit of the ith row of effective blocks of the iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the iteration, and updating the minimum value of the kth bit of the ith row of effective blocks of the previous iteration to the minimum value of the (t+k) -p bit of the ith row of effective blocks of the previous iteration; when k is more than p, updating the minimum value of the k bit of the i-th effective block of the current iteration to the minimum value of the k-p bit of the i-th effective block of the current iteration, and updating the minimum value of the k bit of the i-th effective block of the last iteration to the minimum value of the k-p bit of the i-th effective block of the last iteration; wherein p is the difference of the offset values of two adjacent effective blocks of the ith row; t is the total number of bits per valid block.
The decoder according to claim 18 or 19, wherein if the j-th column is the last column of the present iteration, the processor is further configured to update the minimum value of the k-th bit of the i-th row effective block of the previous iteration to the minimum value of the k-th bit of the i-th row effective block of the present iteration, update the next-smallest value of the k-th bit of the i-th row effective block of the previous iteration to the next-smallest value of the k-th bit of the i-th row effective block of the present iteration, and update both the minimum value and the next-smallest value of the k-th bit of the i-th row effective block of the present iteration to the maximum quantization value of the decoding information.
The decoder according to claim 18 or 19, wherein the processor is specifically configured to update a next-smallest value of a kth bit of the ith row of valid blocks of the present iteration to a smallest value of a kth bit of the ith row of valid blocks of the present iteration, update the smallest value of the kth bit of the ith row of valid blocks of the present iteration to an absolute value of a value of the variable node of the kth bit of the ith row of valid blocks of the present iteration to a check node, and update both the first flag information and the second flag information corresponding to the kth bit of the ith row of valid blocks of the present iteration to a second preset value if an absolute value of a value of the variable node of the kth bit of the ith row of valid blocks of the present iteration transmitted to the check node is smaller than the smallest value of the kth bit of the ith row of valid blocks of the present iteration; if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the minimum value of the kth bit of the ith row effective block of the iteration and smaller than the next-smallest value of the kth bit of the ith row effective block of the iteration, updating the next-smallest value of the kth bit of the ith row effective block of the iteration to be the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block, updating the first mark information corresponding to the kth bit of the ith row and jth column effective block to be a first preset value, and updating the second mark information to be the second preset value; and if the absolute value of the value transmitted to the check node by the variable node of the kth bit of the ith row and jth column effective block is larger than the next-smallest value of the kth bit of the ith row and jth column effective block of the iteration, updating the first mark information and the second mark information corresponding to the kth bit of the ith row and jth column effective block to be the first preset value.
A communication device comprising a decoder, a transceiver, and a demodulator; the decoder being a decoder according to any of claims 18-24;

the transceiver is used for receiving analog signals;

the demodulator is used for converting the analog signal into a digital signal so that the decoder decodes the digital signal; the digital signal includes an LDPC code.
A communication device comprising a decoder and a memory; the decoder being a decoder according to any of claims 18-24;

the memory is used for storing the data decoded by the decoder.
A computer readable storage medium storing a computer program comprising instructions for performing the decoding method of any one of claims 1-17.
A computer program product, the computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the decoding method according to any of claims 1-17.