CN114913900A

CN114913900A - Static ECC error correction NAND error processing method and device, computer equipment and storage medium

Info

Publication number: CN114913900A
Application number: CN202210692393.1A
Authority: CN
Inventors: 冯元元; 王震; 范云松
Original assignee: Suzhou Yilian Information System Co Ltd
Current assignee: Suzhou Yilian Information System Co Ltd
Priority date: 2022-06-17
Filing date: 2022-06-17
Publication date: 2022-08-16

Abstract

The invention relates to a NAND error processing method, a NAND error processing device, computer equipment and a storage medium for static ECC error correction, wherein the method comprises the following steps: if the page data is read and ECC errors occur, entering a normal flash memory re-reading state; judging whether ECC errors occur when the normal flash memory re-reading state is entered; if ECC error occurs, judging whether the re-reading of the flash memory is finished with all levels; if the static ECC correction is finished, executing static ECC correction; judging whether ECC errors occur during static ECC correction; if ECC error occurs, obtaining a PE value, and right-shifting the PE value by 10 bits to obtain an L value; judging whether the cycle number of static ECC error correction is equal to the value L or not; if equal to the value of L, then Riad decoding is performed. The error correction capability of the static ECC is gradually enhanced, and the error correction process of the static ECC is perfected, so that the high-efficiency NAND error process protection of the static ECC is realized.

Description

Static ECC error correction NAND error processing method and device, computer equipment and storage medium

Technical Field

The invention relates to the technical field of static ECC (error correction code), in particular to a NAND error processing method and device for static ECC error correction, computer equipment and a storage medium.

Background

Currently, most solid state disks adopt a static ECC error correction scheme. The size of the ECC error correction unit (user data) and the ECC calibration data is fixed in the whole life cycle of the solid state disk, namely, the error correction capability is always kept unchanged, and the probability of errors is gradually increased along with the use of the flash memory because the probability of bit flipping at the early stage of the use of the flash memory is smaller.

In the conventional NAND error flow, after Read page data, once an ECC fail occurs, Read Retry (flash reread) is performed, if an ECC fail still occurs, static ECC error correction is performed, and if an ECC fail still occurs, Raid is performed.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a NAND error processing method and device for static ECC (error correction code), a computer device and a storage medium.

In order to solve the technical problems, the invention adopts the following technical scheme:

in a first aspect, the present embodiment provides a NAND error processing method for static ECC error correction, including the following steps:

if the page data is read and ECC error occurs, entering a normal flash memory re-reading state;

judging whether ECC errors occur when the normal flash memory re-reading state is entered;

if entering a normal flash memory rereading state and generating an ECC error, judging whether the flash memory rereading has finished all levels;

if the flash memory rereads all levels, executing static ECC error correction;

judging whether ECC errors occur during static ECC correction;

if the static ECC correction is executed and an ECC error occurs, acquiring a PE value, and right-shifting the PE value by 10 bits to obtain an L value;

judging whether the cycle number of static ECC error correction is equal to the value L or not;

if the cycle number of the static ECC error correction is equal to the value L, then the Riad decoding is executed.

The further technical scheme is as follows: if entering the normal flash memory rereading state and generating an ECC error, judging whether the flash memory rereading has finished all the level steps, if the flash memory rereading has not finished all the level, increasing the level times of the flash memory rereading needing to be executed, returning to execute, and if the page data is read and the ECC error is generated, entering the normal flash memory rereading state.

The further technical scheme is as follows: and if the flash memory rereads all levels, executing static ECC error correction through a low-density parity check code in the step of executing the static ECC error correction.

The further technical scheme is as follows: after the step of determining whether the number of cycles of the static ECC error correction is equal to the L value, the method further includes: and if the cycle number of the static ECC error correction is not equal to the value L, recording the cycle number of the static ECC error correction, and returning to execute the static ECC error correction if the flash memory rereads all levels.

In a second aspect, the present embodiment provides a static ECC error correction NAND error processing apparatus, including: the system comprises a generation entering unit, a first judging unit, a second judging unit, a first executing unit, a third judging unit, an obtaining unit, a fourth judging unit and a second executing unit;

the generation entering unit is used for entering a normal flash memory rereading state if the page reading data has ECC errors;

the first judging unit is used for judging whether ECC errors occur when the flash memory enters a normal re-reading state;

the second judging unit is used for judging whether the flash rereading is finished at all levels or not if the ECC error occurs in the normal flash rereading state;

the first execution unit is used for executing static ECC error correction if the flash memory rereads all levels;

the third judging unit is used for judging whether ECC errors occur during static ECC correction;

the obtaining unit is used for obtaining a PE value if the static ECC correction is executed and an ECC error occurs, and right shifting the PE value by 10 bits to obtain an L value;

the fourth judging unit is used for judging whether the cycle number of static ECC correction is equal to the value L or not;

and the second execution unit is used for executing the Riad decoding if the cycle number of the static ECC error correction is equal to the value L.

The further technical scheme is as follows: further comprising: and the adding and returning unit is used for increasing the level times which need to be executed by the flash memory rereading if the flash memory rereading does not finish all the levels, and returning to execute the flash memory rereading state if the page data is read and ECC errors occur.

The further technical scheme is as follows: in the first execution unit, static ECC correction is performed by a low density parity check code.

The further technical scheme is as follows: further comprising: and the error correction returning unit is used for recording the cycle number of the static ECC error correction if the cycle number of the static ECC error correction is not equal to the value L, and returning to execute the static ECC error correction if the flash memory rereads all levels.

In a third aspect, the present embodiment provides a computer device, where the computer device includes a memory and a processor, the memory stores a computer program thereon, and the processor implements the NAND error processing method for static ECC error correction as described above when executing the computer program.

In a fourth aspect, the present embodiment provides a storage medium storing a computer program comprising program instructions that, when executed by a processor, can implement the NAND error handling method for static ECC error correction as described above.

Compared with the prior art, the invention has the beneficial effects that: with the use of the solid state disk, the error correction capability under the static ECC is gradually enhanced, and the flow of static ECC error correction is perfected, so that the high-efficiency NAND error flow protection of static ECC error correction is realized.

The invention is further described below with reference to the accompanying drawings and specific embodiments.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

FIG. 1 is a flowchart illustrating a NAND error processing method for static ECC correction according to an embodiment of the present invention;

FIG. 2 is a schematic block diagram of a static ECC error corrected NAND error handling device according to an embodiment of the present invention;

FIG. 3 is a schematic block diagram of a computer device provided by an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the specification of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be further understood that the term "and/or" as used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

Wherein, the invention relates to the following English, the corresponding translation explanation is as follows:

ECC is the abbreviation of Error Correcting Code, which is a technology capable of realizing Error checking and Correcting;

NAND, granular, flash;

PE, namely the middle of P/E is provided with a slash, is called P/ECycle (P/E for short) for short, and is used for representing the erasable times of the Flash memory, and the P/E times are calculated for 1 time when the whole SSD is programmed (written in)/erased for 1 time each time;

read page, reading page data;

raid, an abbreviation of "Redundant Array of Independent Disk", which means an Independent Redundant Disk Array in chinese;

read Retry, flash reread;

ECC fail, Error Correcting Code Error;

a Retry Table Read Retry, a normal Read Retry (flash Read) process;

level, different gear positions of flash memory rereading;

LDPC, coding and decoding technology, Low Density Parity Check Code english abbreviation, meaning Low Density Parity Check Code;

TLC PE, flash SLC, MLC, TLC in TLC, Triple Level Cell (TLC for short);

RAID Decode, RAID Decode.

Referring to the embodiment shown in fig. 1, the present invention discloses a NAND error processing method for static ECC error correction, comprising the following steps:

s1, if the page data has ECC error, then entering into normal flash memory re-reading state;

specifically, data to be transmitted by a user is encoded through encoding and decoding such as LDPC and CRC to form an ECC check bit, and when the data is received, the data and the ECC check bit are decoded through LDPC, CRC and the like, and if the decoding is correct, the data is correct (ECC pass), and if the decoding is failed, the data is in error (ECC fail); the solid state hard disk controller is provided with an ECC (error correction code) module, part of the flash memory is also integrated with the ECC module, and the commonly used flash memory ECC algorithm comprises BCH (broadcast channel), LDPC (low density parity check) and the like.

S2, judging whether ECC error occurs when the normal flash memory re-reading state is entered; if the normal flash memory re-reading state is entered and the ECC error does not occur, ending the operation;

the ECC error in the step S2 is similar to the ECC error in the step S1.

S3, if entering the normal flash memory rereading state and generating ECC error, judging whether the flash memory rereading has done all levels; if the flash memory rereads and does not finish all levels, jumping to execute the step S9;

s4, if the flash memory rereads all levels, executing static ECC error correction;

specifically, in step S4, static ECC error correction is performed by the low density parity check code.

Specifically, LDPC is a common codec, and only LDPC codec needs to be used. The method is simple in that an array with a moderate calculation amount, namely a parity check code, is provided, the code can be encoded with data, and when the code is correspondingly decoded, the array is required to be circularly decoded, so that the common encoding and decoding are realized, and related knowledge is universal.

S5, judging whether ECC error occurs during static ECC correction; if the static ECC correction is executed and no ECC error occurs, ending the operation;

the ECC error in the step S5 is similar to the ECC error in the step S1. In particular, static ECC refers to codec whose check bit length is fixed (which is a static history), and dynamic ECC if the check bit length is changed. In addition, the difference between static ECC and dynamic ECC is further illustrated: currently, most solid state disks adopt a static ECC error correction scheme. The size of the ECC error correction unit (user data) and the ECC calibration data is fixed throughout the life cycle of the solid state disk, i.e. the error correction capability remains constant all the time. Since the probability of bit flipping at the early stage of use of flash memory is small, the probability of error gradually increases as the flash memory is used. Therefore, some solid state disks began to use a dynamic ECC error correction scheme: starting to use less error correction code in order to store more user data in the flash page; with the use of the solid state disk, the error correction capability needs to be enhanced, and the smaller the proportion of the user data in the flash memory page is, the larger the proportion of the error correction code is. The dynamic ECC correction scheme is to dynamically adjust the ECC correction capability of the solid state disk along with the use of the solid state disk.

S6, if the static ECC correction is executed and an ECC error occurs, obtaining a PE value, and right-shifting the PE value by 10 bits to obtain an L value;

specifically, taking the PE value and right shifting the PE value by 10 bits has the effect of dividing PE by 1024 for a whole, e.g., L is 0 when TLC PE <1024 and L is 1 if more than 1024 is less than 2048.

Specifically, acquiring the PE value means that the firmware counts a table, records the table as 1P/E once the flash memory is completely erased, and records the table in a specific space of the flash memory for storage.

S7, judging whether the cycle number of the static ECC error correction is equal to the L value; if the cycle number of the static ECC error correction is not equal to the value L, skipping to execute the step S10;

the firmware sets a maximum number of times to be L, i.e. the ECC error correction is cycled for a maximum of L times. The value of L is 0 or 1 or other values.

S8, if the cycle number of the static ECC error correction is equal to the L value, then executing the Riad decoding;

specifically, the read decoding is performed, and the result is that the data with errors is corrected, that is, the ECC is wrong with the description data, and the wrong data is corrected by Raid.

S9, increasing the level times required to be executed by flash memory rereading, and returning to execute the step of entering a normal flash memory rereading state if ECC (error correction code) errors occur in the page data read;

specifically, this is a flash memory re-reading function, which provides a way to adjust the reference voltage for data re-reading, generally speaking, different flash memory manufacturers provide 36 th-Level voltage adjustment, where Level refers to the 36 th-Level reference voltage adjustment, so that there is an opportunity to read correct data by adjusting the reference voltage.

And S10, recording the cycle number of static ECC error correction, and returning to execute the static ECC error correction if the flash memory rereads all levels.

Specifically, static ECC error correction is cycled through, recording the number of cycles.

The static ECC correction flow is dynamically adjusted according to the use condition of the PE, so that different static ECC correction capabilities are used in different PEs, the error correction capability of the static ECC correction scheme can be gradually enhanced along with the use of the solid state disk, the static ECC correction flow is perfected, and the high-efficiency NAND error flow protection of static ECC correction is realized.

Referring to fig. 2, the present invention also discloses a static ECC error correction NAND error processing apparatus, including: the occurrence entering unit 10, the first judging unit 20, the second judging unit 30, the first executing unit 40, the third judging unit 50, the obtaining unit 60, the fourth judging unit 70 and the second executing unit 80;

the occurrence entering unit 10 is configured to enter a normal flash re-reading state if an ECC error occurs in page data reading;

the first judging unit 20 is configured to judge whether an ECC error occurs when the flash memory enters a normal re-read state;

the second determining unit 30 is configured to determine whether the flash rereading has finished all levels if the ECC error occurs in the normal flash rereading state;

the first execution unit 40 is configured to execute static ECC error correction if the flash memory rereads all levels;

the third determining unit 50 is configured to determine whether an ECC error occurs during static ECC correction;

the obtaining unit 60 is configured to obtain a PE value if an ECC error occurs during static ECC error correction, and shift the PE value by 10 bits to the right to obtain an L value;

the fourth judging unit 70 is configured to judge whether the number of cycles of static ECC error correction is equal to the value L;

the second execution unit 80 is configured to execute the read decoding if the number of cycles of the static ECC error correction is equal to the value L.

Wherein, the device still includes: and the adding and returning unit 90 is configured to increase the level times that the flash rereading needs to be performed if the flash rereading does not complete all levels, and return to perform the step of entering a normal flash rereading state if the page data is read and an ECC error occurs.

Wherein, in the first execution unit 40, static ECC error correction is performed by low density parity check code.

Wherein, the device still includes: and an error correction returning unit 100, configured to record the cycle number of the static ECC error correction if the cycle number of the static ECC error correction is not equal to the value L, and return to execute the static ECC error correction if the flash rereading has finished all levels.

It should be noted that, as can be clearly understood by those skilled in the art, the specific implementation process of the static ECC error correction NAND error processing apparatus and each unit may refer to the corresponding description in the foregoing method embodiment, and for convenience and brevity of description, no further description is provided here.

The static ECC error corrected NAND error handling apparatus may be implemented in the form of a computer program that can be run on a computer device as shown in fig. 3.

Referring to fig. 3, fig. 3 is a schematic block diagram of a computer device according to an embodiment of the present application; the computer device 500 may be a terminal or a server, where the terminal may be an electronic device with a communication function, such as a smart phone, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of a plurality of servers.

Referring to fig. 3, the computer device 500 includes a processor 502, memory, and a network interface 505 connected by a system bus 501, where the memory may include a non-volatile storage medium 503 and an internal memory 504.

The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 comprises program instructions that, when executed, cause the processor 502 to perform a static ECC error correction NAND error handling method.

The processor 502 is used to provide computing and control capabilities to support the operation of the overall computer device 500.

The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503, and when the computer program 5032 is executed by the processor 502, the processor 502 can be enabled to execute a static ECC error correction NAND error handling method.

The network interface 505 is used for network communication with other devices. Those skilled in the art will appreciate that the configuration shown in fig. 3 is a block diagram of only a portion of the configuration associated with the present application and does not constitute a limitation of the computer device 500 to which the present application may be applied, and that a particular computer device 500 may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

Wherein the processor 502 is configured to run the computer program 5032 stored in the memory to implement the following steps:

step S1, if the page data has ECC error, then entering into normal flash memory re-reading state;

step S2, judging whether ECC error occurs when entering into normal flash memory re-reading state;

step S3, if entering the normal flash memory rereading state and generating ECC error, judging whether the flash memory rereading has done all levels;

step S4, if the flash memory rereads all the levels, executing static ECC error correction;

step S5, determining whether an ECC error occurs during static ECC error correction;

step S6, if ECC error occurs during static ECC, obtaining a PE value, and right-shifting the PE value by 10 bits to obtain an L value;

step S7, judging whether the cycle number of the static ECC correction is equal to the L value;

in step S8, if the number of cycles of static ECC error correction is equal to the value L, then the load decoding is performed.

It should be understood that in the embodiment of the present Application, the Processor 502 may be a Central Processing Unit (CPU), and the Processor 502 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like. Wherein a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It will be understood by those skilled in the art that all or part of the flow of the method implementing the above embodiments may be implemented by a computer program instructing associated hardware. The computer program includes program instructions, and the computer program may be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the flow steps of the embodiments of the method described above.

Accordingly, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program comprises program instructions that, when executed by a processor, may implement the static ECC error correction NAND error handling method described above. The storage medium stores a computer program comprising program instructions which, when executed by a processor, implement the method described above. The program instructions include the steps of:

step S2, judging whether ECC error occurs when entering the normal flash memory re-reading state;

step S3, if entering into normal flash memory rereading state and generating ECC error, judging whether the flash memory rereading has done all levels;

step S4, if the flash memory rereads all levels, executing static ECC error correction;

step S5, determining whether an ECC error occurs during static ECC correction;

The storage medium may be a usb disk, a removable hard disk, a Read-only memory (ROM), a magnetic disk or an optical disk, and various computer readable storage media that can store program codes.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or combinations of both, and that the components and steps of the examples have been described in a functional general in the foregoing description for the purpose of illustrating clearly the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative. For example, the division of each unit is only one logic function division, and there may be another division manner in actual implementation. For example, various elements or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented.

The steps in the method of the embodiment of the invention can be sequentially adjusted, combined and deleted according to actual needs. The units in the device of the embodiment of the invention can be combined, divided and deleted according to actual needs. In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in a storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a terminal, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention.

The above embodiments are preferred implementations of the present invention, and the present invention can be implemented in other ways without departing from the spirit of the present invention.

Claims

1. The NAND error processing method for static ECC error correction is characterized by comprising the following steps of:

if the flash memory rereads all levels, executing static ECC error correction;

judging whether ECC errors occur during static ECC correction;

2. The NAND error handling method for static ECC error correction according to claim 1, wherein if entering a normal flash re-reading state and an ECC error occurs, it determines whether the flash re-reading has completed all level steps, and if the flash re-reading has not completed all levels, it increases the level times that the flash re-reading needs to be performed, and returns to perform, and if the page data read and an ECC error occurs, it enters a normal flash re-reading state.

3. The NAND error handling method for static ECC error correction according to claim 1, wherein if the flash memory rereads all levels, the static ECC error correction step is performed by using a low density parity check code.

4. The NAND error handling method of static ECC error correction according to claim 1, wherein after the step of determining whether the number of cycles of static ECC error correction is equal to the value L, the method further comprises: and if the cycle number of the static ECC error correction is not equal to the value L, recording the cycle number of the static ECC error correction, and returning to execute the static ECC error correction if the flash memory rereads all levels.

5. A NAND error processing apparatus for static ECC error correction, comprising: the system comprises a generation entering unit, a first judging unit, a second judging unit, a first executing unit, a third judging unit, an obtaining unit, a fourth judging unit and a second executing unit;

the first judging unit is used for judging whether ECC errors occur when the normal flash memory rereading state is entered;

6. The static ECC corrected NAND error processing apparatus of claim 5, further comprising: and the adding and returning unit is used for increasing the level times which need to be executed by the flash memory rereading if the flash memory rereading does not finish all the levels, and returning to execute the flash memory rereading state if the page data is read and ECC errors occur.

7. The static ECC corrected NAND error handling device of claim 5, wherein static ECC correction is performed by low density parity check codes in the first execution unit.

8. The static ECC corrected NAND error processing apparatus of claim 5, further comprising: and the error correction returning unit is used for recording the cycle number of the static ECC error correction if the cycle number of the static ECC error correction is not equal to the value L, and returning to execute the static ECC error correction if the flash memory rereads all levels.

9. A computer device, characterized in that the computer device comprises a memory on which a computer program is stored and a processor which, when executing the computer program, implements the static ECC error correction NAND error handling method of any of claims 1-4.

10. A storage medium storing a computer program comprising program instructions which, when executed by a processor, implement the static ECC error corrected NAND error handling method of any of claims 1-4.