CN112133672B - Flash memory device and method of manufacturing the same - Google Patents

Flash memory device and method of manufacturing the same Download PDF

Info

Publication number
CN112133672B
CN112133672B CN201910548030.9A CN201910548030A CN112133672B CN 112133672 B CN112133672 B CN 112133672B CN 201910548030 A CN201910548030 A CN 201910548030A CN 112133672 B CN112133672 B CN 112133672B
Authority
CN
China
Prior art keywords
dielectric layer
region
layer
substrate
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910548030.9A
Other languages
Chinese (zh)
Other versions
CN112133672A (en
Inventor
杨政达
蒋汝平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Winbond Electronics Corp
Original Assignee
Winbond Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Winbond Electronics Corp filed Critical Winbond Electronics Corp
Priority to CN201910548030.9A priority Critical patent/CN112133672B/en
Publication of CN112133672A publication Critical patent/CN112133672A/en
Application granted granted Critical
Publication of CN112133672B publication Critical patent/CN112133672B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a flash memory device and a manufacturing method thereof. The first dielectric layer is formed on the substrate in the first region of the peripheral region. The second dielectric layer is formed on the substrate in the second region of the peripheral region. The third dielectric layer is formed on the substrate in the array region. The bottom surface of the third dielectric layer is lower than the bottom surface of the second dielectric layer. The first polysilicon layer is formed on the first dielectric layer and the second dielectric layer. The second polysilicon layer is formed on the third dielectric layer.

Description

Flash memory device and method of manufacturing the same
Technical Field
The present invention relates to a memory device, and more particularly, to a flash memory device and a method for manufacturing the same.
Background
In the manufacturing technology of the flash memory device, oxide layers with different thicknesses can be formed in a plurality of areas of one chip by multiple oxidation processes. Each region may correspond to a different operating voltage depending on the thickness of the oxide layer. Therefore, the flexibility of circuit design can be increased, and the product value can be improved.
However, in the conventional multiple oxidation process, the dopants included in the floating gate may enter the tunnel dielectric layer or penetrate the tunnel dielectric layer to enter the substrate, resulting in operation errors, thereby reducing the yield and reliability of the flash memory device.
Therefore, there is still a need in the field of flash memory devices for improvement of reliability and yield.
Disclosure of Invention
The embodiment of the invention provides a flash memory device and a manufacturing method thereof, which can prevent the reliability of a tunneling dielectric layer from being reduced due to the fact that a dopant penetrates through the tunneling dielectric layer, and can improve the thickness uniformity of the tunneling dielectric layer.
An embodiment of the invention discloses a flash memory device, comprising: the substrate comprises an array region and a peripheral region, wherein the peripheral region comprises a first region and a second region; a first dielectric layer formed on the substrate in the first region; a second dielectric layer formed on the substrate in the second region; a third dielectric layer formed on the substrate in the array region, wherein the bottom surface of the third dielectric layer is lower than the bottom surface of the second dielectric layer; the first polysilicon layer is formed on the first dielectric layer and the second dielectric layer, wherein the first polysilicon layer comprises a first doping substance; and a second polysilicon layer formed on the third dielectric layer, wherein the second polysilicon layer includes a second dopant.
An embodiment of the invention discloses a method for manufacturing a flash memory device, which comprises the following steps: providing a substrate, wherein the substrate comprises an array region and a peripheral region, and the peripheral region comprises a first region and a second region; forming a first dielectric layer on the substrate of the array region and the first region; forming a second dielectric layer on the substrate of the second region; forming a first polysilicon layer on the first dielectric layer and the second dielectric layer, wherein the first polysilicon layer comprises a first dopant; removing the first polysilicon layer and the first dielectric layer in the array region to expose the substrate in the array region; and forming a third dielectric layer on the substrate in the array region, wherein the bottom surface of the third dielectric layer is lower than the bottom surface of the second dielectric layer.
The manufacturing method of the flash memory device provided by the embodiment of the invention can avoid the problems of dopant penetration or uneven oxide layer thickness encountered by a triple oxidation process. Therefore, the yield and reliability of the flash memory device can be significantly improved.
Drawings
Fig. 1A to 1H are schematic cross-sectional views illustrating steps in manufacturing a flash memory device according to some embodiments of the present invention.
Description of the reference numerals
10-array area;
108-a photomask layer;
20 to a peripheral region;
110 to a first dielectric layer;
20A to a first region;
120-second dielectric layer;
20B to a second region;
130 to a first polysilicon layer;
20C to a third region;
132-nitride photomask layer;
100-flash memory device;
134 to a photoresist layer;
102 to a substrate;
140 to a third dielectric layer;
104 to a sacrificial layer;
150-second polysilicon layer;
106 to pad nitride layer;
165-a first nitridation process;
175 to a second nitridation process;
t2 to a second thickness;
t1 to a first thickness;
t3 to a third thickness.
Detailed Description
The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. Furthermore, repeated reference characters and/or words may be used in various examples of the invention. These repeated symbols or words are for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structures.
The terms "about" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The numbers given herein are about numbers, meaning that "about" may still be implied without specific recitation.
Fig. 1A to 1H are schematic cross-sectional views illustrating steps in a process of a flash memory device 100 according to some embodiments of the invention.
Referring to fig. 1A, a sacrificial layer 104 is formed on a substrate 102. The substrate 102 may include an array region 10 and a peripheral region 20 adjacent to the array region 10. The peripheral region 20 may include a plurality of regions corresponding to different operating voltages. In some embodiments, the peripheral region 20 includes a first region 20A, a second region 20B, and a third region 20C. It should be noted that the dimensions and arrangement of the first region, the second region and the third region shown in fig. 1A are only illustrative, and are not meant to limit the present invention.
In some embodiments, the substrate 102 may be a semiconductor substrate. In some embodiments, the material of the substrate 102 may include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon-on-insulator (silicon on insulator, SOI), other suitable materials, or combinations of the above. In the present embodiment, the substrate 102 is a silicon substrate. In some embodiments, other structures may be formed in the substrate 102. For example, a p-type well, an n-type well, or a conductive region (not shown) may be formed in the substrate 102 by an implantation process.
The material of sacrificial layer 104 may be an oxide. In some embodiments, sacrificial layer 104 may be formed by oxidizing the surface of substrate 102 by a thermal oxidation process. In other embodiments, sacrificial layer 104 may be formed on substrate 102 by a suitable deposition process. In this embodiment, the sacrificial layer 104 is formed before the implantation process, so that the surface of the substrate 102 is protected from damage.
Next, a pad nitride layer 106 is formed on the sacrificial layer 104, and a photomask layer 108 is formed on the pad nitride layer 106. Thereafter, the photomask layer 108 is patterned and the pad nitride layer 106 is partially removed by the patterned photomask layer 108. Wherein the pad nitride layer 106 in the second region 20B is retained and the pad nitride layer 106 in the array region 10, the first region 20A and the third region 20C is removed. Since the removal condition having a selective ratio to sacrificial layer 104 is employed, sacrificial layer 104 may act as an etch stop layer when liner nitride layer 106 is removed.
Referring to fig. 1B, the sacrificial layer 104 in the array region 10, the first region 20A and the third region 20C is removed to expose the substrate 102 in the array region 10, the first region 20A and the third region 20C. Next, a first dielectric layer 110 is formed on the substrate 102 in the array region 10, the first region 20A and the third region 20C. In this embodiment, the first dielectric layer 110 may be formed by oxidizing the surface of the substrate 102 by a first thermal oxidation process (e.g., a furnace process). Thus, the top surfaces of the substrate 102 in the array region 10, the first region 20A and the third region 20C are lower than the top surfaces of the second region 20B. In this embodiment, when removing the sacrificial layer 104, a selective ratio of the removal condition of the pad nitride layer 106 is selected, so that the pad nitride layer 106 can be used as a protection layer, and the sacrificial layer 104 located in the second region 20B is retained.
Referring to fig. 1C, the pad nitride layer 106 and the sacrificial layer 104 in the second region 20B are removed to expose the substrate 102 in the second region 20B. Next, a second dielectric layer 120 is formed on the substrate 102 in the second region 20B. The thickness of the second dielectric layer 120 is less than the thickness of the first dielectric layer 110. In this embodiment, the second dielectric layer 120 may be formed by oxidizing the surface of the substrate 102 by a second thermal oxidation process. After forming the second dielectric layer 120, a first nitridation process 165 is performed on the first dielectric layer 110 and the second dielectric layer 120. The first nitridation process 165 may include an oxynitride anneal process (NO annealing), a plasma nitridation anneal process (plasma nitridation annealing, PNA), or a plasma nitridation process (plasma nitridation, PN).
Referring to fig. 1D, a first polysilicon layer 130 is formed on the first dielectric layer 110 and the second dielectric layer 120. Next, a nitride photomask layer 132 and a photoresist layer 134 are sequentially formed on the first polysilicon layer 130. The photoresist layer 134 is then patterned to expose the nitride mask layer 132 in the array region 10 and the third region 20C.
The first polysilicon layer 130 may include a first dopant to enhance the conductivity of the first polysilicon layer 130. Thus, the first polysilicon layer 130 may be used as a floating gate or other conductive device. In some embodiments, a polysilicon layer may be deposited and then the first dopant may be doped into the polysilicon layer. In other words, the first polysilicon layer 130 is formed by ex-situ (ex-situ) deposition. In this embodiment, the polysilicon layer is deposited and doped with the first dopant. In other words, the first polysilicon layer 130 is formed by in-situ (in-situ) deposition. In this embodiment, the time and cost of the deposition process can be reduced.
The first dopant may be a p-type dopant or an n-type dopant. Specifically, the first dopant may be boron, gallium, phosphorus, arsenic, or other suitable dopant. In this embodiment, the first dopant is boron and the first polysilicon layer 130 is a p-type floating gate. The p-type floating gate has better charge retention than the n-type floating gate. Therefore, the thickness of the floating gate and the tunneling dielectric layer can be made smaller, thereby facilitating miniaturization of the flash memory device. Furthermore, if a p-type floating gate is used, the write operation can be performed at a lower voltage. Therefore, the performance of the flash memory device can be improved.
Referring to fig. 1E, the nitride photomask layer 132, the first polysilicon layer 130 and the first oxide layer 110 in the array region 10 and the third region 20C are removed by patterning the photoresist layer 134 to expose the substrate 102 in the array region 10 and the third region 20C.
Referring to fig. 1F, a third dielectric layer 140 is formed on the substrate 102 in the array region 10 and the third region 20C. In this embodiment, the third dielectric layer 140 may be formed by oxidizing the surface of the substrate 102 through a third thermal oxidation process. After forming the third dielectric layer 140, a second nitridation process 175 is performed on the third dielectric layer 140 in the array region 10 and the third region 20C. The second nitridation process 175 may include an oxynitride annealing process, a plasma nitridation annealing process, or a plasma nitridation process. In some embodiments, the second nitridation process 175 is the same as the first nitridation process 165, and thus, process complexity may be reduced. In other embodiments, the second nitridation process 175 is different from the first nitridation process 165.
Referring to fig. 1G, a second polysilicon layer 150 is formed on the third dielectric layer 140 and the nitride photomask layer 132. The second polysilicon layer 150 may include a second dopant to enhance the conductivity of the second polysilicon layer 150. Thus, the second polysilicon layer 150 may be used as a floating gate or other conductive device. The material and process for forming the second polysilicon layer 150 may be the same as the material and process for forming the first polysilicon layer 130, and will not be described in detail herein. Furthermore, the second dopant may be the same as or different from the first dopant. In this embodiment, the first dopant and the second dopant are both boron, and the first polysilicon layer 130 and the second polysilicon layer 150 are p-type floating gates.
Referring to fig. 1H, the nitride photomask layer 132 and the second polysilicon layer 150 in the first region 20A and the second region 20B are removed, and the first polysilicon layer 130 in the first region 20A and the second region 20B is exposed. Thereafter, other conventional processes (e.g., forming control gates, patterning floating gates, and patterning control gates) may be performed to complete flash memory device 100. Other conventional processes are not described in detail herein.
In some embodiments, the method of manufacturing the flash memory device includes a triple oxidation process, and thus, three dielectric layers having different thicknesses may be formed in different regions of the substrate. More specifically, referring to fig. 1H, a first dielectric layer 110, a second dielectric layer 120 and a third dielectric layer 140 having different thicknesses are respectively formed in the first region 20A, the second region 20B and the third region 20C of the peripheral region 20. Furthermore, a third dielectric layer 140 is also formed in the array region 10. The third dielectric layer 140 in the array region 10 can control the switching of the memory cells by tunneling effect, and therefore, in this specification, the third dielectric layer 140 in the array region 10 is also referred to as "tunneling dielectric layer".
When the thickness of the second dielectric layer 120 is smaller than that of the first dielectric layer 110 and the second dielectric layer 120 is an oxide layer, the first dopant in the first polysilicon layer 130 may penetrate the second dielectric layer 120 and enter the substrate. Similarly, when the thickness of the third dielectric layer 140 is smaller than the thickness of the first dielectric layer 110 and the third dielectric layer 140 is an oxide layer, the second dopant in the second polysilicon layer 150 may penetrate through the third dielectric layer 140 and enter the substrate. In this way, operation errors are caused, and the yield and reliability of the flash memory device are reduced. In this embodiment, the first dopant is boron. The problem of dopant penetration becomes more serious than other dopants, which have smaller volumes of boron dopant.
In order to solve the above-mentioned problem of dopant penetration, as shown in fig. 1C and 1F, a nitridation process may be performed on the oxide layer to form a very thin nitride layer on the surface of the oxide layer, so as to block the dopants in the first polysilicon layer 130 and the second polysilicon layer 150 formed later from entering the oxide layer or the substrate.
However, the nitridation process may cause a portion of nitrogen atoms to diffuse into the oxide layer, so that the surface of the substrate exposed by the nitrided oxide layer is not smooth, resulting in uneven thickness of the tunnel dielectric layer formed later. For some flash memory devices (e.g., NAND FLASH), the quality and thickness uniformity of the tunnel dielectric layer of the array region are important conditions that influence the probability of tunneling. If the thickness of the tunneling dielectric layer in the array region is not uniform, electrons tunnel from the thinner region of the dielectric layer, so that the thinner region of the dielectric layer is easily damaged and leakage current is generated, thereby easily causing operation errors. In this way, the yield, lifetime and reliability of the flash memory device are reduced.
Referring to fig. 1B, in the present embodiment, a first dielectric layer 110 is formed in the array region 10, the first region 20A and the third region 20C at the same time. By providing the thicker first dielectric layer 110 prior to performing the first nitridation process 165 (as depicted in fig. 1C), nitrogen atoms in the subsequent nitridation process 165 are prevented from accumulating on the surface of the substrate 102. Thus, after removing the first dielectric layer 110 of the array region 10 and the third region 20C, the surface of the exposed substrate 102 is flat. The third dielectric layer 140 formed in the array region 10 and the third region 20C may have a substantially uniform thickness even though the thickness of the third dielectric layer 140 is small. Thus, the problem of uneven thickness of the oxide layer can be avoided, and the service life and reliability of the flash memory device can be improved.
Similarly, since the third dielectric layer 140 is formed before the second nitridation process 175, even if a small amount of nitrogen atoms exist on the surface of the substrate 102 due to the subsequent second nitridation process 175, the thickness uniformity of the formed third dielectric layer 140 is hardly affected. Thus, the problem of uneven thickness of the oxide layer can be avoided, and the service life and reliability of the nonvolatile memory device can be improved.
Furthermore, when the third dielectric layer 140 is an oxide layer, a thermal oxidation process is performed after the floating gate is patterned to repair the damage of the tunnel dielectric layer at the edge of the pattern. However, the edges of the floating gate are oxidized, and bird's beak effect (bird's beak effect) occurs. The performance and yield of the flash memory device may be reduced due to the reduced conductivity of the partially oxidized floating gate. As the size is miniaturized, the effect of bird's beak effect becomes more serious. In this embodiment, by performing the second nitridation process 175 on the third dielectric layer 140, oxygen in the third dielectric layer 140 is prevented from entering the second polysilicon layer 150, thereby reducing the bird's beak effect.
Some embodiments of the present invention provide a flash memory device 100. Referring to fig. 1H, the flash memory device 100 includes a substrate 102. The substrate 102 includes an array region 10 and a peripheral region 20, and the peripheral region 20 includes a first region 20A, a second region 20B and a third region 20C. The flash memory device 100 includes a first dielectric layer 110, a second dielectric layer 120, and a third dielectric layer 140 formed on a substrate 102. The first dielectric layer 110 is located in the first region 20A. The second dielectric layer 120 is located in the second region 20B. The third dielectric layer 140 is located in the array region 10 and the third region 20C. The flash memory device 100 includes a first polysilicon layer 130 and a second polysilicon layer 150. The first polysilicon layer 130 is formed on the first dielectric layer 110 and the second dielectric layer 120. The second polysilicon layer 150 is formed on the third dielectric layer 140. The first polysilicon layer 130 includes a first dopant and the second polysilicon layer 150 includes a second dopant. In the present embodiment, the first dielectric layer 110, the second dielectric layer 120 and the third dielectric layer 130 are all oxide layers subjected to nitridation treatment. In this embodiment, the first dopant and the second dopant are both boron. In another embodiment, the first dielectric layer 110, the second dielectric layer 120 and the third dielectric layer 130 may comprise silicon nitride or/and a high dielectric constant material.
Referring to fig. 1H, a dashed line AA' represents a top surface of the substrate 102 or a bottom surface of the second dielectric layer 120 in the second region 20B. In this embodiment, the top surfaces of the substrate 102 in the array region 10, the first region 20A and the third region 20C are lower than the top surfaces of the substrate 102 in the second region 20B. That is, the bottom surface of the first dielectric layer 110 and the bottom surface of the third dielectric layer 140 are lower than the bottom surface of the second dielectric layer 120. In addition, in an embodiment not shown, the third dielectric layer 140 is formed by performing a thermal oxidation process on the substrate 102, so that the bottom surface of the third dielectric layer 140 is lower than the bottom surface of the first dielectric layer 110.
In the present embodiment, the first dielectric layer 110 located in the first region 20A has a first thickness T1. The second dielectric layer 120 in the second region 20B has a second thickness T2. The third dielectric layer 140 in the third region 20C and the array region 10 has a third thickness T3. The first thickness T1 is greater than the second thickness T2 and the third thickness T3. The third thickness T3 is greater than the second thickness T2. The thicker the dielectric layer, the higher the operating voltage corresponding to the dielectric layer, so the first operating voltage corresponding to the first region 20A is greater than the second operating voltage corresponding to the second region 20B and greater than the third operating voltage corresponding to the third region 20C and the array region 10. And the third operating voltage is greater than the second operating voltage.
In some embodiments, the first thickness T1 of the first dielectric layer 110 is 10-40nm to avoid accumulation of nitrogen atoms on the surface of the substrate 102. In some embodiments, the third thickness T3 of the third dielectric layer 140 is 5-9nm, thereby improving the performance and lifetime of the nonvolatile memory device 100. In some embodiments, the second thickness T2 of the second dielectric layer 120 is 1-4nm, such that the peripheral region 20 can have a second operating voltage lower than the third operating voltage.
In the manufacturing method of the present embodiment, the first dielectric layer 110, the second dielectric layer 120 and the third dielectric layer 140 may be formed independently. Furthermore, in the flash memory device 100 of the present embodiment, the peripheral region 20 includes 3 dielectric layers with different thicknesses, and can correspond to 3 different operation voltages, so that the flexibility of circuit design can be greatly increased.
In summary, the method for manufacturing a flash memory device according to the embodiments of the present invention can avoid the problems of dopant penetration and uneven oxide layer thickness. Therefore, the yield, reliability, performance and life of the flash memory device can be significantly improved. Furthermore, the method for manufacturing the flash memory device provided by the embodiment of the invention does not use an additional photomask or developing process. Therefore, the method can be easily integrated into the existing process, and the time and cost for production are not affected. In addition, the dielectric layers of different regions may be formed independently of each other. Therefore, the process flexibility of the flash memory device can be greatly improved.
Although the invention has been described with respect to several preferred embodiments, it will be understood by those skilled in the art that various changes, modifications and alterations may be made without departing from the spirit and scope of the invention, and it is intended that the invention be limited only by the claims appended hereto.

Claims (13)

1. A method of manufacturing a flash memory device, the method comprising:
providing a substrate, wherein the substrate comprises an array region and a peripheral region, and the peripheral region comprises a first region, a second region and a third region;
forming a first dielectric layer on the substrate in the array region, the first region and the third region;
forming a second dielectric layer on the substrate in the second region, wherein the second dielectric layer is an oxide layer;
after the second dielectric layer is formed, performing a first nitridation process on the second dielectric layer;
forming a first polysilicon layer on the first dielectric layer and the second dielectric layer, wherein the first polysilicon layer comprises a first dopant;
removing the first polysilicon layer and the first dielectric layer in the array region and the third region to expose the substrate in the array region and the third region; and
forming a third dielectric layer on the substrate in the array region and the third region, wherein the bottom surface of the third dielectric layer is lower than the bottom surface of the second dielectric layer;
wherein the method further comprises:
before forming the first dielectric layer, forming a sacrificial layer on the substrate, and removing the sacrificial layer in the array region and the first region to expose the substrate in the array region and the first region; and
removing the sacrificial layer in the second region after forming the first dielectric layer to expose the substrate in the second region,
the step of forming the first dielectric layer comprises a first thermal oxidation process on the substrate, and the step of forming the second dielectric layer comprises a second thermal oxidation process on the substrate.
2. The method of manufacturing a flash memory device according to claim 1, further comprising:
after forming the third dielectric layer, performing a second nitridation process on the third dielectric layer,
wherein the third dielectric layer is an oxide layer.
3. The method of claim 2, wherein the first nitridation process and the second nitridation process comprise an oxynitride annealing process, a plasma nitridation annealing process, or a plasma nitridation process.
4. The method of manufacturing a flash memory device according to claim 1, wherein a first nitridation process is performed on the first dielectric layer after forming the second dielectric layer.
5. The method of manufacturing a flash memory device according to claim 2, wherein the thickness of the first dielectric layer is 10-40nm.
6. The method of manufacturing a flash memory device of claim 1, wherein the second dielectric layer has a thickness of 1-4nm.
7. The method of claim 1, wherein the thickness of the third dielectric layer is 5-9nm.
8. The method of claim 2, wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, the third dielectric layer has a third thickness, and wherein the first thickness is greater than the second thickness and the third thickness, and the third thickness is greater than the second thickness.
9. A flash memory device manufactured according to the manufacturing method of the flash memory device according to any one of claims 1 to 8, characterized in that the device comprises:
the substrate comprises the array region and the peripheral region, and the peripheral region comprises the first region, the second region and the third region;
the first dielectric layer is formed on the substrate positioned in the first area;
the second dielectric layer is formed on the substrate positioned in the second area;
the third dielectric layer is formed on the substrate positioned in the array region and the third region, wherein the bottom surface of the third dielectric layer is lower than the bottom surface of the second dielectric layer;
the first polysilicon layer is formed on the first dielectric layer and the second dielectric layer, wherein the first polysilicon layer comprises the first dopant; and
a second polysilicon layer formed on the third dielectric layer, wherein the second polysilicon layer comprises a second dopant;
wherein the second dielectric layer is an oxide layer subjected to nitridation treatment.
10. The flash memory device of claim 9, wherein the first dielectric layer and the third dielectric layer are nitrided oxide layers.
11. The flash memory device of claim 10, wherein the first dielectric layer has a first thickness, the second dielectric layer has a second thickness, the third dielectric layer has a third thickness, and wherein the first thickness is greater than the second thickness and the third thickness, and the third thickness is greater than the second thickness.
12. The flash memory device of claim 9, wherein the first dopant and the second dopant are both boron.
13. The flash memory device of claim 10, wherein a bottom surface of the third dielectric layer in the array region is coplanar with a bottom surface of the third dielectric layer in the third region.
CN201910548030.9A 2019-06-24 2019-06-24 Flash memory device and method of manufacturing the same Active CN112133672B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910548030.9A CN112133672B (en) 2019-06-24 2019-06-24 Flash memory device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910548030.9A CN112133672B (en) 2019-06-24 2019-06-24 Flash memory device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
CN112133672A CN112133672A (en) 2020-12-25
CN112133672B true CN112133672B (en) 2024-04-12

Family

ID=73849967

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910548030.9A Active CN112133672B (en) 2019-06-24 2019-06-24 Flash memory device and method of manufacturing the same

Country Status (1)

Country Link
CN (1) CN112133672B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001338996A (en) * 2000-05-26 2001-12-07 Hitachi Ltd Non-volatile semiconductor storage device and its manufacturing method
KR20070000664A (en) * 2005-06-28 2007-01-03 삼성전자주식회사 Method of manufacturing a flash memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100375220B1 (en) * 2000-10-12 2003-03-07 삼성전자주식회사 Method of Making Flash Memory Devices

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001338996A (en) * 2000-05-26 2001-12-07 Hitachi Ltd Non-volatile semiconductor storage device and its manufacturing method
KR20070000664A (en) * 2005-06-28 2007-01-03 삼성전자주식회사 Method of manufacturing a flash memory device

Also Published As

Publication number Publication date
CN112133672A (en) 2020-12-25

Similar Documents

Publication Publication Date Title
US20220157993A1 (en) Flash memory device
US20120108051A1 (en) Different gate oxides thicknesses for different transistors in an integrated circuit
KR101225410B1 (en) Nonvolatile memory device and manufacturing method thereof
US9343537B2 (en) Split gate embedded memory technology and manufacturing method thereof
US8796129B2 (en) Nonvolatile storage device and method for manufacturing the same in which insulating film is located between first and second impurity diffusion regions but absent on first impurity diffusion region
KR20080009445A (en) Method of manufacturing flash semiconductor device
CN103208459B (en) The manufacture method of not b gate type flash memory devices
CN112133672B (en) Flash memory device and method of manufacturing the same
US7301193B2 (en) Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell
US6642111B1 (en) Memory device structure and method of fabricating the same
EP3493268A1 (en) Method of manufacturing semiconductor device
US6514807B1 (en) Method for fabricating semiconductor device applied system on chip
US20240038874A1 (en) Manufacturing method of semiconductor device
CN109461733B (en) Method for manufacturing flash memory device
KR20050023650A (en) Method for fabricating semiconductor device having salicide
US6673676B2 (en) Method of fabricating a flash memory cell
KR20060005177A (en) A gate electrode of nonvolatile memory device and a method for forming the same
KR100423576B1 (en) Fabricating method of flash memory device for reducing undercut and noise
KR100475033B1 (en) Manufacturing method of nonvolatile memory device
KR100943133B1 (en) Transistor of semiconductor device and forming method thereof
KR100741275B1 (en) Method for fabrication of semiconductor device
KR100339431B1 (en) Method for fabricating of semiconductor device
KR100356480B1 (en) Method of manufacturing a flash memory cell
KR100447218B1 (en) Structure of flash memory device and Method for manufacturing of the same
US20060014345A1 (en) Uniform channel programmable erasable flash EEPROM

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant