CN109461733B - Method for manufacturing flash memory device - Google Patents
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- CN109461733B CN109461733B CN201811216570.9A CN201811216570A CN109461733B CN 109461733 B CN109461733 B CN 109461733B CN 201811216570 A CN201811216570 A CN 201811216570A CN 109461733 B CN109461733 B CN 109461733B
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Abstract
The invention provides a manufacturing method of a flash memory device, which comprises the following steps: providing a substrate with a storage region and a peripheral region, wherein at least one floating gate is formed on the storage region, and N-type ions or P-type ions are doped in the floating gate; and the side wall of the floating gate closest to the peripheral region, which faces the peripheral region, is exposed; forming a blocking side wall on the side wall, which is closest to the peripheral area and faces the peripheral area, of the floating gate; and forming a gate oxide layer on the surface of the substrate in the peripheral region. According to the technical scheme, doped ions in the floating gate of the flash memory device can be prevented from diffusing into the peripheral region under the action of high temperature, so that the growth of the gate oxide layer on the peripheral region and the influence on the original doping in the floating gate are avoided, and the reliability of the flash memory device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more particularly, to a method for manufacturing a flash memory device.
Background
Flash memory (Flash) is a programmable, erasable memory that is widely used as the best choice for non-volatile memory applications due to its advantages of high density and low price. In order to prevent the loss of electrons stored in the floating gate, the floating gate in the conventional flash memory is simultaneously surrounded by a tunneling oxide layer at the bottom, a silicon oxide-silicon nitride-silicon oxide (ONO) layer at the periphery and at the top, so as to realize a long-term information maintaining state.
The flash memory device generally comprises a storage area and a peripheral area, and for the storage area in the flash memory device, the reliability is the most important, and the accuracy of stored information can be influenced; reliability of the peripheral region (various circuits for supplying voltage source, current source, and read/write operations) in the flash memory device is also important, and reliability of the memory region and the peripheral region may be affected by a manufacturing process of the flash memory device. The conventional flash memory device manufacturing process generally includes: forming shallow trench isolation structures higher than the surface of a substrate in substrates of a peripheral region and a storage region respectively, then depositing a floating gate polycrystalline silicon layer on the peripheral region and the storage region, performing phosphorus ion heavily-doped ion implantation and annealing on the floating gate polycrystalline silicon layer, and performing chemical mechanical polishing until the top surface of the shallow trench isolation structures is exposed; etching to remove the floating gate polysilicon layer on the peripheral region, and etching back the shallow trench isolation structure in the storage region to the bottom surface of the floating gate polysilicon layer to form a plurality of floating gates on the storage region; then forming an ONO inter-gate insulating layer on the peripheral region and the storage region, and etching to remove the ONO inter-gate insulating layer on the peripheral region, wherein the side wall of the floating gate closest to the peripheral region facing the peripheral region is exposed because the side wall is not covered by the ONO inter-gate insulating layer; and then forming a high-voltage gate oxide layer on the high-voltage device area of the peripheral area, performing low-voltage well ion implantation on the substrate of the low-voltage device area of the peripheral area, and forming a low-voltage gate oxide layer on the low-voltage device area of the peripheral area. Because the side wall of the floating gate closest to the peripheral region, which faces the peripheral region, is exposed outside, in the high-temperature process of forming the high-voltage gate oxide layer of the peripheral region, heavily doped phosphorus in the floating gate can be released under the action of high temperature and further diffused to the high-voltage device region and the low-voltage device region of the peripheral region, so that the growth speed and the growth quality of the high-voltage gate oxide layer in the peripheral region can be influenced, for example, the thickness of the finally formed high-voltage gate oxide layer is insufficient, and the thin high-voltage gate oxide layer is easy to break down when the flash memory device is loaded with high voltage; the released phosphorus can also influence the growth speed and the growth quality of the low-voltage gate oxide layer in the peripheral region after being diffused into the substrate or the tunneling oxide layer of the low-voltage device region in the peripheral region; in addition, the floating gate closest to the peripheral region may also affect the original doping due to the release of phosphorus, so that the doping concentration of the floating gate is different from that of other floating gates, thereby affecting the reliability of the flash memory device.
Therefore, how to prevent phosphorus in the floating gate of the flash memory device from diffusing to the peripheral region to avoid affecting the growth of the gate oxide layer on the peripheral region and the original doping in the floating gate, and further improve the reliability of the flash memory device is a problem to be solved.
Disclosure of Invention
The present invention provides a method for manufacturing a flash memory device, which can prevent ions in a floating gate of the flash memory device from diffusing into a peripheral region, so as to avoid the influence on the growth of a gate oxide layer on the peripheral region and on the original doping in the floating gate, thereby improving the reliability of the flash memory device.
To achieve the above object, the present invention provides a method of manufacturing a flash memory device, comprising:
providing a substrate with a storage region and a peripheral region, wherein at least one floating gate is formed on the storage region, and N-type ions or P-type ions are doped in the floating gate; and the side wall of the floating gate closest to the peripheral region, which faces the peripheral region, is exposed;
forming a blocking side wall on the side wall, which is closest to the peripheral area and faces the peripheral area, of the floating gate; and the number of the first and second groups,
and forming a gate oxide layer on the surface of the substrate in the peripheral region.
Optionally, the step of forming the floating gate includes:
sequentially forming a tunneling oxide layer and a floating gate polycrystalline silicon layer on the substrate;
carrying out ion implantation on the floating gate polycrystalline silicon layer by adopting N-type ions or P-type ions;
etching the floating gate polysilicon layer to remove the floating gate polysilicon layer on the peripheral region and form at least one floating gate on the storage region;
depositing an inter-gate insulating layer on the substrate with the floating gate; removing the inter-gate insulating layer on the peripheral region, and simultaneously exposing the side wall, facing the peripheral region, of the floating gate closest to the peripheral region;
alternatively, the step of forming the floating gate includes:
sequentially forming a tunneling oxide layer and a floating gate polycrystalline silicon layer on the substrate, wherein a plurality of shallow trench isolation structures higher than the surface of the substrate are formed in the storage region, and the floating gate polycrystalline silicon layer fills the trenches between the adjacent shallow trench isolation structures;
carrying out ion implantation on the floating gate polycrystalline silicon layer by adopting N-type ions or P-type ions;
chemical mechanical polishing planarizes the floating gate polysilicon layer to the top surface of the shallow trench isolation structure;
etching to remove the floating gate polysilicon layer on the peripheral region, and etching back the shallow trench isolation structure in the storage region to the bottom surface of the floating gate polysilicon layer to form at least one floating gate on the storage region;
depositing an inter-gate insulating layer on the substrate with the floating gate; removing the inter-gate insulating layer on the peripheral region, and simultaneously exposing the side wall, facing the peripheral region, of the floating gate closest to the peripheral region;
alternatively, the step of forming the floating gate includes:
sequentially forming a tunneling oxide layer, a floating gate polycrystalline silicon layer doped with N-type ions or P-type ions and an inter-gate insulating layer on the substrate;
sequentially etching the inter-gate insulating layer and the floating gate polycrystalline silicon layer to remove the inter-gate insulating layer and the floating gate polycrystalline silicon layer on the peripheral region and form at least one floating gate on the storage region, wherein the inter-gate insulating layer covers the top surface of each floating gate; and when the barrier side wall is formed, the barrier side wall is formed on all the side walls of the floating gate.
Optionally, the inter-gate insulating layer includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence from bottom to top.
Optionally, the method for forming the barrier sidewall includes rapid thermal oxidation.
Optionally, the thickness of the barrier sidewall is
Optionally, the material of the barrier sidewall does not contain nitrogen.
Optionally, the peripheral region comprises a peripheral high-voltage region and a peripheral low-voltage region, and the peripheral high-voltage region and the peripheral low-voltage region are separated by a shallow trench isolation structure; the step of forming a gate oxide layer on the substrate surface of the peripheral region includes: forming a first gate oxide layer on the peripheral high voltage region; performing trap ion implantation to the peripheral low-voltage region; and forming a second gate oxide layer on the peripheral low-voltage region and the peripheral high-voltage region.
Optionally, when the material of the blocking side wall includes a material other than silicon dioxide, the blocking side wall is removed after the first gate oxide layer is formed or after trap ion implantation is performed on the peripheral low-voltage region.
Optionally, after forming the second gate oxide layer, the method further includes: forming a control gate polysilicon layer on the storage region and the peripheral region; and etching the control gate polysilicon layer to simultaneously form a control gate on the inter-gate insulating layer of the storage region and a peripheral gate on the second gate oxide layer of the peripheral high-voltage region and the peripheral low-voltage region.
Compared with the prior art, the manufacturing method of the flash memory device has the advantages that before the gate oxide layer on the peripheral region grows, the floating gate closest to the peripheral region in the storage region faces the peripheral region and is exposed on the side wall to form the blocking side wall so as to block doped ions in the floating gate from diffusing into the peripheral region under the action of high temperature, the growth of the gate oxide layer on the peripheral region and the influence on the original doping in the floating gate are avoided, and the reliability of the flash memory device is improved.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a flash memory device according to an embodiment of the present invention;
fig. 2a to 2e are device diagrams in a method of manufacturing the flash memory device shown in fig. 1.
Wherein the reference numerals of the accompanying figures 1-2 e are as follows:
10-a substrate; 11-a storage area; 12-a peripheral region; 121-peripheral high-pressure region; 122-peripheral low-voltage region; 20-shallow trench isolation structures; 30-tunneling oxide layer; 40-a floating gate polysilicon layer; 41-floating gate; 50-an inter-gate insulating layer; 60-barrier side walls; 70-a gate oxide layer; 71-a first gate oxide layer; 72-second gate oxide layer.
Detailed Description
To make the objects, advantages and features of the present invention more clear, the following describes the manufacturing method of the flash memory device in detail with reference to fig. 1-2 e. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a flash memory device, and referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a flash memory device according to an embodiment of the present invention, where the method for manufacturing a flash memory device includes:
step S1-A, providing a substrate with a storage area and a peripheral area, wherein at least one floating gate is formed on the storage area, and N-type ions or P-type ions are doped in the floating gate; and the side wall of the floating gate closest to the peripheral region, which faces the peripheral region, is exposed;
step S1-B, forming a blocking side wall on the side wall of the floating gate closest to the peripheral area, which faces the peripheral area;
and step S1-C, forming a gate oxide layer on the surface of the substrate in the peripheral area.
The method for manufacturing the flash memory device according to the present embodiment will be described in more detail with reference to fig. 2a to 2e, and fig. 2a to 2e are device diagrams in the method for manufacturing the flash memory device shown in fig. 1.
First, referring to fig. 2a to 2c, according to step S1-a, providing a substrate 10 having a storage region 11 and a peripheral region 12, wherein at least one floating gate 41 is formed on the storage region 11, and the floating gate 41 is doped with N-type ions or P-type ions; and the sidewalls of the floating gates 41 closest to the peripheral region 12 facing the peripheral region 12 are exposed. A tunnel oxide layer 30 is further formed on the storage region 11 and the peripheral region 12, and an inter-gate insulating layer 50 is further formed on a top surface of the floating gate 41. The inter-gate insulating layer 50 includes a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, which are sequentially stacked from bottom to top. The peripheral region 12 includes a peripheral high-voltage region 121 and a peripheral low-voltage region 122, and the peripheral high-voltage region 121 and the peripheral low-voltage region 122 are isolated by a shallow trench isolation structure 20. The N-type ions may include one or more of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and the P-type ions may include one or more of boron (B), aluminum (Al), gallium (Ga), and indium (In). As can be seen from fig. 2a to 2c, the step of forming the floating gate 41 may include: firstly, sequentially forming a tunneling oxide layer 30 and a floating gate polysilicon layer 40 on the substrate 10, forming a plurality of shallow trench isolation structures 20 higher than the surface of the substrate 10 in the storage region 11, and filling the trenches between adjacent shallow trench isolation structures 20 with the floating gate polysilicon layer 40; then, carrying out ion implantation on the floating gate polysilicon layer 40 by adopting N-type ions or P-type ions, and carrying out annealing treatment; then, planarizing the floating gate polysilicon layer 40 to the top surface of the shallow trench isolation structure 20 by using a chemical mechanical polishing process, as shown in fig. 2 a; then, etching to remove the floating gate polysilicon layer 40 on the peripheral region 12, and etching back the shallow trench isolation structure 20 in the storage region 11 to the bottom surface of the floating gate polysilicon layer 40 to form at least one floating gate 41 on the storage region 11, as shown in fig. 2 b; finally, an inter-gate insulating layer 50 is deposited on the substrate 10 having the floating gate 41, and the inter-gate insulating layer 50 on the peripheral region 12 is removed by etching, and at the same time, the side wall of the floating gate 41 closest to the peripheral region 12 facing the peripheral region 12 is exposed, as shown in fig. 2 c.
In addition, the step of forming the floating gate may include (not shown): firstly, sequentially forming a tunneling oxide layer and a floating gate polycrystalline silicon layer on the substrate; then, carrying out ion implantation on the floating gate polycrystalline silicon layer by adopting N-type ions or P-type ions; then, etching the floating gate polysilicon layer to remove the floating gate polysilicon layer on the peripheral region and form at least one floating gate on the storage region; then, depositing an inter-gate insulating layer on the substrate with the floating gate; finally, removing the inter-gate insulating layer on the peripheral region, and simultaneously exposing the side wall, facing the peripheral region, of the floating gate closest to the peripheral region. The step of forming the floating gate may further include (not shown): firstly, sequentially forming a tunneling oxide layer, a floating gate polycrystalline silicon layer doped with N-type ions or P-type ions and an inter-gate insulating layer on the substrate; then, etching the inter-gate insulating layer and the floating gate polysilicon layer in sequence to remove the inter-gate insulating layer and the floating gate polysilicon layer on the peripheral region and form at least one floating gate on the storage region, wherein the inter-gate insulating layer covers the top surface of each floating gate; and when the barrier side wall is formed in the subsequent process, the barrier side wall is formed on all the side walls of the floating gate.
Then, referring to fig. 2d, according to step S1-B, a blocking sidewall 60 is formed on the sidewall of the floating gate 41 closest to the peripheral region 12 facing the peripheral region 12. The material of the barrier sidewall 60 may not contain nitrogen, for example, when the material of the barrier sidewall 60 is silicon dioxide, the material of the silicon dioxide does not affect the performance of the peripheral region 12, so that the barrier sidewall 60 does not need to be removed in the subsequent formation process of the gate oxide layer 70. When the material of the barrier sidewall 60 includes a material other than silicon dioxide, for example, a nitrogen-containing material, since the nitrogen-containing material may affect the performance of the peripheral region 12, the barrier sidewall 60 needs to be removed after the first gate oxide layer 71 is formed or after the trap ion implantation is performed on the peripheral low voltage region 122. The method for forming the barrier sidewall 60 may be Rapid Thermal Oxidation (RTO), specifically, the substrate 10 including the floating gate 41 may be placed in a process chamber for rapid oxidation, a tungsten halogen lamp is used as a radiation heat source, parameters in the process chamber are set, for example, a process temperature is set to 800 ℃ -950 ℃ (for example, 850 ℃, 900 ℃ and the like), a reaction time is set to 10 s-90 s (for example, 20s, 50s, 80s and the like), and parameters such as an oxygen flow rate and a reaction pressure are set, so as to form a thin and dense layer of the barrier sidewall 60. The thickness of the barrier sidewall spacers 60 may be formed as follows
(for example, is
Etc.), can be controlled by adjusting the process temperature of the rapid thermal oxidationTime and the like are used to obtain the required thickness of the barrier sidewall 60. The rapid thermal oxidation method has the characteristics of short reaction time, fast temperature rise speed, and the like, and can rapidly form the barrier sidewall 60 on the sidewall of the floating gate 41 facing the peripheral region 12.
Finally, referring to fig. 2e, a gate oxide layer 70 is formed on the surface of the substrate 10 in the peripheral region 12 according to step S1-C. The step of forming the gate oxide layer 70 on the surface of the substrate 10 in the peripheral region 12 includes: first, a first gate oxide layer 71 is formed on the peripheral high voltage region 121; then, well ion implantation is performed to the peripheral low-voltage region 122; finally, a second gate oxide layer 72 is formed on the peripheral low-voltage region 122 and the peripheral high-voltage region 121, or the second gate oxide layer 72 can be directly formed on the peripheral low-voltage region 122. The material of the first gate oxide layer 71 and the second gate oxide layer 72 may be silicon dioxide. The method of forming the first gate oxide layer 71 and the second gate oxide layer 72 may be Rapid Thermal Oxidation (RTO) or high temperature thermal oxidation (HTO), since the first gate oxide layer 71 and the second gate oxide layer 72 are formed at a temperature of 800-950 ℃ (e.g., 850 ℃, 900 ℃, etc.), if the sidewall of the floating gate 41 facing the peripheral region 12 is not provided with the barrier sidewall 60, under the action of high temperature, the doped N-type ions or P-type ions in the floating gate 41 are released, diffused into the process chamber, and further diffused to the peripheral high voltage region 121 and the peripheral low voltage region 122, the growth rate and the growth quality of the first gate oxide layer 71 are affected, for example, resulting in an insufficient thickness of the finally formed first gate oxide layer 71, when the flash memory device is loaded with high voltage, the thinner first gate oxide layer 71 is easy to break down; and the released doping ions also affect the growth speed and the growth quality of the second gate oxide layer 72 after diffusing into the substrate 10 or the tunnel oxide layer 30 of the peripheral low-voltage region 122; in addition, the floating gate 41 closest to the peripheral region 12 may also affect the original doping due to the release of the doping ions, so that the doping concentration of the floating gate is different from that of other floating gates, thereby affecting the reliability of the flash memory device.
In addition, after the second gate oxide layer is formed, the process steps which can be continued further include: forming a control gate polysilicon layer on the storage region and the peripheral region; and etching the control gate polysilicon layer to simultaneously form a control gate on the inter-gate insulating layer of the storage region and a peripheral gate on the second gate oxide layer of the peripheral high-voltage region and the peripheral low-voltage region to obtain the flash memory device.
In summary, the method for manufacturing a flash memory device provided by the present invention includes: providing a substrate with a storage region and a peripheral region, wherein at least one floating gate is formed on the storage region, and N-type ions or P-type ions are doped in the floating gate; and the side wall of the floating gate closest to the peripheral region, which faces the peripheral region, is exposed; forming a blocking side wall on the side wall, which is closest to the peripheral area and faces the peripheral area, of the floating gate; and forming a gate oxide layer on the surface of the substrate in the peripheral region. According to the technical scheme, doped ions in the floating gate of the flash memory device can be prevented from diffusing into the peripheral region under the action of high temperature, so that the growth of the gate oxide layer on the peripheral region and the influence on the original doping in the floating gate are avoided, and the reliability of the flash memory device is improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (5)
1. A method of manufacturing a flash memory device, comprising:
providing a substrate with a storage region and a peripheral region, wherein at least one floating gate is formed on the storage region, and N-type ions or P-type ions are doped in the floating gate; and the side wall of the floating gate closest to the peripheral region, which faces the peripheral region, is exposed;
forming a blocking side wall on the side wall, which is closest to the peripheral area and faces the peripheral area, of the floating gate; and the number of the first and second groups,
forming a gate oxide layer on the surface of the substrate in the peripheral region, wherein the gate oxide layer is formed at a high temperature of 800-900 ℃;
wherein the peripheral region comprises a peripheral high-voltage region and a peripheral low-voltage region, the peripheral high-voltage region and the peripheral low-voltage region being separated by a shallow trench isolation structure; the step of forming the gate oxide layer on the substrate surface of the peripheral region includes: forming a first gate oxide layer on the peripheral high voltage region; performing trap ion implantation to the peripheral low-voltage region; and forming a second gate oxide layer on the peripheral low-voltage region and the peripheral high-voltage region; and the barrier side wall is made of a nitrogen-containing material, and is removed after the first gate oxide layer is formed or after trap ion implantation is performed on the peripheral low-voltage region.
2. The method of manufacturing a flash memory device according to claim 1, wherein the step of forming the floating gate includes:
sequentially forming a tunneling oxide layer and a floating gate polycrystalline silicon layer on the substrate;
carrying out ion implantation on the floating gate polycrystalline silicon layer by adopting N-type ions or P-type ions;
etching the floating gate polysilicon layer to remove the floating gate polysilicon layer on the peripheral region and form at least one floating gate on the storage region;
depositing an inter-gate insulating layer on the substrate with the floating gate; removing the inter-gate insulating layer on the peripheral region, and simultaneously exposing the side wall, facing the peripheral region, of the floating gate closest to the peripheral region;
alternatively, the step of forming the floating gate includes:
sequentially forming a tunneling oxide layer and a floating gate polycrystalline silicon layer on the substrate, wherein a plurality of shallow trench isolation structures higher than the surface of the substrate are formed in the storage region, and the floating gate polycrystalline silicon layer fills the trenches between the adjacent shallow trench isolation structures;
carrying out ion implantation on the floating gate polycrystalline silicon layer by adopting N-type ions or P-type ions;
chemical mechanical polishing planarizes the floating gate polysilicon layer to the top surface of the shallow trench isolation structure;
etching to remove the floating gate polysilicon layer on the peripheral region, and etching back the shallow trench isolation structure in the storage region to the bottom surface of the floating gate polysilicon layer to form at least one floating gate on the storage region;
depositing an inter-gate insulating layer on the substrate with the floating gate; removing the inter-gate insulating layer on the peripheral region, and simultaneously exposing the side wall, facing the peripheral region, of the floating gate closest to the peripheral region;
alternatively, the step of forming the floating gate includes:
sequentially forming a tunneling oxide layer, a floating gate polycrystalline silicon layer doped with N-type ions or P-type ions and an inter-gate insulating layer on the substrate;
sequentially etching the inter-gate insulating layer and the floating gate polycrystalline silicon layer to remove the inter-gate insulating layer and the floating gate polycrystalline silicon layer on the peripheral region and form at least one floating gate on the storage region, wherein the inter-gate insulating layer covers the top surface of each floating gate; and when the barrier side wall is formed, the barrier side wall is formed on all the side walls of the floating gate.
3. The method of manufacturing a flash memory device according to claim 2, wherein the inter-gate insulating layer comprises a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, which are sequentially stacked from bottom to top.
4. The method of manufacturing a flash memory device according to claim 1, wherein a thickness of the barrier side wall is 15A-50A.
5. The method of manufacturing a flash memory device according to claim 1, further comprising, after forming the second gate oxide layer: forming a control gate polysilicon layer on the storage region and the peripheral region; and etching the control gate polysilicon layer to simultaneously form a control gate on the inter-gate insulating layer of the storage region and a peripheral gate on the second gate oxide layer of the peripheral high-voltage region and the peripheral low-voltage region.
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