CN112131822B

CN112131822B - CPU chip and design method thereof

Info

Publication number: CN112131822B
Application number: CN202011044820.2A
Authority: CN
Inventors: 沈琪; 晋大师; 王毓千
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2020-09-28
Filing date: 2020-09-28
Publication date: 2022-12-09
Anticipated expiration: 2040-09-28
Also published as: CN112131822A

Abstract

The embodiment of the invention discloses a CPU chip and a design method thereof, belongs to the technical field of integrated circuits, and is used for solving the problem that the existing CPU chip is poor in effect when ECO is realized. The CPU chip comprises a plurality of redundant logic units which are uniformly distributed in the CPU chip according to a preset uniform distribution strategy; the redundancy logic unit comprises a plurality of logic components which are gathered together, and the input end of the redundancy logic unit is electrically connected with the corresponding connection suspension input TIE unit. The invention is suitable for all integrated circuit chip designs.

Description

CPU chip and design method thereof

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a CPU chip and a design method thereof.

Background

With the development of the integration process, the sizes of the CMOS transistor and the metal wiring are smaller and smaller, the chip scale and the integration density are higher and higher, the reliability and controllability of the process in the chip manufacturing process are reduced, and the design method for improving the reliability in the chip manufacturing process by improving the design in the chip design process becomes a significant link in the chip design field. On the other hand, the cost and cost of chip production are rapidly increasing with the increase of integration, so the cost factor must be considered throughout all aspects of the chip design field. Reliability design often increases reliability by introducing redundancy in the circuit, which is costly. Reliability design, which is cost-effective, is becoming a hot spot in this area.

Adding redundant logic cells (spare cells) in a circuit is an effective means for improving the reliability of design, and the principle is to add redundant standard cells in each area of the circuit, and the cells have some simple logic functions or memory functions. When the initial design of the chip finds problems in the verification after the completion of the tape (the problems may be multifaceted, may be a process problem, may be a layout structure problem, and may also be a functional problem caused by insufficient previous functional verification), the problems need to be corrected by changing or adjusting the structure of a certain part of the circuit, the changes can be completed by the spare cell added in advance in the design stage, and the metal connection of the corresponding pin of the spare cell only needs to be modified. During plate making, various problems found in the initial flow sheet of the chip can be conveniently corrected only by replacing masks of a plurality of layers of metals needing to be modified by a factory. Compared with redesigning and reflow, the design period of the method is greatly reduced, and the design cost is also obviously reduced.

A commonly used method for adding redundancy logic is to randomly scatter some combinational logic and sequential logic inside a chip, and usually such redundancy logic is randomly placed inside the chip and is relatively a dispersed structure, so that, many times, if some functions need to be changed, if there are not enough types of redundancy logic nearby, it may be necessary to find the redundancy logic from a relatively far position to implement an ECO, so that the workload of the ECO is relatively large, and the effect may not necessarily meet the expected target.

Disclosure of Invention

In view of this, embodiments of the present invention provide a CPU chip and a design method thereof, so as to solve the problem that an effect is not good when an ECO is implemented due to a random position of a redundant logic unit added in the existing CPU chip design.

In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:

in a first aspect, an embodiment of the present invention provides a CPU chip, including a plurality of redundant logic units, where the plurality of redundant logic units are uniformly distributed in the CPU chip according to a predetermined uniform distribution strategy; the redundant logic unit comprises a plurality of logic components which are gathered together, and the input end of the redundant logic unit is electrically connected with the corresponding connecting suspension input TIE unit.

With reference to the first aspect, in a first implementation manner of the first aspect, the redundant logic units are uniformly distributed in the CPU chip at predetermined intervals.

With reference to the first aspect, in a second implementation manner of the first aspect, N redundant logic units are uniformly distributed in a CPU chip according to an area of the CPU chip;

the using number N of the redundant logic units is determined by N = M a, M is the total number of the first logic units in the CPU chip, and a is a preset proportion; the first logic unit is other logic units except the redundant logic unit which are required for realizing the functions of the CPU chip.

With reference to the first aspect, in a third implementation manner of the first aspect, the redundancy logic unit includes: the device comprises a buffer, an inverter, a selector, a register and an ECO logic unit; the buffer, the inverter, the selector, the register and the ECO logic unit are gathered together through a preset placing strategy.

With reference to the third implementation manner of the first aspect, in a fourth possible implementation manner of the first aspect, the predetermined placement policy is:

placing the buffer and the inverter in a first row, with the buffer disposed to the left of the inverter;

placing the selector and the register on a second row, wherein the selector is arranged on the left side of the register;

and placing the ECO logic units in a third row.

In a second aspect, an embodiment of the present invention provides a method for designing a CPU chip, where when a step of layout planning, floorplan, of a chip design flow is executed, before a first logic unit is laid out, the method includes:

uniformly distributing a plurality of redundant logic units in the CPU chip;

connecting the input end of the redundant logic unit to a corresponding connection suspension input TIE unit;

the redundancy logic unit comprises a plurality of logic components which are gathered together, and the first logic unit is other logic units except the redundancy logic unit which are required for realizing the functions of the CPU chip.

With reference to the second aspect, in a first implementation manner of the second aspect, the uniformly distributing a plurality of preset redundant logic units in the CPU chip includes:

and uniformly distributing the redundant logic units in the CPU chip according to a preset distance.

With reference to the second aspect, in a second implementation manner of the second aspect, the uniformly distributing a plurality of preset redundant logic units in the CPU chip includes:

uniformly distributing N redundant logic units in the CPU chip according to the area of the CPU chip;

the using number N of the redundant logic units is determined by N = M × a, M is the total number of the first logic units in the CPU chip, and a is a preset proportion.

With reference to the second aspect, in a third implementation manner of the second aspect, before uniformly distributing a plurality of preset redundant logic units in the CPU chip, the method further includes:

and gathering the buffer, the inverter, the selector, the register and the ECO logic unit together through a preset placing strategy to form the redundant logic unit.

With reference to the third implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the gathering the buffer, the inverter, the selector, the register, and the ECO logic unit together by using a predetermined placement policy includes:

and placing the ECO logic units in a third row.

In the CPU chip and the design method thereof provided by the embodiment of the invention, a plurality of selected hardware components are gathered together as a group of cell list to be used as redundant logic units, the redundant logic units are uniformly distributed in the CPU chip according to a certain distance or a certain proportion and are connected with the input ends of all redundant logic units, so that the required logic components can be found out from the group of redundant logic units nearby for ECO through metal connecting wires in the later ECO process, and the problem of poor ECO realization effect caused by random positions of the redundant logic units in the design process of the traditional CPU chip can be solved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a CPU chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an arrangement of redundant logic units according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a redundant logic unit according to an embodiment of the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Fig. 1 is a schematic structural diagram of a CPU chip according to an embodiment of the present invention. As shown in fig. 1, the chip includes a plurality of redundant logic units 1, and the plurality of redundant logic units 1 are uniformly distributed in the CPU chip according to a predetermined uniform distribution strategy; for convenience of representation, only 6 redundant logic cells 1 are schematically shown in fig. 1. Each redundant logic unit 1 comprises a plurality of logic components which are gathered together, and the input end of the redundant logic unit 1 is electrically connected with a corresponding connection floating input TIE unit (not shown in fig. 1).

In an optional embodiment, the predetermined uniform distribution strategy is uniform distribution according to distance, that is: the redundant logic units 1 are uniformly distributed in the CPU chip at a predetermined pitch, for example, as shown in fig. 2, the pitch of the plurality of redundant logic units 1 in the transverse direction of the CPU chip is 50um, the pitch of the plurality of redundant logic units in the longitudinal direction is 10um, and the redundant logic units are uniformly distributed in a grid shape.

In another optional embodiment, the predetermined uniform distribution strategy is uniform distribution according to a chip area, specifically, the total number of the first logic units in the CPU chip is M, and a preset ratio is a; calculating the using number N of the required redundant logic units, and uniformly distributing the N redundant logic units in the CPU chip according to the area of the CPU chip; wherein N = M × a, the first logic unit is another logic unit except the redundant logic unit 1, which is required to implement the function of the CPU chip.

In an alternative embodiment, the present invention provides a redundant logic cell 1 comprising: the device comprises a buffer, an inverter, a selector, a register and an ECO logic unit; the buffer, the inverter, the selector, the register and the ECO logic unit are gathered together through a preset placing strategy. Preferably, as shown in fig. 3, the predetermined placement strategy is: placing a Buffer (BUF) 11 and an Inverter (INV) 12 in a first row, with the Buffer (BUF) 11 disposed on the left side of the Inverter (INV) 12; the selector (MUX) 13 and the register (FF) 14 are placed in the second row, and the selector (MUX) 13 is disposed on the left side of the register (FF) 14; an ECO logic cell (ECO DECAP) 15 is laid out in the third row.

According to the CPU chip, a plurality of selected hardware components are gathered together as a group of cell list to serve as the redundant logic unit, the redundant logic units are uniformly distributed in the CPU chip according to a certain distance or a certain proportion and are connected with the input ends of all the redundant logic units, the required logic components can be found out from the group of redundant logic units nearby for ECO through metal connecting lines in the later ECO process, the problem that the effect is poor when ECO is achieved due to the random positions of the redundant logic units in the existing CPU chip design process is solved, the chip design success rate is improved, the change is convenient, and the chip waste is reduced.

Corresponding to the CPU chip provided in the embodiment of the present invention, an embodiment of the present invention further provides a design method of a CPU chip, which may sequentially include a preparation stage assembly step, a Floorplan step, a Place optimization step, a clock tree synthesis Cts step, a routing step, and a layout and routing end PrFinish step, similar to a general chip design method, where in the method provided in the present invention, when the Floorplan step of the chip design flow is executed, before a first logic unit is laid out, the method includes the following steps:

s101: uniformly distributing a plurality of preset redundant logic units in the CPU chip;

s102: connecting the input end of the redundant logic unit to a corresponding connection suspension input TIE unit;

The method provided by the embodiment is used for realizing the device shown in fig. 1, and a plurality of redundant logic units are arranged and uniformly arranged in the target CPU chip in the early stage, so that the ECO operation is conveniently performed in the later stage.

Preferably, step S101 may include: and uniformly distributing the redundant logic units in the CPU chip according to a preset distance.

Preferably, step S101 may include: uniformly distributing N redundant logic units in the CPU chip according to the area of the CPU chip; the using number N of the redundant logic units is determined by N = M × a, M is the total number of the first logic units in the CPU chip, and a is a preset proportion.

In an alternative embodiment, before step S101, the method further includes the steps of: and gathering the buffer, the phase inverter, the selector, the register and the ECO logic unit together through a preset placing strategy to form the redundant logic unit. Preferably, the buffer and the inverter are arranged in a first row, and the buffer is arranged at the left side of the inverter; placing the selector and the register on a second row, wherein the selector is arranged on the left side of the register; and placing the ECO logic units in a third row.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.

The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A CPU chip is characterized by comprising a plurality of redundant logic units, wherein the redundant logic units are uniformly distributed in the CPU chip according to a preset uniform distribution strategy; the redundant logic unit comprises a plurality of logic components which are gathered together through a preset placing strategy, and the input end of the redundant logic unit is electrically connected with the corresponding connection suspension input TIE unit; the preset uniform distribution strategies are uniformly distributed according to the distance or the chip area.

2. The CPU chip of claim 1, wherein the redundant logic units are evenly distributed in the CPU chip at predetermined intervals.

3. The CPU chip of claim 1, wherein N of said redundant logic units are evenly distributed in said CPU chip according to an area of said CPU chip;

the using number N of the redundant logic units is determined by N = M × a, M is the total number of the first logic units in the CPU chip, and a is a preset proportion; the first logic unit is other logic units except the redundant logic unit which are required for realizing the functions of the CPU chip.

4. The CPU chip of claim 1, wherein the redundancy logic unit comprises: the device comprises a buffer, an inverter, a selector, a register and an ECO logic unit; the buffer, the inverter, the selector, the register and the ECO logic unit are gathered together through a preset placing strategy.

5. The CPU chip of claim 4, wherein the predetermined placement strategy is:

and placing the ECO logic units in a third row.

6. A design method of a CPU chip is characterized in that when executing a layout planning Floorplan step of a chip design flow, before laying out a first logic unit, the method comprises the following steps:

uniformly distributing a plurality of preset redundant logic units in the CPU chip according to the distance or the chip area;

the redundant logic unit comprises a plurality of logic components which are gathered together through a preset placing strategy, and the first logic unit is other logic units except the redundant logic unit which are required for realizing the functions of the CPU chip.

7. The method for designing the CPU chip according to claim 6, wherein the step of uniformly distributing a plurality of predetermined redundant logic units in the CPU chip comprises:

8. The method for designing the CPU chip according to claim 6, wherein the step of uniformly distributing a plurality of predetermined redundant logic units in the CPU chip comprises:

9. The method for designing the CPU chip according to claim 6, wherein before the step of uniformly distributing a plurality of predetermined redundant logic units in the CPU chip, the method further comprises:

and gathering the buffer, the phase inverter, the selector, the register and the ECO logic unit together through a preset placing strategy to form the redundant logic unit.

10. The method of designing a CPU chip of claim 9, wherein said bringing together buffers, inverters, selectors, registers and ECO logic units by a predetermined placement strategy comprises:

and placing the ECO logic units in a third row.