CN112968948A - Gateway controller design method, gateway controller and automobile - Google Patents
Gateway controller design method, gateway controller and automobile Download PDFInfo
- Publication number
- CN112968948A CN112968948A CN202110137950.9A CN202110137950A CN112968948A CN 112968948 A CN112968948 A CN 112968948A CN 202110137950 A CN202110137950 A CN 202110137950A CN 112968948 A CN112968948 A CN 112968948A
- Authority
- CN
- China
- Prior art keywords
- gateway controller
- communication chip
- information
- chip
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000013461 design Methods 0.000 title abstract description 17
- 238000004891 communication Methods 0.000 claims abstract description 137
- 238000012360 testing method Methods 0.000 claims abstract description 55
- 238000012795 verification Methods 0.000 claims description 18
- 230000003993 interaction Effects 0.000 claims description 7
- 238000012545 processing Methods 0.000 claims description 6
- 230000006870 function Effects 0.000 abstract description 62
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000011161 development Methods 0.000 description 15
- 230000005540 biological transmission Effects 0.000 description 8
- 238000003745 diagnosis Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 8
- 239000000306 component Substances 0.000 description 6
- WXZOXVVKILCOPG-UHFFFAOYSA-N bis(2-ethylhexyl) benzene-1,3-dicarboxylate Chemical compound CCCCC(CC)COC(=O)C1=CC=CC(C(=O)OCC(CC)CCCC)=C1 WXZOXVVKILCOPG-UHFFFAOYSA-N 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 5
- 230000008569 process Effects 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010365 information processing Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000013522 software testing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/01—Protocols
- H04L67/12—Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40215—Controller Area Network CAN
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Health & Medical Sciences (AREA)
- Computing Systems (AREA)
- General Health & Medical Sciences (AREA)
- Medical Informatics (AREA)
- Small-Scale Networks (AREA)
Abstract
The invention discloses a gateway controller design method, a gateway controller and an automobile. The gateway controller design method comprises the following steps: acquiring the functional requirements of a user; determining structural information of a communication chip according to the functional requirements, wherein the structural information comprises the number of intellectual property cores of the communication chip, the number of the intellectual property cores is N, and N is more than or equal to 2; acquiring test information of the communication chip in a gateway controller; and adjusting the structure of the gateway controller according to the test information. The invention provides a gateway controller design method, a gateway controller and an automobile, which increase the functions of the gateway controller by customizing a communication chip integrated with at least 2 intellectual property cores according to the functional requirements of users, meet the functional requirements of the users, solve the problems of high cost and large volume caused by the fact that the conventional gateway controller uses a plurality of mass production chips, and improve the cost performance.
Description
Technical Field
The embodiment of the invention relates to the technical field of communication, in particular to a gateway controller design method, a gateway controller and an automobile.
Background
The gateway Controller is a core component in an electronic and electrical architecture of a whole vehicle, and is used as a data interaction hub of a whole vehicle Network, and CAN route Network data such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), an Ethernet (Ethernet) and the like in different networks. In addition, due to the existence of the independent gateway controller, the design of the electronic and electrical architecture of the whole automobile can be optimized, and a whole automobile factory can improve the expandability of the topological structure of the whole automobile, the safety of the whole automobile and the confidentiality of network data of the whole automobile. Gateway controllers have therefore increasingly become an essential component in the electronic and electrical architecture of a finished vehicle.
The existing gateway controller development scheme uses a mass production chip which is a single-core chip, and needs to use a plurality of chips due to insufficient functions, thereby increasing the cost and the volume and having lower cost performance.
Disclosure of Invention
The invention provides a gateway controller design method, a gateway controller and an automobile, which aim to reduce cost and volume and improve cost performance.
In a first aspect, an embodiment of the present invention provides a method for designing a gateway controller, where the method includes:
acquiring the functional requirements of a user;
determining structural information of a communication chip according to the functional requirements, wherein the structural information comprises the number of intellectual property cores of the communication chip, the number of the intellectual property cores is N, and N is more than or equal to 2;
acquiring test information of the communication chip in a gateway controller;
and adjusting the structure of the gateway controller according to the test information.
Optionally, after determining the structural information of the communication chip according to the functional requirement, the method further includes:
performing function verification on the communication chip through the FPGA board card to obtain a function verification result;
and adjusting the structural information of the communication chip according to the function verification result.
Optionally, obtaining test information of the communication chip in the gateway controller includes:
and carrying out HIL test on the gateway controller to acquire the test information of the communication chip in the gateway controller.
Optionally, performing HIL test on the gateway controller, including:
connecting the gateway controller with an HIL rack;
sending a test signal to the gateway controller through the HIL rack;
reading a return result from the gateway controller through the HIL rack, and performing function verification on the gateway controller according to the return result.
Optionally, before sending the test signal to the gateway controller through the HIL rack, the method further includes:
and placing the gateway controller into an environment bin to apply a vehicle-mounted environment to the gateway controller.
In a second aspect, an embodiment of the present invention further provides a gateway controller, where the gateway controller is obtained by the method for designing any gateway controller in the first aspect, and the gateway controller includes:
the system comprises a main control chip and a communication chip;
the main control chip is used for carrying out information interaction with the vehicle-mounted equipment;
the communication chip is electrically connected with the main control chip;
the structure information of the communication chip is matched with the functional requirements of a user, and the structure information comprises the number of intellectual property cores of the communication chip, wherein the number of the intellectual property cores is N, and N is more than or equal to 2.
Optionally, the master control chip is connected with a CAN bus;
the intellectual property core comprises an Ethernet switch, and the communication chip is respectively connected with the CAN bus and the Ethernet bus;
the communication chip is used for processing at least part of information of the CAN bus and/or the Ethernet bus received by the gateway controller and feeding back the processed information to the CAN bus and/or the Ethernet bus.
Optionally, the communication chip is connected to the main control chip through a PCIe bus.
Optionally, N is more than or equal to 5 and less than or equal to 10.
In a third aspect, an embodiment of the present invention further provides an automobile, including any one of the gateway controllers described in the second aspect.
According to the design method of the gateway controller provided by the embodiment of the invention, the communication chips in the gateway controller are customized according to the functional requirements of users, and the functions of the communication chips are increased by setting the number of the intellectual property cores in the communication chips to be at least 2, so that the functional requirements of the users are met, a plurality of chips are not needed, the cost and the volume are reduced, the problems of high cost and large volume caused by the fact that the conventional gateway controller uses a plurality of mass production chips are solved, and the cost performance is improved.
Drawings
Fig. 1 is a schematic flowchart of a method for designing a gateway controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an HIL test provided in an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a gateway controller according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an operating system according to an embodiment of the present invention;
fig. 5 is a system configuration diagram of a communication chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic flow chart of a method for designing a gateway controller according to an embodiment of the present invention, and as shown in fig. 1, the method for designing a gateway controller according to the embodiment of the present invention includes:
and step 110, acquiring the function requirement of the user.
Different users have different functional requirements on the gateway controller, and the gateway controller is required to be provided with 12 paths of high-speed CAN/CAN-FD channels, 2 paths of LIN channels, 1 path of 100base-Tx channels, 9 paths of 100base-T1 channels and 2 paths of 1000base-T1 channels exemplarily; the integrated vehicle-mounted Ethernet switch is required to have the cascade expansion capability of a plurality of vehicle-mounted Ethernet switches; the information exchange and network management among the CAN network, the LIN network and the Ethernet network are realized, and the real-time performance of the system and the safety of data transmission are ensured. Support VLAN MAC, TCP/IP, ARP, ICMP and other traditional Ethernet protocol functions, support SOME/IP, Service Discovery protocol functions, support DHCP protocol functions and support DOIP protocol functions. The diagnosis function is required to be provided with the functions of UDS CAN diagnosis and program flashing, DOIP diagnosis activation by using Active Line, mirror image configuration function and the like.
And 120, determining structural information of the communication chip according to the functional requirements, wherein the structural information comprises the number of intellectual property cores of the communication chip, the number of the intellectual property cores is N, and N is more than or equal to 2.
The communication chip is customized according to different functional requirements of different users, so that the communication chip can meet the functional requirements of the users. Specifically, the structural information of the communication chip is determined according to the functional requirements, the structural information includes the number of intellectual property cores (IPs) of the communication chip, and the number of the intellectual property cores is greater than 2.
Intellectual property cores (IPs) play a very important role in EDA technology development, and the semiconductor industry IP can be defined as a pre-designed circuit function block for use in an ASIC or FPGA. The IP is mainly classified into soft IP, fixed IP, and hard IP. The soft IP is a functional block described by using a hardware description language such as Verilog/VHDL, but does not relate to what specific circuit elements are used to realize the functions, the fixed IP is a functional block which is completed comprehensively, and the hard IP provides a final stage product of design, namely a mask.
The communication chip with at least two intellectual property cores is customized to meet the functional requirements of users, only a single communication chip is needed, resources can be utilized more effectively, redundant backup resources are avoided, the cost is lower, the size is smaller, the problems that an existing gateway controller uses a plurality of mass production chips, the cost is high, the size is large and the cost performance is improved are solved.
Step 130, obtaining the test information of the communication chip in the gateway controller.
After the communication chip is designed, the design file of the communication chip is subjected to wafer flow and packaging to produce the communication chip. Then, a gateway controller is designed, the gateway controller comprises the communication chip, and the gateway controller is tested to obtain the test information of the communication chip in the gateway controller.
And step 140, adjusting the structure of the gateway controller according to the test information.
The structure of the gateway controller is adjusted according to the test information of the communication chip in the gateway controller, so that the reliability and the stability of the gateway controller are ensured.
According to the design method of the gateway controller provided by the embodiment of the invention, the communication chips in the gateway controller are customized according to the functional requirements of users, and the functions of the communication chips are increased by setting the number of the intellectual property cores in the communication chips to be at least 2, so that the functional requirements of the users are met, a plurality of chips are not needed, the cost and the volume are reduced, the problems of high cost and large volume caused by the fact that the conventional gateway controller uses a plurality of mass production chips are solved, and the cost performance is improved.
Optionally, after determining the structural information of the communication chip according to the functional requirement, the method further includes:
and performing function verification on the communication chip through the FPGA board card to obtain a function verification result.
And adjusting the structural information of the communication chip according to the function verification result.
Specifically, in the initial development stage of the communication chip, the functions of the communication chip are verified and simulated by using the FPGA board card, and all-dimensional function and reliability tests are performed in the chip test. The FPGA board card is used for verifying and simulating the functions of the communication chip and can be divided into front simulation and rear simulation so as to simulate the functions of the communication chip to run, and the main purpose is to confirm whether the functional requirements of a user are completely realized and whether all the functions are correct. And adjusting the structural information of the communication chip according to the function verification result so as to ensure the reliability and stability of the communication chip.
It should be noted that, because the communication chip includes a plurality of intellectual property cores (IPs), the power supply current and the anti-interference development can be increased during the design process, for example, the power supply current is increased during the development to support the operation of a plurality of IPs, and compared with a single-IP mass-production chip, the current can be increased by 20%, and any other current can be set, and those skilled in the art can set the current according to actual requirements. In order to prevent the anti-interference capability of the communication chip from weakening, a common mode inductor can be added to improve the anti-interference capability, the common mode inductor can be arranged on a circuit board bearing the communication chip, and a person skilled in the art can set the common mode inductor according to actual requirements, which is not limited in the embodiment of the invention.
After the communication chip passes through the function verification of the FPGA board card, the design file is subjected to wafer flow and packaging to produce the communication chip, and then the communication chip is placed into a gateway controller to complete the design work of the gateway controller.
Optionally, obtaining test information of the communication chip in the gateway controller includes:
and carrying out HIL test on the gateway controller to acquire the test information of the communication chip in the gateway controller.
In the later development stage of the gateway controller, a hardware-in-loop (HIL) test and a hardware reliability and service life test can be performed on the gateway controller, and the test information of the communication chip in the gateway controller is obtained. The HIL test can shorten the development period of the gateway controller and reduce the development cost, meanwhile, the HIL test link is prior to the real vehicle test, partial limit working condition tests can be carried out in a ring test environment by utilizing hardware, the risk in the real vehicle test can be avoided, the HIL test can also rapidly simulate and reproduce a fault mode, and the risk and the difficulty of fault injection test on the real vehicle are solved.
Optionally, performing HIL test on the gateway controller, including:
and connecting the gateway controller with the HIL rack.
Test signals are sent to the gateway controller via the HIL bench.
Reading a return result from the gateway controller through the HIL rack, and performing function verification on the gateway controller according to the return result.
Fig. 2 is a schematic diagram of an HIL test according to an embodiment of the present invention, as shown in fig. 2, a gateway controller 14 is connected to an HIL rack 10, the HIL rack 10 includes a control module 11, a communication module 12 and a function checking module 13, and the communication module 12 is connected to the control module 11 and the function checking module 13, respectively. Firstly, an application program is used on the HIL to carry out reliability test on the gateway controller, the HIL builds a test model for the gateway controller 14 based on a simulation technology, typical working conditions encountered in real vehicle test are simulated, a sensor signal is simulated to generate a test signal, the control module 11 sends the test signal to the gateway controller 14 through the communication module 12, the function verification module 13 collects and reads a return result of the gateway controller 14, real-time communication is carried out on the gateway controller 14, and function verification is carried out on the gateway controller 14 according to the return result. Wherein, by changing various different test signals, the output of the gateway controller 14 is observed to verify all functions of the gateway controller 14, especially all communication functions of the communication chip, and to perform function verification on the communication chip, verify whether the logic relationship is realized according to the expected design requirements.
With continued reference to fig. 2, before transmitting the test signal to the gateway controller via the HIL jack, the method further includes:
and placing the gateway controller into an environment bin to apply a vehicle-mounted environment to the gateway controller.
The vehicle-mounted environment is applied to the gateway controller through the environment bin, the vehicle-mounted environment can comprise high and low temperature, temperature cycle, durability, damp and hot, vibration, interference environment and the like, and the functions of the communication chip in the vehicle-mounted environment can be tested, so that the reliability joint test of the HIL is added for the instability of the communication chip, and the closed-loop test is performed on all the functions of the communication chip in the automobile life test environment.
The embodiment of the invention provides a gateway controller design method, which is a gateway controller hardware development method based on vehicle-specification-level independent communication chip development, and is characterized in that functional requirements are provided for the communication chip in terms of requirements of a whole vehicle network architecture by acquiring user requirements, the communication chip is customized according to the functional requirements, and the functions of the communication chip are increased by increasing the number of intellectual property cores in the communication chip, so that more intellectual property cores are used for completing the communication function, the functional requirements of users are met, a plurality of chips are not required to be used, the cost and the volume are reduced, the problems of high cost and large volume caused by the fact that the conventional gateway controller uses a plurality of mass-production chips are solved, and the cost performance is improved. In addition, the gateway controller design method provided by the embodiment of the invention uses a vehicle-specification-level development process to carry out development and integration, and performs HIL test on the gateway controller in a vehicle-mounted environment based on application software, so that all functions and reliability of a communication chip are verified by using a vehicle-specification-level specification, the stability of the communication chip is ensured, the development period can be effectively shortened, and the risk of real vehicle test and calibration is reduced.
Based on the same inventive concept, an embodiment of the present invention further provides a gateway controller, fig. 3 is a schematic structural diagram of the gateway controller provided in the embodiment of the present invention, and as shown in fig. 3, the gateway controller 20 provided in the embodiment of the present invention is obtained by the method for designing a gateway controller described in any embodiment of the present invention, so that the gateway controller 20 provided in the embodiment of the present invention has the technical effects of the technical solutions in any embodiment, and the explanations of the structures and terms that are the same as or corresponding to those in the embodiment are not repeated herein.
As shown in fig. 3, the gateway controller provided in the embodiment of the present invention includes a main control chip 21 and a communication chip 22, where the main control chip 21 is used for performing information interaction with the vehicle-mounted device. The communication chip 22 is electrically connected with the main control chip 21, the structural information of the communication chip 22 is matched with the functional requirements of the user, and the structural information includes the number of intellectual property cores of the communication chip 22, wherein the number of the intellectual property cores is N, and N is not less than 2.
The main control chip 21 is configured to perform information interaction with the vehicle-mounted device, and may specifically adopt a single chip Microcomputer (MCU), where software modules such as application software, a communication protocol, and bottom layer software may be set in the MCU to implement information interaction with the communication chip 22.
In other embodiments, the main control chip 21 may also be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, a discrete Gate or transistor logic device, a discrete hardware component, etc., and those skilled in the art can set the configuration according to actual needs.
The communication chip 22 is electrically connected with the main control chip 21, and the structural information of the communication chip 22 matches with the functional requirements of the user, for example, the functional requirements are that the gateway controller is provided with 12 high-speed CAN/CAN-FD channels, 2 LIN channels, 1 100base-Tx channel, 9 100base-T1 channels, and 2 1000base-T1 channels; the integrated vehicle-mounted Ethernet switch is required to have the cascade expansion capability of a plurality of vehicle-mounted Ethernet switches; information exchange and network management among the CAN network, the LIN network and the Ethernet network are realized, and the real-time performance of the system and the safety of data transmission are ensured; the system supports traditional Ethernet protocol functions such as VLAN MAC, TCP/IP, ARP and ICMP, supports SOME/IP and Service Discovery protocol functions, supports DHCP protocol function and supports DOIP protocol function; the communication chip is required to have the following diagnosis functions, namely a UDS CAN diagnosis and program flashing function, a DOIP diagnosis and program flashing function, activation of DOIP diagnosis by using Active Line, and a mirror image configuration function, so that the communication chip is used for realizing the functions.
At least two intellectual property cores are integrated in the communication chip 22, the functional requirements of users are met by increasing the number of the intellectual property cores in the communication chip, only a single communication chip is needed, resources can be utilized more effectively, redundant backup resources are not needed, the cost is lower, the size is smaller, the problems that an existing gateway controller uses a plurality of mass production chips, the cost is high, the size is large are solved, and the cost performance is improved.
With continued reference to fig. 3, optionally, the main control chip 21 is connected to a CAN bus 23, the intellectual property core includes an Ethernet (ETH) switch, the communication chip 22 is connected to the CAN bus 23 and the Ethernet bus 24, respectively, and the communication chip 22 is configured to process at least part of the information of the CAN bus 23 and/or the Ethernet (ETH) bus 24 received by the gateway controller, and feed back the processed information to the CAN bus 23 and/or the Ethernet bus 24.
Among them, CAN (Controller Area Network ) is one of the most widely used field buses internationally as an international standard (ISO11898), and the main control chip 21 performs information interaction with the vehicle-mounted device through the CAN bus 23.
The Ethernet switch is integrated as an intellectual property core in the communication chip 22, so that the communication chip 22 has the functions of a vehicle-mounted Ethernet switch and the cascade expansion capability of a plurality of vehicle-mounted Ethernet switches, thereby realizing information exchange and network management among the CAN bus, the LIN bus and the Ethernet bus, and ensuring the real-time performance of the system and the safety of data transmission. The LIN bus is a low-cost serial communication Network defined for a distributed electronic system of an automobile, is a supplement to other automobile multi-path networks such as a CAN (Controller Area Network) and the like, and is suitable for application without high requirements on the bandwidth, performance or fault-tolerant function of the Network.
With continued reference to fig. 3, the communication chip 22 is connected to the CAN bus 23 and the ethernet bus 24, respectively, and the intellectual property core may further include a core 25, and the core 25 of the communication chip 22 is utilized to interact information of a part of the CAN bus 23 and the ethernet bus 24 without intervention of the main control chip 21, which helps to improve the information processing speed of the gateway controller. The kernel 25 pre-judges the types of the information of the CAN bus 23 and the Ethernet bus 24 in advance, and the information only needing a gateway controller is subjected to information circulation and is processed by the kernel 25; for the information that needs to be judged by the main control chip 21, the kernel 25 still transmits the information to the main control chip 21 for processing.
With continued reference to fig. 3, optionally, the communication chip 22 is connected to the master chip 21 via a PCIe bus 26.
The PCI-express (peripheral component interconnect express) is PCIe, is a high-speed serial computer expansion bus standard, belongs to high-speed serial point-to-point dual-channel high-bandwidth transmission, and is connected with devices which distribute independent channel bandwidth and do not share bus bandwidth, mainly supports functions of active power management, error reporting, end-to-end reliable transmission, hot plug, quality of service (QOS) and the like, and has the advantage of high data transmission rate. As shown in fig. 3, the kernel 25 pre-determines the types of the information of the CAN bus 23 and the ethernet bus 24 in advance, and for the information that needs to be determined by the main control chip 21, the kernel 25 transmits the information to the main control chip 21 through the PCIe bus 26 for processing, which is helpful to improve the information transmission speed.
Optionally, N is more than or equal to 5 and less than or equal to 10.
If the number of the intellectual property cores in the communication chip 22 is too small, the functional requirements of the user cannot be met, and if the number of the intellectual property cores in the communication chip 22 is too large, the power consumption of the communication chip 22 can be increased.
With continued reference to fig. 3, the gateway controller according to the embodiment of the present invention further includes a Power module (Power)27, where the Power module 27 may provide various voltages for the communication chip 25, and those skilled in the art may set the Power module 27 and the communication chip 25 according to actual requirements, for example, since the communication chip 25 includes a plurality of intellectual property cores (IPs), a higher Power voltage may be selected to support a plurality of IPs to work, which is not limited in the embodiment of the present invention.
In other embodiments, the Power module (Power)27 may also be disposed outside the gateway controller, and those skilled in the art may set the Power module according to actual requirements, which is not limited in the embodiments of the present invention.
It should be noted that, when designing the gateway controller, the main control chip 21 needs to be configured to cooperate with the communication chip 22 of the main control chip 21.
Fig. 4 is a schematic structural diagram of an operating system according to an embodiment of the present invention, and as shown in fig. 4, a bottom layer is a hardware layer, the hardware layer includes a main control chip 21, and the main control chip 21 may be a single chip Microcomputer (MCU).
The software layer is a bottom software layer above the hardware layer, the bottom software layer comprises a real-time Operating System (OS), a communication protocol stack and an MCAL (micro controller Abstraction layer), the operating system is operated on the main control chip 21 to ensure the system safety, thereby meeting the requirement of the automobile electronic function safety and realizing the real-time processing function of the gateway controller, wherein the MCAL is a microcontroller Abstraction layer and is a software module which can directly access an on-chip MCU peripheral module mapped to a memory and external equipment, so that the upper software layer is unrelated to the MCU, the MCAL provided by a chip manufacturer is used as a first layer driver, the MCAL interfaces of different chip manufacturers are consistent, and the replacement of a single chip microcomputer is convenient. In addition, the underlying software layer conforms to the AUTomotive Open System Architecture (AUTOSAR) standard to normalize the underlying software layer.
And an application software layer is arranged above the bottom software layer, and the power management function, the communication management function, the power on/off management function and the diagnosis management function are embodied in the application software layer. The development process of the application software layer comprises three steps of requirement, development and verification, and comprises a software design document, software development integration, software testing and the like.
Fig. 5 is a system configuration diagram of a communication chip according to an embodiment of the present invention, and as shown in fig. 5, a gateway controller selects an arrangement that can be increased or decreased according to a requirement of a whole vehicle, so as to increase or decrease corresponding intellectual property cores in the communication chip, thereby implementing an optimal function with a minimum cost.
The internal functions of the communication chip CAN comprise an ARM core, 4 paths of 100BASE-T1, 4 paths of 1000BASE-T1, other xmII, XPI, SMI and other expansion interfaces and 6 paths of CAN channels. Illustratively, as shown in fig. 5, TCM is a technical manner of CPU tightly coupled storage, gpio (general Purpose Input output) is a digital Input output interface, spi (serial Peripheral interface) is a serial communication interface, jtag (joint Test Action group) is a download interface, Switch is a Switch module, AVB/TSN 802.1 is an ethernet transmission protocol, uart (Universal Asynchronous Receiver/Transmitter) is a serial communication interface, can (controller Area network) and lin (local interface network) are vehicle communication interfaces, pcie (Peripheral interface), sgmi (Media TX index interface) and mii (local component interface) are vehicle communication interfaces, pcie (Peripheral component interface) is a Media interface, sgmi Media TX index interface and mii (Media TX index interface) are configured to communicate with each other through ethernet interface, eeprom (basic interface) is configured to communicate with each other through ethernet interface, and eeprom (basic component interface) is configured to multiple communication interfaces, and eeprom (host interface) is configured to communicate with each other through ethernet interface, ethernet interface is configured to multiple communication interfaces, and eeprom (host interface) is configured to a multiple communication interface for communicating with each other through ethernet interface, ethernet interface 35media access interface, and eeprom (host interface) is configured to a communication interface for communicating with each of a host, thereby realizing the functional requirements of the user.
In other embodiments, the gateway controller may further include other functional modules, for example, to prevent the interference rejection capability of the communication chip from becoming weak, a common mode inductor may be added to improve the interference rejection capability; and other functional modules such as an antenna and the like are arranged, and those skilled in the art can perform the arrangement according to actual requirements, which is not limited in the embodiment of the present invention.
According to the gateway controller provided by the embodiment of the invention, the functions of the gateway controller are increased by adopting the communication chip integrated with at least 2 intellectual property cores, so that the functional requirements of users are met, and meanwhile, a plurality of chips are not required, the cost and the volume are reduced, the problems of high cost and large volume caused by the fact that a plurality of mass production chips are used in the conventional gateway controller are solved, and the cost performance is improved. The communication chip 22 is arranged to interact information of a part of the CAN bus 23 and the Ethernet bus 24 without the intervention of the main control chip 21, so that the information processing speed of the gateway controller is improved.
Based on the same inventive concept, an embodiment of the present invention further provides an automobile, where the automobile includes the gateway controller provided in any embodiment of the present invention, and therefore, the automobile provided in the embodiment of the present invention has the technical effects of the technical solutions in any embodiment described above, and explanations of structures and terms that are the same as or corresponding to those in the embodiment described above are omitted here for brevity.
It should be noted that the vehicle provided in the embodiment of the present invention may further include other functional modules, such as a CAN bus, an ethernet bus, a LIN bus, and other vehicle-mounted devices, which may be set by a person skilled in the art according to actual needs, and the embodiment of the present invention does not limit this.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method for designing a gateway controller, comprising:
acquiring the functional requirements of a user;
determining structural information of a communication chip according to the functional requirements, wherein the structural information comprises the number of intellectual property cores of the communication chip, the number of the intellectual property cores is N, and N is more than or equal to 2;
acquiring test information of the communication chip in a gateway controller;
and adjusting the structure of the gateway controller according to the test information.
2. The method of claim 1, wherein after determining the configuration information of the communication chip according to the functional requirement, the method further comprises:
performing function verification on the communication chip through the FPGA board card to obtain a function verification result;
and adjusting the structural information of the communication chip according to the function verification result.
3. The method of claim 1, wherein obtaining the test information of the communication chip in the gateway controller comprises:
and carrying out HIL test on the gateway controller to acquire the test information of the communication chip in the gateway controller.
4. The method of claim 3, wherein performing the HIL test on the gateway controller comprises:
connecting the gateway controller with an HIL rack;
sending a test signal to the gateway controller through the HIL rack;
reading a return result from the gateway controller through the HIL rack, and performing function verification on the gateway controller according to the return result.
5. The method of claim 4, wherein before sending the test signal to the gateway controller via the HIL bench, the method further comprises:
and placing the gateway controller into an environment bin to apply a vehicle-mounted environment to the gateway controller.
6. A gateway controller, characterized in that the gateway controller is obtained by the method of designing a gateway controller according to any one of claims 1 to 5, the gateway controller comprising:
the system comprises a main control chip and a communication chip;
the main control chip is used for carrying out information interaction with the vehicle-mounted equipment;
the communication chip is electrically connected with the main control chip;
the structure information of the communication chip is matched with the functional requirements of a user, and the structure information comprises the number of intellectual property cores of the communication chip, wherein the number of the intellectual property cores is N, and N is more than or equal to 2.
7. The gateway controller of claim 6,
the master control chip is connected with the CAN bus;
the intellectual property core comprises an Ethernet switch, and the communication chip is respectively connected with the CAN bus and the Ethernet bus;
the communication chip is used for processing at least part of information of the CAN bus and/or the Ethernet bus received by the gateway controller and feeding back the processed information to the CAN bus and/or the Ethernet bus.
8. The gateway controller of claim 6, wherein the communication chip is coupled to the master chip via a PCIe bus.
9. The gateway controller of claim 6, wherein N is 5 ≦ N ≦ 10.
10. A vehicle comprising a gateway controller as claimed in any one of claims 6 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110137950.9A CN112968948A (en) | 2021-02-01 | 2021-02-01 | Gateway controller design method, gateway controller and automobile |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110137950.9A CN112968948A (en) | 2021-02-01 | 2021-02-01 | Gateway controller design method, gateway controller and automobile |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112968948A true CN112968948A (en) | 2021-06-15 |
Family
ID=76272873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110137950.9A Pending CN112968948A (en) | 2021-02-01 | 2021-02-01 | Gateway controller design method, gateway controller and automobile |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112968948A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113378508A (en) * | 2021-07-09 | 2021-09-10 | 安谋科技（中国）有限公司 | Intellectual property core of pipeline structure, customization method thereof and system on chip |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080107188A1 (en) * | 2001-03-20 | 2008-05-08 | Lightwaves Systems, Inc. | High bandwidth data transport system |
| WO2009058149A1 (en) * | 2007-10-29 | 2009-05-07 | Lightwaves Systems, Inc. | Improved high bandwidth data transport system |
| CN107124125A (en) * | 2017-06-08 | 2017-09-01 | 西南交通大学 | A kind of multiaxis controllor for step-by-step motor system based on fpga chip |
| CN108156062A (en) * | 2017-08-18 | 2018-06-12 | 上海金脉电子科技有限公司 | The gateway controller of various communications protocols including compatible Ethernet and CAN FD |
| CN108696424A (en) * | 2017-04-07 | 2018-10-23 | 上汽通用汽车有限公司 | Vehicle communication system |
| CN111158967A (en) * | 2019-12-31 | 2020-05-15 | 北京百度网讯科技有限公司 | Artificial intelligence chip testing method, device, equipment and storage medium |
| CN111277476A (en) * | 2018-12-04 | 2020-06-12 | 广州汽车集团股份有限公司 | Gateway controller function verification method, gateway controller function verification device, computer equipment and storage medium |
| CN111638706A (en) * | 2020-06-05 | 2020-09-08 | 中国第一汽车股份有限公司 | System and method for testing gateway controller |
| CN112131822A (en) * | 2020-09-28 | 2020-12-25 | 海光信息技术股份有限公司 | CPU chip and design method thereof |
-
2021
- 2021-02-01 CN CN202110137950.9A patent/CN112968948A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080107188A1 (en) * | 2001-03-20 | 2008-05-08 | Lightwaves Systems, Inc. | High bandwidth data transport system |
| WO2009058149A1 (en) * | 2007-10-29 | 2009-05-07 | Lightwaves Systems, Inc. | Improved high bandwidth data transport system |
| CN108696424A (en) * | 2017-04-07 | 2018-10-23 | 上汽通用汽车有限公司 | Vehicle communication system |
| CN107124125A (en) * | 2017-06-08 | 2017-09-01 | 西南交通大学 | A kind of multiaxis controllor for step-by-step motor system based on fpga chip |
| CN108156062A (en) * | 2017-08-18 | 2018-06-12 | 上海金脉电子科技有限公司 | The gateway controller of various communications protocols including compatible Ethernet and CAN FD |
| CN111277476A (en) * | 2018-12-04 | 2020-06-12 | 广州汽车集团股份有限公司 | Gateway controller function verification method, gateway controller function verification device, computer equipment and storage medium |
| CN111158967A (en) * | 2019-12-31 | 2020-05-15 | 北京百度网讯科技有限公司 | Artificial intelligence chip testing method, device, equipment and storage medium |
| CN111638706A (en) * | 2020-06-05 | 2020-09-08 | 中国第一汽车股份有限公司 | System and method for testing gateway controller |
| CN112131822A (en) * | 2020-09-28 | 2020-12-25 | 海光信息技术股份有限公司 | CPU chip and design method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113378508A (en) * | 2021-07-09 | 2021-09-10 | 安谋科技（中国）有限公司 | Intellectual property core of pipeline structure, customization method thereof and system on chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10996950B2 (en) | Apparatuses and methods involving selective disablement of side effects caused by accessing register sets | |
| CN105095037A (en) | Wire card, backboard of wire card and wire card test method | |
| CN115496018A (en) | Multi-version verification method, device and equipment for SoC (System on chip) | |
| CN114417768A (en) | Digital-analog hybrid simulation method and system of Ethernet chip | |
| CN112968948A (en) | Gateway controller design method, gateway controller and automobile | |
| CN117311313A (en) | Test method and system, calculation processing end and readable storage medium | |
| CN101599050B (en) | Adaptable pci express controller core and method | |
| WO2002067515A1 (en) | Method and system for generating multiple self-id packets on the 1394 bus using a standard phy chip | |
| CN111708661A (en) | Pressure testing system and method suitable for central gateway | |
| CN108989111B (en) | Method for simulating communication between nodes | |
| CN116258113A (en) | Multi-protocol low-speed bus interface chip architecture | |
| Wiecha et al. | Architecture and design of a Bluetooth low energy controller | |
| CN111404697B (en) | Vehicle-mounted Ethernet simulation board card | |
| EP2135386B1 (en) | Hardware interface board for connecting an emulator to a network | |
| CN210402332U (en) | Arinc659 bus communication simulation system | |
| JP2021036425A (en) | Device with test function and method for test | |
| CN220401774U (en) | Communication detecting system based on vehicle-mounted gateway | |
| CN111865839A (en) | Communication method, device and equipment of electronic control unit and computer storage medium | |
| KR20170029951A (en) | Compliance test apparatus and method of communication node | |
| CN113938449B (en) | Control method of network security equipment and network security equipment | |
| Prasad et al. | Conformance Test of Automotive CAN BUS Transceiver: Empirical Research of Industry Case | |
| CN106921548A (en) | A kind of automatic coagulation analyzer communication system based on CAN | |
| CN216310776U (en) | Interface board card, user equipment and CPU test system | |
| CN117057286B (en) | SMBus module level verification system based on UVM and VIP | |
| CN113765827B (en) | Switch firmware protection system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210615 |