CN211743123U - Integrated circuit version control unit and control circuit - Google Patents
Integrated circuit version control unit and control circuit Download PDFInfo
- Publication number
- CN211743123U CN211743123U CN202020456465.9U CN202020456465U CN211743123U CN 211743123 U CN211743123 U CN 211743123U CN 202020456465 U CN202020456465 U CN 202020456465U CN 211743123 U CN211743123 U CN 211743123U
- Authority
- CN
- China
- Prior art keywords
- metal
- branch
- parallel
- via hole
- version control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses an integrated circuit version control unit and control circuit, the version control unit includes metal and via hole series branch, metal parallel branch and via hole parallel branch; the metal and via hole series branch, the metal parallel branch and the via hole parallel branch are connected in parallel; the metal and via hole series branch comprises a plurality of metal layers and a plurality of via holes which are sequentially connected in series, and the metal layers and the via holes are connected at intervals; cutting off positions are reserved for each metal layer and each through hole; the metal parallel branches comprise a plurality of metal branches connected in parallel, and each metal branch is provided with a notch; the via parallel branch comprises a plurality of via branches connected in parallel; each layer of via hole branch comprises two connected metal layers, and the two connected metal layers have an overlapping region; the overlapping area reserves the position for placing the through hole. The utility model provides an integrated circuit version control unit and control circuit can improve the convenience of integrated circuit version control information modification, improves work efficiency.
Description
Technical Field
The utility model belongs to the technical field of integrated circuit, a integrated circuit engineering modification method is related to, especially relate to an integrated circuit version control unit and control circuit.
Background
At present, the life cycle of an integrated circuit design mainly comprises design, manufacture and packaging test. Where the demarcation points for design and manufacturing are differentiated by the design company providing layout data to the foundry of the integrated circuit. After the data of the design company is obtained and confirmed, the foundry works usually start to manufacture the mask and the integrated circuit according to the layout data.
In the integrated circuit design flow, Engineering Change Order (ECO) refers to modifying a netlist generated by synthesis of a design tool by a manual method, and performing back-end layout, timing verification, physical verification again to generate manufacturing data which is finally provided to a foundry. The engineering modification can be implemented to correct a small range of chip design errors through a small cost and a short iteration period. Engineering modifications can generally be implemented in two phases:
(1) and (5) chip design stage. Implementing engineering modifications at this stage may save design iterations (ranging from days to months depending on design scale) of complete design synthesis, place and route, parasitic extraction, timing verification. The engineering modification freedom degree at this stage is large, and all layout resources can be modified.
(2) After the chip is manufactured. Engineering modification at this stage can save mask manufacturing cost. The mask is extremely high in precision and extremely expensive, and a set of complete chip manufacturing data usually needs tens of layers of masks (the number of the masks in a latest 7nm process is as high as hundreds of layers). If the purpose of modifying the design can be achieved by only modifying a plurality of layers of layouts (usually metal and via holes, which are collectively called routing resources), the cost can be greatly reduced. Engineering modification which is completed only by means of metal layer mask plate modification needs to reserve a spare device at the beginning of design, so that the spare device can be fused into the main circuit by modifying the metal layer during engineering modification.
Research and development personnel generally expect that the version information of different engineering change chips can be acquired in a certain way to carry out material management and software configuration optimization. These version information can be marked in several ways, but none of them have some problems.
(1) And (4) packaging the version. Corresponding text information can be printed on the surface of the chip for different versions of the chip which are modified in engineering in the packaging stage. But effective versioning cannot be implemented for unpackaged dies; in addition, some products with special requirements can be subjected to glue filling on the circuit board in consideration of water resistance, dust resistance, ageing resistance and the like during assembly, and the version of the chip cannot be judged through packaging after glue filling; in addition, the chips modified by different projects may have slight differences in configuration, and information marked on the package cannot be read by software, so that differential configuration cannot be performed on the chips of different project modification versions.
(2) eFulse or EPROM/Flash burning version information. In the chip testing stage, corresponding engineering revision information can be burned at a specific position in an eFuse or EPROM/Flash in the chip in the automatic testing process, and the corresponding engineering revision information can be judged by reading the content of the specific position. However, both efuses and Flash values can only be burned during automatic testing, and the version of the chip which is not burned cannot be judged. And the eFuse needs to increase a separate IP module, and the EPROM/Flash needs a special process or the required chip bare chip and Flash bare chip are sealed in the same package during packaging, so that the universality is poor.
(3) And additionally modifying the netlist information of the reserved version flag bits in the circuit besides the original engineering modification during the engineering modification, and then performing layout and routing by means of an EDA tool to generate a required design file. As previously mentioned, the placement and routing for engineering modifications by the tool depends on the spare devices that are reserved in advance. Spare devices are typically scattered around the chip, possibly far from the location of the required modification, requiring more routing resources to be modified. In addition, the trace resource for modifying the version flag and the trace resource for modifying the original project are not necessarily completely consistent. It is very likely to consume additional routing resources for modifying the version flag, which increases the cost of engineering modification.
The chinese patent "a method for reducing the number of modified layers during modification of integrated circuit engineering" (CN106709154A) "provides a solution for completing modification by modifying only a single-layer via. As shown in fig. 1, in the solution, a hard module unit is introduced during the design of an integrated circuit, a plurality of default value modification units are arranged in the hard module unit, and any bit of the output of each default value modification unit can be independently set to '0' or '1', so that the hard module unit can be called for the default value of any register or the parameter of an analog module, the wires of the default value modification units are all located on the same metal layer, and only one via layer or one metal layer needs to be modified during the ECO, which can greatly reduce the cost of re-platemaking, reduce the time for modifying a mask by a factory, and improve the efficiency of engineering modification.
FIG. 2 is a schematic diagram of the method provided by the present invention during engineering modification, wherein the metal wires connected to the pull-down unit and the metal wires connected to the pull-up unit are located on the metal layer 2, and the output high-level trace H [ n ], the output low-level trace L [ n ], the input trace I [ n ] and the output trace O [ n ] of the default modification unit are all located on the metal layer 3. This example illustrates the modification of O4 and O1, taking the modification of O4 as an example: the via connecting L4 to the metal line connected to the pull-down cell is disconnected at A1, and a via is added at A2 to connect I4 to the metal line connected to the pull-up cell. The modification to O1 is similar to O4. The embodiment illustrates that no matter how many groups of default value modification units need to be modified, the modification can be realized only by modifying the same via hole layer, so that the cost caused by the revision can be greatly reduced.
However, the utility model must modify the predetermined metal layer, such as the via hole between metal layer 2 and metal layer 3 in the above embodiment, when modifying the output value. If the trace resources to be changed by the predetermined engineering modification do not include the via hole from the metal layer 2 to the metal layer 3, the via hole from the metal layer 2 to the metal layer 3 needs to be additionally modified in order to change the output of the trace resources, which results in an increase in engineering modification cost.
In view of the foregoing, there is a need to design a new method for adjusting version information of an integrated circuit, so as to overcome at least some of the above-mentioned disadvantages of the existing method for adjusting version information of an integrated circuit.
SUMMERY OF THE UTILITY MODEL
The utility model provides an integrated circuit version control unit and control circuit can improve the convenience of integrated circuit version control information modification, improves work efficiency.
For solving the technical problem, according to the utility model discloses an aspect adopts following technical scheme:
an integrated circuit version control unit, the version control unit comprising: a metal and via series branch, a metal parallel branch and a via parallel branch;
the metal and via hole series branch, the metal parallel branch and the via hole parallel branch are connected in parallel, and the outputs of the branches are connected with each other to form the output of the version control unit;
the first end of the metal and via hole series branch is connected with the pull-down unit, and the first end of the metal parallel branch and the input of the via hole parallel branch are connected with the pull-up unit;
the metal and via hole series branch comprises a plurality of metal layers and a plurality of via holes which are sequentially connected in series, and the metal layers and the via holes are connected at intervals and output through the metal layers; the metal layer in the metal and via series branch is directly connected with the metal layer in the metal parallel branch; cutting off positions are reserved for each metal layer and each through hole;
the metal parallel branches comprise a plurality of metal branches connected in parallel, each metal branch is connected with the pull-up unit, and each metal branch is provided with a notch;
the via hole parallel branches comprise a plurality of via hole branches connected in parallel, and each via hole branch is respectively connected with the pull-up unit; each layer of via hole branch comprises two connected metal layers, and the two connected metal layers have an overlapping region; the position of placing the via hole is reserved in the overlapping area, and the metal overlapping part meets the physical design rule required after the via hole is placed.
As an embodiment of the present invention, the metal parallel branch includes n metal branches, and each metal branch includes a layer metal layer, and is marked as: a first metal layer, a second metal layer, …, an n-1 th metal layer, an nth metal layer; wherein n is more than or equal to 2;
the via parallel branches comprise n-1 via branches, and the ith via branch comprises an ith metal layer and an (i + 1) th metal layer; wherein i is an integer, i is more than or equal to 1 and less than or equal to n-1; an ith through hole is formed between the ith metal layer and the (i + 1) th metal layer.
In one embodiment of the present invention, n is 4.
According to another aspect of the utility model, adopt following technical scheme:
an integrated circuit version control circuit comprises at least one integrated circuit version control unit and an encoder; and each integrated circuit version control unit is respectively connected with the encoder.
The beneficial effects of the utility model reside in that: the utility model provides an integrated circuit version control unit and control circuit can improve the convenience of integrated circuit version control information modification, improves work efficiency.
Drawings
FIG. 1 is a diagram of a hard module unit according to an embodiment of the prior art.
FIG. 2 is a diagram illustrating a prior art implementation of metal only ECO using hard module units.
Fig. 3 is a schematic diagram of a version control unit according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a modification of the version control unit according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of an engineering revision control encoding according to an embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
For further understanding of the present invention, preferred embodiments of the present invention will be described below with reference to examples, but it should be understood that these descriptions are only for the purpose of further illustrating the features and advantages of the present invention, and are not intended to limit the claims of the present invention.
The description in this section is for exemplary embodiments only, and the present invention is not limited to the scope of the embodiments described. The same or similar prior art means and some technical features of the embodiments are mutually replaced and are also within the scope of the description and the protection of the invention.
The utility model discloses an integrated circuit version control unit, and FIG. 3 is a schematic diagram of the version control unit in an embodiment of the present invention; referring to fig. 3, in an embodiment of the present invention, the version control unit includes: a metal and via series branch 1, a metal parallel branch 3, and a via parallel branch 5. The metal and via hole series branch 1, the metal parallel branch 3 and the via hole parallel branch 5 are connected in parallel, and the outputs of the branches are connected with each other to form the output of the version control unit. The first end of the metal and via hole series branch 1 is connected with a pull-down unit 7, and the first end of the metal parallel branch 3 and the input of the via hole parallel branch 5 are connected with a pull-up unit 9.
The metal and via hole series branch 1 comprises a plurality of metals and a plurality of via holes which are sequentially connected in series, and the metals and the via holes are connected at intervals and finally output through metal connection; the metal in the metal and via hole series branch 1 is directly connected with the metal in the metal parallel branch; and a cutting position is reserved for each layer of metal and each through hole. The metal parallel branch 3 comprises a plurality of metal branches 30 connected in parallel, each metal branch 30 is connected with the pull-up unit 9, and each metal branch 30 is provided with a notch. The via parallel branch 5 comprises a plurality of via branches 50 connected in parallel, and each via branch 50 is connected with the pull-up unit 9; each via branch 50 comprises two connected metal layers having an overlap region; the position of placing the via hole is reserved in the overlapping area, and the metal overlapping part meets the physical design rule required after the via hole is placed.
In an embodiment of the present invention, the metal parallel branch includes n metal branches, and each metal branch includes a layer of metal, and is marked as: a first metal, a second metal, …, an n-1 metal, an nth metal; wherein n is more than or equal to 2. The via parallel branches comprise n-1 via branches, and the ith via branch comprises ith metal and (i + 1) th metal; wherein i is an integer, i is more than or equal to 1 and less than or equal to n-1; an ith through hole is formed between the ith metal and the (i + 1) th metal. In one embodiment, n is 4, but n may also be 5, 6, 7, 8, 9, 12, 15, and so on.
The utility model discloses only need can realize the version change through modifying arbitrary one deck metal or via hole. In addition, the version control information modification scheme can completely utilize routing resources including metal and via holes required by the modification of the original engineering, and no extra cost is needed. The scheme includes an implementation of an engineering modified version control unit (fig. 3) and a version control scheme implemented with the unit (fig. 5).
Fig. 3 is a plan view showing an implementation of an engineering modified version control unit in a four-level metal three-level via interconnect process. Fig. 3 is divided into three major parts from bottom to top: the metal and via hole series branch 1, the metal parallel branch 3 and the via hole parallel branch 5 form a parallel structure, and the outputs of the branches are connected with each other to form the output of the engineering revision version control unit.
The metal and via series branch includes a first metal layer M1, a first via V1 (for connecting the first metal layer M1 and the second metal layer M2), a second metal layer M2, a second via V2 (for connecting the second metal layer M2 and the third metal layer M3), … … connected in series with the pull-down unit 7 to the fourth metal layer M4 and connected to the output. Each layer of metal and via hole is reserved with a cutting position, as shown in fig. 3, a first reserved cutting position S _ M1, a second reserved cutting position S _ V1, a third reserved cutting position S _ M2, a fourth reserved cutting position S _ V2, a fifth reserved cutting position S _ M3, a sixth reserved cutting position S _ V3, and a seventh reserved cutting position S _ M4 in sequence.
The metal parallel branch comprises four parallel branches connected with the pull-up unit 2, namely a first parallel branch (provided with a first metal layer M1), a second parallel branch (provided with a second metal layer M2), a third parallel branch (provided with a third metal layer M3) and a fourth parallel branch (provided with a fourth metal layer M4). The inputs of the four branches are connected to the pull-up unit 9, and the first metal layer M1, the second metal layer M2, the third metal layer M3, and the fourth metal layer M4 are respectively provided with a first gap P _ M1, a second gap P _ M2, a third gap P _ M3, and a fourth gap P _ M4 (as shown in fig. 3). The four metal layers may be connected to the output through a fourth metal layer M4.
The via parallel branch comprises three parallel branches connected with the pull-up unit 9, namely a fifth parallel branch, a sixth parallel branch and a seventh parallel branch. The fifth parallel branch comprises a first metal layer M1 and a second metal layer M2, and the first metal layer M1 and the second metal layer M2 are provided with a first overlapping area P _ V1; the sixth parallel branch comprises a second metal layer M2 and a third metal layer M3, and a second overlapping area P _ V2 is arranged on the second metal layer M2 and the third metal layer M3; the third parallel branch comprises a third metal layer M3 and a fourth metal layer M4, and the third metal layer M3 and the fourth metal layer M4 are provided with a third overlapping region P _ V3. The first overlapping region P _ V1, the second overlapping region P _ V2, and the third overlapping region P _ V3 reserve positions for placing a first via V1, a second via V2, and a third via V3, respectively, and the metal overlapping portion meets a physical design rule required after placing the vias.
As shown in fig. 4, before the engineering modification, the version control unit is in the initial state, i.e., the output is connected to the pull-down unit through the serial branch, and the metal parallel branch and the via parallel branch are disconnected from the pull-up unit, so the output of the version control unit is '0'. If engineering modifications occur and assuming that the original engineering modifications only modify via V1, then S _ V1 in the series branch may be removed and the P _ V1 position in the via parallel branch added to V1. This allows the output that would otherwise be connected to the pull-down unit through the series branch to be disconnected, and the branch in which P _ V1 in the via parallel branch that would otherwise be disconnected from the pull-up unit is connected to the output. The output is therefore '1'.
Similarly, changing the originally '0' output to '1' may be accomplished by disconnecting any of the S _ M1, S _ V1, S _ M2, S _ V2, S _ M3, S _ V3, S _ M4 points in the series branch, and connecting the corresponding P _ M1, P _ V1, P _ M2, P _ V2, P _ M3, P _ V3, P _ M4 points in the parallel branch.
The utility model discloses well engineering revises version control unit's core lies in containing the topological structure that the series connection branch and the parallelly connected branch of accessible arbitrary layer metal or via hole connection constitute through arbitrary layer metal or via hole disconnection. Any shape or position change that satisfies the topological relationship is considered to be the subject of the present invention. Including but not limited to adjusting the order of metal cascading in the series branches, stacking multiple layers of metal together in the parallel branches, merging via parallel branches and metal parallel branches, etc.
The utility model discloses an utilize above-mentioned integrated circuit version control unit's modification integrated circuit version control information method, the method includes: and arranging a via hole at the set via hole position according to the control version information, and cutting off at the set cut-off position of the metal and via hole serial branch. In one embodiment, the method comprises: and receiving the data input by each version control unit through an encoder, and outputting version information after encoding.
The utility model discloses still a kind of integrated circuit version control circuit, the said integrated circuit version control circuit includes at least one above-mentioned integrated circuit version control unit and an encoder; and each integrated circuit version control unit is respectively connected with the encoder.
It should be noted that the output of the engineering revision control unit shown in fig. 3 can only implement one modification from the initial '0' to '1'. Once modified to '1', it cannot be modified to '0' again. In order to mark multiple engineering modifications, multiple version control units and peripheral auxiliary circuits are needed to be realized in a matching manner. Fig. 5 shows the implementation of a complete engineering modified board control circuit consisting of 16 version control units and thermometer code to binary code encoding circuits, using a 4-bit version output as an example. The coding circuit consists of an adder, adds the outputs of the 16 engineering revision version control units, and outputs corresponding two-level system codes. All 16 version control unit outputs are '0' in the initial state, the encoder input is 16 '0000 _0000_0000_0000, and thus the encoder output is 4' b 000; when the 1 st project is modified, the output of the version control unit [0] is changed into ' 1 ', and the output of the encoder is 4 ' b 001; the version control unit [1] output is changed to '1' at the 2 nd engineering modification, the encoder input is 16 'b 0000_0000_0000_0011 and the encoder output is 4' b 010. By analogy, in an embodiment of the present invention, a total of 16 different versions (initial version and 15 engineering revision versions) can be marked using the circuit shown in fig. 5.
To sum up, the utility model provides an integrated circuit version control unit and control circuit can improve the convenience of integrated circuit version control information modification, improves work efficiency.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The description and applications of the present invention are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the present invention.
Claims (4)
1. An integrated circuit version control unit, characterized in that the version control unit comprises: a metal and via series branch, a metal parallel branch and a via parallel branch;
the metal and via hole series branch, the metal parallel branch and the via hole parallel branch are connected in parallel, and the outputs of the branches are connected with each other to form the output of the version control unit;
the first end of the metal and via hole series branch is connected with the pull-down unit, and the first end of the metal parallel branch and the input of the via hole parallel branch are connected with the pull-up unit;
the metal and via hole series branch comprises a plurality of metal layers and a plurality of via holes which are sequentially connected in series, and the metal layers and the via holes are connected at intervals and output through the metal layers; the metal layer in the metal and via series branch is directly connected with the metal layer in the metal parallel branch; cutting off positions are reserved for each metal layer and each through hole;
the metal parallel branches comprise a plurality of metal branches connected in parallel, each metal branch is connected with the pull-up unit, and each metal branch is provided with a notch;
the via hole parallel branches comprise a plurality of via hole branches connected in parallel, and each via hole branch is respectively connected with the pull-up unit; each layer of via hole branch comprises two connected metal layers, and the two connected metal layers have an overlapping region; the position of placing the via hole is reserved in the overlapping area, and the metal overlapping part meets the physical design rule required after the via hole is placed.
2. The integrated circuit version control unit of claim 1, wherein:
the metal parallel branches include n metal branches, each metal branch includes a metal layer, which is respectively marked as: a first metal layer, a second metal layer, …, an n-1 th metal layer, an nth metal layer; wherein n is more than or equal to 2;
the via parallel branches comprise n-1 via branches, and the ith via branch comprises an ith metal layer and an (i + 1) th metal layer; wherein i is an integer, i is more than or equal to 1 and less than or equal to n-1; an ith through hole is formed between the ith metal layer and the (i + 1) th metal layer.
3. The integrated circuit version control unit of claim 2, wherein:
n＝4。
4. an integrated circuit version control circuit, comprising: the integrated circuit version control circuit comprises at least one integrated circuit version control unit of any one of claims 1 to 3 and an encoder; and each integrated circuit version control unit is respectively connected with the encoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020456465.9U CN211743123U (en) | 2020-04-01 | 2020-04-01 | Integrated circuit version control unit and control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202020456465.9U CN211743123U (en) | 2020-04-01 | 2020-04-01 | Integrated circuit version control unit and control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN211743123U true CN211743123U (en) | 2020-10-23 |
Family
ID=72853209
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202020456465.9U Active CN211743123U (en) | 2020-04-01 | 2020-04-01 | Integrated circuit version control unit and control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN211743123U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114492256A (en) * | 2022-04-15 | 2022-05-13 | 南京沁恒微电子股份有限公司 | Integrated circuit digital back end ECO method, system and computer storage medium |
-
2020
- 2020-04-01 CN CN202020456465.9U patent/CN211743123U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114492256A (en) * | 2022-04-15 | 2022-05-13 | 南京沁恒微电子股份有限公司 | Integrated circuit digital back end ECO method, system and computer storage medium |
| CN114492256B (en) * | 2022-04-15 | 2022-07-08 | 南京沁恒微电子股份有限公司 | Integrated circuit digital back-end ECO method, system and computer storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1848122B (en) | Method for integrally checking chip and package substrate layouts for errors and system thereof | |
| JP3891599B2 (en) | Device for automatic insertion of standard cells into an integrated circuit layout. | |
| US6574786B1 (en) | Gate array cell generator using cadence relative object design | |
| CN101587508B (en) | Method, system and computer program product for determining routing of data paths in interconnect circuitry | |
| CN100342381C (en) | Integrated circuit design conforming method and component element, transaction method and product applied thereby | |
| US20050280438A1 (en) | Switch methodology for mask-programmable logic devices | |
| US20040080334A1 (en) | Spare cell architecture for fixing design errors in manufactured integrated circuits | |
| Case et al. | Solid logic design automation | |
| CN211743123U (en) | Integrated circuit version control unit and control circuit | |
| US11670610B2 (en) | Method and system for verifying integrated circuit stack having photonic device | |
| US6629307B2 (en) | Method for ensuring correct pin assignments between system board connections using common mapping files | |
| CN115329713B (en) | Layout module, method and device for generating wiring file and wiring | |
| CN114925647A (en) | Gate-level netlist migration method, machine-readable medium and integrated circuit design system | |
| CN111463170A (en) | Integrated circuit version control unit and control circuit and modification method | |
| US6584606B1 (en) | Fast method of I/O circuit placement and electrical rule checking | |
| CN100382087C (en) | Semiconductor device, semiconductor device wiring method and manufacturing method thereof | |
| US7480888B1 (en) | Design structure for facilitating engineering changes in integrated circuits | |
| CN105224702A (en) | A kind of layout design method and layout design system | |
| US8671374B2 (en) | Information processing apparatus | |
| CN104750887A (en) | Method for generating parameterized unit in modularized mode | |
| US10216963B2 (en) | Method to protect an IC layout | |
| CN102156789B (en) | System and method for automatically generating constraint file of field programmable gate array (FPGA) | |
| CN104424379A (en) | Verifying partial good voltage island structures | |
| KR100272887B1 (en) | Semiconductor device layout method capable of arranging functional cells with data signal lines and control signal lines having a proper length and configuration | |
| CN113515913B (en) | Magnetic process design method of STT-MRAM related circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |