CN112131150A - Multi-chip external memory control method and device - Google Patents
Multi-chip external memory control method and device Download PDFInfo
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- CN112131150A CN112131150A CN202010967597.2A CN202010967597A CN112131150A CN 112131150 A CN112131150 A CN 112131150A CN 202010967597 A CN202010967597 A CN 202010967597A CN 112131150 A CN112131150 A CN 112131150A
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
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Abstract
The invention discloses a method and a device for controlling a plurality of external memories, which are suitable for FPGA chips of Xilinx company and comprise the following steps: the user interface modules are composed of a command FIFO, a write data FIFO and a read data FIFO, and the control of a user program on the off-chip memories can be simplified into the control of the FIFOs in the user interface modules; the interface multiplexing module completes polling reading and writing and bit width comparison of a plurality of user interface modules; and the time sequence conversion module is used for completing the conversion between the FIFO time sequence and the MIG time sequence (an IP core used for controlling an off-chip memory in the FPGA of Xilinx company). The invention can avoid the complex interface time sequence of the MIG IP core directly operated by the user to a certain extent, and can complete the control of a plurality of off-chip memories only by operating the FIFO time sequence.
Description
Technical Field
The invention belongs to the field of electronic engineering and computer science, and particularly relates to a multi-chip external memory control method and device.
Background
An MIG (memory Interface Generator) IP core is provided by an FPGA manufacturer Xilinx for FPGA developers and is used for realizing access to off-chip memories, such as DDR2, DDR3 and the like. The MIG IP core itself provides two forms of user interface: native interface and AXI interface. The AXI interface has a form meeting international standards and complete functions, but because the AXI interface has more signals and more complex time sequence, the design progress is slowed down to a great extent in a design mode of manual coding; the Native interface is developed by Xilinx, and has the advantages of relatively less interface signals and relatively simple time sequence, but cannot adapt to the data bit width of user logic, cannot perform complete data Burst transmission operation, and does not have the control capability of a plurality of user programs on a plurality of off-chip memories. That is, when the user interface function of the IP core is complete, the interface form is complex; when the form of the user interface is relatively simple, the interface function is not complete.
Disclosure of Invention
The invention provides a method and a device for controlling a plurality of off-chip memories, aiming at solving the technical problems, and the method and the device comprise a user interface module, an interface multiplexing module and a time sequence conversion module, can avoid the situation that a user directly operates the MIG IP core complex interface time sequence to a certain extent, and can complete the control of the plurality of off-chip memories only by operating FIFO time sequence.
The technical problem to be solved by the invention is realized by adopting the following technical scheme: an apparatus for controlling an off-chip memory, comprising:
(1) the user interface module comprises a plurality of user interfaces, each user interface comprises a command FIFO, a write data FIFO and a read data FIFO, and the control of a user on a plurality of off-chip memories is simplified into the FIFO control in the user interfaces, and the user interface module specifically comprises the following steps:
each user interface of the off-chip memory to be controlled comprises three independent FIFOs, namely the command FIFO, the write data FIFO and the read data FIFO;
the command FIFO is used for storing a plurality of read-write commands of the user interface in sequence, including read commands, write commands, read-write byte length, bit width and target off-chip memory addresses;
the write data FIFO is used for storing the effective data which are to be written into the target off-chip memory by the user interface in sequence;
the read data FIFO is used for storing the effective data read by the user interface from the target off-chip memory in sequence;
(2) the interface multiplexing module is used for completing polling reading and writing, bit width comparison and sequential storage of a plurality of user interfaces, and specifically comprises:
a polling read-write module for completing polling read-write to a plurality of user interfaces, namely after completing the read-write to a certain user interface, an interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
a bit width comparison module for reading a bit width field in a command FIFO in the user interface, comparing a data bit width in a write data FIFO in the user interface with a bit width of a MIG IP core in the FPGA, namely supplementing 0 to the data in the write data FIFO when the data bit width in the write data FIFO in the user interface is less than the bit width of the MIG IP core;
the interface multiplexing module directly stores the data returned by the MIG IP core into the corresponding user interface read FIFO in sequence without bit width adjustment;
(3) the time sequence conversion module completes the conversion between the FIFO time sequence and the MIG IP core time sequence, and specifically comprises:
the device comprises a read time sequence conversion state machine module, a read time sequence conversion state machine module and a control interface module, wherein the read time sequence conversion state machine module is used for completing the conversion between an FIFO read time sequence and an MIG IP core read time sequence and realizing the data reading of an off-chip memory of a user interface based on the FIFO time sequence;
and the writing time sequence conversion state machine module is used for completing the conversion between the FIFO writing time sequence and the MIG IP core writing time sequence and realizing the data writing of the off-chip memory of the user interface based on the FIFO time sequence.
Furthermore, the multi-chip external memory control device is suitable for FPGA chips of Xilinx company.
According to another aspect of the present invention, there is provided a multi-chip external memory control method, including:
step one, for writing data to a target off-chip memory:
the method comprises the following steps that firstly, a user program respectively stores a write command and data to be written into a command FIFO and a write data FIFO in a user interface module, wherein the write command comprises a write command, a write byte length, a bit width and a target off-chip memory address;
the polling read-write module in the interface multiplexing module finishes reading the user interface, and the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
thirdly, the bit width comparison module in the interface multiplexing module reads a bit width field in a command FIFO in the user interface, compares the bit width of data in a write data FIFO in the user interface with the bit width of a MIG IP core in the FPGA according to the bit width of the MIG IP core in the FPGA, namely, when the bit width of the data in the write data FIFO in the user interface is smaller than the bit width of the MIG IP core, the data in the write data FIFO is compensated with 0 in a high position;
a write time sequence conversion state machine module in the time sequence conversion module completes the conversion between the FIFO write time sequence and the MIG IP core write time sequence, and realizes the data write-in of the off-chip memory of the user interface based on the FIFO time sequence;
step two, for reading data from the target off-chip memory:
firstly, a user program stores a read command into a command FIFO in a user interface module, wherein the read command comprises a read command, a read byte length, a bit width and a target off-chip memory address;
the polling read-write module in the interface multiplexing module finishes reading the user interface, and the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
the data returned by the MIG IP core is directly and sequentially stored in the corresponding user interface read FIFO by the sequential storage module in the interface multiplexing module without bit width adjustment;
and fourthly, a reading time sequence conversion state machine module in the time sequence conversion module completes the conversion between the FIFO reading time sequence and the MIG IP core reading time sequence, and the data reading of the off-chip memory of the user interface based on the FIFO time sequence is realized.
Furthermore, the multi-chip external memory control method is suitable for FPGA chips of Xilinx company.
Has the advantages that:
compared with the prior art, the invention has the advantages that: the method can solve the contradiction between the simple form of the MIG IP core user interface and the completeness of the interface function to a certain extent, avoid the complicated interface time sequence of the MIG IP core directly operated by a user, and can complete the control of a plurality of off-chip memories only by operating the FIFO time sequence.
Drawings
FIG. 1 is a block diagram of the apparatus of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments, and all other embodiments obtained by a person skilled in the art based on the embodiments of the present invention belong to the protection scope of the present invention without creative efforts.
The invention relates to a control method of a multi-chip external memory, which can solve the contradiction between the simple form of a MIG IP core user interface and the completeness of interface functions to a certain extent, avoid the complicated interface time sequence of the MIG IP core directly operated by a user and complete the control of the multi-chip external memory only by operating FIFO time sequence.
According to an embodiment of the present invention, as shown in fig. 1, a block diagram of a control apparatus for a multi-chip external memory is provided, which includes a user interface module, an interface multiplexing module, and a timing conversion module, and specifically includes:
(1) the user interface module comprises a plurality of user interfaces, each user interface consists of a command FIFO, a write data FIFO and a read data FIFO, and the control of a user program on a plurality of off-chip memories can be simplified into the FIFO control in the user interfaces, and the specific implementation is as follows:
designing three independent FIFOs (namely a command FIFO, a write data FIFO and a read data FIFO) aiming at a user interface (a plurality of user interfaces can be operated in parallel in one FPGA) of each off-chip memory to be controlled;
the command FIFO sequentially stores a plurality of read-write commands of the user interface, including read commands, write commands, read-write byte length, bit width and target off-chip memory addresses;
writing data FIFO sequentially storing the effective data which are to be written into the target off-chip memory by the user interface;
the reading data FIFO stores the effective data read by the user interface from the target off-chip memory in sequence;
(2) designing an interface multiplexing module which completes polling reading and writing and bit width comparison of a plurality of user interfaces, wherein a bit width field in the user interface module is less than or equal to the bit width of an MIG IP core, and the specific implementation is as follows:
firstly, the interface multiplexing module completes polling read-write to a plurality of user interfaces, namely after completing the read-write to a certain user interface, the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
secondly, the interface multiplexing module reads a bit width field in a command FIFO in the user interface, compares the bit width of data in a write data FIFO in the user interface with the bit width of a MIG IP core in the FPGA according to the bit width of the MIG IP core in the FPGA, namely, when the bit width of the data in the write data FIFO in the user interface is smaller than the bit width of the MIG IP core, the data in the write data FIFO is compensated with 0 in a high position;
the interface multiplexing module directly stores the data returned by the MIG IP core into the corresponding user interface read FIFO in sequence without bit width adjustment;
(3) designing a time sequence conversion module, wherein the module completes the conversion between the FIFO time sequence and the MIG time sequence (an IP core used for controlling an off-chip memory in FPGA of Xilinx company), and the specific implementation is as follows:
firstly, a programming state machine completes the conversion between an FIFO (first in first out) reading time sequence and an MIG (Metal inert gas) reading time sequence, and realizes the data reading of an off-chip memory of a user interface based on the FIFO time sequence;
and secondly, the writing state machine completes the conversion between the FIFO writing time sequence and the MIG writing time sequence, and realizes the data writing of the off-chip memory of the user interface based on the FIFO time sequence.
According to another embodiment of the present invention, a method for controlling a multi-chip external memory is further provided, including the steps of:
step one, for writing data to a target off-chip memory:
the method comprises the following steps that firstly, a user program respectively stores a write command and data to be written into a command FIFO and a write data FIFO in a user interface module, wherein the write command comprises a write command, a write byte length, a bit width and a target off-chip memory address;
the polling read-write module in the interface multiplexing module finishes reading the user interface, and the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
thirdly, the bit width comparison module in the interface multiplexing module reads a bit width field in a command FIFO in the user interface, compares the bit width of data in a write data FIFO in the user interface with the bit width of a MIG IP core in the FPGA according to the bit width of the MIG IP core in the FPGA, namely, when the bit width of the data in the write data FIFO in the user interface is smaller than the bit width of the MIG IP core, the data in the write data FIFO is compensated with 0 in a high position;
a write time sequence conversion state machine module in the time sequence conversion module completes the conversion between the FIFO write time sequence and the MIG IP core write time sequence, and realizes the data write-in of the off-chip memory of the user interface based on the FIFO time sequence;
step two, for reading data from the target off-chip memory:
firstly, a user program stores a read command into a command FIFO in a user interface module, wherein the read command comprises a read command, a read byte length, a bit width and a target off-chip memory address;
the polling read-write module in the interface multiplexing module finishes reading the user interface, and the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
the data returned by the MIG IP core is directly and sequentially stored in the corresponding user interface read FIFO by the sequential storage module in the interface multiplexing module without bit width adjustment;
and fourthly, a reading time sequence conversion state machine module in the time sequence conversion module completes the conversion between the FIFO reading time sequence and the MIG IP core reading time sequence, and the data reading of the off-chip memory of the user interface based on the FIFO time sequence is realized.
In summary, the present invention discloses a method and an apparatus for controlling a plurality of external storage devices, which includes designing a user interface module, an interface multiplexing module and a timing conversion module, and can solve the contradiction between the simple user interface form and the completeness of interface function of a MIG IP core to a certain extent, and avoid the user from directly operating the complex interface timing of the MIG IP core, and can complete the control of the plurality of external storage devices only by operating a FIFO timing.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (4)
1. A multi-chip external memory control apparatus, comprising:
(1) the user interface module comprises a plurality of user interfaces, each user interface comprises a command FIFO, a write data FIFO and a read data FIFO, and the control of a user on a plurality of off-chip memories is simplified into the FIFO control in the user interfaces, and the user interface module specifically comprises the following steps:
each user interface of the off-chip memory to be controlled comprises three independent FIFOs, namely the command FIFO, the write data FIFO and the read data FIFO;
the command FIFO is used for storing a plurality of read-write commands of the user interface in sequence, including read commands, write commands, read-write byte length, bit width and target off-chip memory addresses;
the write data FIFO is used for storing the effective data which are to be written into the target off-chip memory by the user interface in sequence;
the read data FIFO is used for storing the effective data read by the user interface from the target off-chip memory in sequence;
(2) the interface multiplexing module is used for completing polling reading and writing, bit width comparison and sequential storage of a plurality of user interfaces, and specifically comprises:
a polling read-write module for completing polling read-write to a plurality of user interfaces, namely after completing the read-write to a certain user interface, an interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
a bit width comparison module for reading a bit width field in a command FIFO in the user interface, comparing a data bit width in a write data FIFO in the user interface with a bit width of a MIG IP core in the FPGA, namely supplementing 0 to the data in the write data FIFO when the data bit width in the write data FIFO in the user interface is less than the bit width of the MIG IP core;
the interface multiplexing module directly stores the data returned by the MIG IP core into the corresponding user interface read FIFO in sequence without bit width adjustment;
(3) the time sequence conversion module completes the conversion between the FIFO time sequence and the MIG IP core time sequence, and specifically comprises:
the device comprises a read time sequence conversion state machine module, a read time sequence conversion state machine module and a control interface module, wherein the read time sequence conversion state machine module is used for completing the conversion between an FIFO read time sequence and an MIG IP core read time sequence and realizing the data reading of an off-chip memory of a user interface based on the FIFO time sequence;
and the writing time sequence conversion state machine module is used for completing the conversion between the FIFO writing time sequence and the MIG IP core writing time sequence and realizing the data writing of the off-chip memory of the user interface based on the FIFO time sequence.
2. The multi-chip off-chip memory control device of claim 1, adapted for use with Xilinx FPGA chips.
3. A multi-chip external memory control method is characterized by comprising the following steps:
step one, for writing data to a target off-chip memory:
the method comprises the following steps that firstly, a user program respectively stores a write command and data to be written into a command FIFO and a write data FIFO in a user interface module, wherein the write command comprises a write command, a write byte length, a bit width and a target off-chip memory address;
the polling read-write module in the interface multiplexing module finishes reading the user interface, and the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
thirdly, the bit width comparison module in the interface multiplexing module reads a bit width field in a command FIFO in the user interface, compares the bit width of data in a write data FIFO in the user interface with the bit width of a MIG IP core in the FPGA according to the bit width of the MIG IP core in the FPGA, namely, when the bit width of the data in the write data FIFO in the user interface is smaller than the bit width of the MIG IP core, the data in the write data FIFO is compensated with 0 in a high position;
a write time sequence conversion state machine module in the time sequence conversion module completes the conversion between the FIFO write time sequence and the MIG IP core write time sequence, and realizes the data write-in of the off-chip memory of the user interface based on the FIFO time sequence;
step two, for reading data from the target off-chip memory:
firstly, a user program stores a read command into a command FIFO in a user interface module, wherein the read command comprises a read command, a read byte length, a bit width and a target off-chip memory address;
the polling read-write module in the interface multiplexing module finishes reading the user interface, and the interface multiplexing module points to the next user interface no matter whether the user interface has unprocessed tasks or not;
the data returned by the MIG IP core is directly and sequentially stored in the corresponding user interface read FIFO by the sequential storage module in the interface multiplexing module without bit width adjustment;
and fourthly, a reading time sequence conversion state machine module in the time sequence conversion module completes the conversion between the FIFO reading time sequence and the MIG IP core reading time sequence, and the data reading of the off-chip memory of the user interface based on the FIFO time sequence is realized.
4. The method as claimed in claim 3, wherein the device is suitable for Xilinx FPGA chip.
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