CN108563590A - OTP controller based on piece FLASH memory and control method - Google Patents
OTP controller based on piece FLASH memory and control method Download PDFInfo
- Publication number
- CN108563590A CN108563590A CN201810684179.5A CN201810684179A CN108563590A CN 108563590 A CN108563590 A CN 108563590A CN 201810684179 A CN201810684179 A CN 201810684179A CN 108563590 A CN108563590 A CN 108563590A
- Authority
- CN
- China
- Prior art keywords
- flash memory
- data
- read
- protected
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000004891 communication Methods 0.000 claims abstract description 46
- 238000006243 chemical reaction Methods 0.000 claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims abstract description 5
- 230000009466 transformation Effects 0.000 claims description 6
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000004590 computer program Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 241001269238 Data Species 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 239000002699 waste material Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000006399 behavior Effects 0.000 description 2
- 238000009933 burial Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The present invention provides a kind of OTP controller and control method based on piece FLASH memory.The OTP controller includes：Communication bus module, processor are used to carry out reading and writing data on piece FLASH memory and OTP controller by the communication bus module；Bus protocol conversion module is communicated with the communication bus module, and the bus protocol of the communication bus module is converted to the read-write bus protocol of on piece FLASH memory；Read-write state control module is communicated with the bus protocol conversion module, the read-write state for controlling the on piece FLASH memory；And OTP interfaces, it is communicated with the bus protocol conversion module and the on piece FLASH memory, is used for transmission of the OTP data between OTP controller and the storage unit of on piece FLASH memory.The OTP controller of the present invention can carry out FLASH memory the reading and writing data of one time programming, and OTP data can be protected not to be written over.
Description
Technical field
The present invention relates to field of semiconductor devices, more particularly to a kind of OTP controller based on piece FLASH memory and
Control method.
Background technology
Often strict protection is done on piece portion of program code and/or data in microcontroller and system on chip, only
Authorized user could read these code and/or datas by ad hoc fashion, while these code and/or datas are once
After being written into, any user cannot change or delete these code and/or datas.If these critical codes and/
Or data are read by the user of unauthorized, or are modified/are deleted, it will seriously affect the performance of whole system with it is reliable
Property.
In the microcontroller and SOC Design of early stage, these need protected code and/or data to be cured
In on piece read-only memory (Read-Only-Memory, ROM).But under the content in ROM is fixed in chip manufacturing
Come, different users can not be directed to a chip or applies and store different code and/or datas in ROM.To improve spirit
Activity, at present mainstay by based on anti-fuse technology or Floating-gate Technology OTP (One Time Programmable, disposably
It is programmable) in eprom memory insertion chip, content can be voluntarily written after chip manufacture by user, simultaneously because OTP
EPROM can be only written into once, therefore content can not be modified/delete, to realize data protection.
Embedded Flash Memory is that one kind is widely used on microcontroller and System on Chip/SoC for storing program generation
The non-volatile memory device of code and/or data.Compared with OTP EPROM, Embedded Flash Memory has storage size big,
The advantages of programming can be repeated several times, facilitate test.Therefore, it designs now with more and more chips and is deposited using embedded FLASH
Reservoir replaces OTP EPROM.
Since Embedded Flash Memory is repeatable erasable, critical data therein to be protected not to be written over or not
Authorized user reads, it is necessary to control reading, the deletion to Embedded Flash Memory by other hardware of on piece or software
And programming operation.Feature its internal storage unit of Embedded Flash Memory is organized by sector, delete operation
Smallest object is also a sector, and the corresponding software for controlling Embedded Flash Memory operation or hardware are also fanned for all also one
Area is minimum control object.
A sector or multiple addresses can only be protected to connect substantially the protection circuit of data on piece FLASH memory at present
Data in continuous sector are less than a sector if you need to data to be protected or data address are discontinuous, then protect data place
Other storage units of sector also can not be taken as common storage unit arbitrarily to be read and write by user, result in waste of resources, and increase
Product cost.
Being disclosed in the information of the background technology part, it is only intended to increase understanding of the overall background of the invention, without answering
It has been the prior art well known to persons skilled in the art when being considered as recognizing or imply that the information is constituted in any form.
Invention content
The purpose of the present invention is to provide a kind of OTP controllers based on piece FLASH memory, can be to FLASH
Memory carries out the reading and writing data of one time programming.
Another object of the present invention is to provide a kind of OTP controllers based on piece FLASH memory, can protect
OTP data are not written over.
To achieve the above object, the present invention provides a kind of OTP controllers based on piece FLASH memory, to described
The read-write operation of on piece FLASH memory is controlled.The OTP controller includes：Communication bus module, processor are logical by this
Believe that bus module is used to carry out reading and writing data on piece FLASH memory and OTP controller；Bus protocol conversion module, with
The communication bus module is communicated, and the bus protocol of the communication bus module is converted to the reading of on piece FLASH memory
Write bus agreement；Read-write state control module is communicated with the bus protocol conversion module, for controlling the on piece
The read-write state of FLASH memory；And OTP interfaces, it is deposited with the bus protocol conversion module and the on piece FLASH
Reservoir is communicated, for OTP data between the OTP controller and the storage unit of the on piece FLASH memory
Transmission.
In a preferred embodiment, the OTP controller further includes：Cache module is deposited with the on piece FLASH
Reservoir is into row data communication, the OTP data for caching FLASH memory.
In a preferred embodiment, the capacity of the cache module is equal to the single of the on piece FLASH memory
The capacity of data sector.
In a preferred embodiment, the bus type of the communication bus module is AXI or AHB types.
In a preferred embodiment, read-write state control module deposits the FLASH from the communication bus module
Reservoir interior access address is made comparisons with the predefined need one or more addresses FLASH to be protected, with confirming inter access
Whether location is protected, and when the inter access address is not to be protected address, then the inter access address is directly output to described
The address interface of FLASH memory, when the inter access address is then to the inter access to do predefined change by protection address
In the address interface for being output to FLASH memory after changing.
In a preferred embodiment, one to be protected to the need of predefined address of the read-write state control module
Or the state recording of protected data is read in multiple addresses FLASH, when protected inter access address is never programmed, then
Corresponding FLASH erasing instructions and programming instruction are generated, and the data from communication bus module are sent to FLASH memory
Data-interface；When the protected programmed mistake in inter access address, then programming operation is skipped.
In a preferred embodiment, before carrying out data erasing or programming operation, the read-write state control module
It is checked according to predefined rule in the sectors FLASH to be operated and whether contains protected data, as there is protected number in sector
According to, then first the protected data of the sector is read and is cached in the cache module, then execute the sector erasing behaviour
Make, then the protected data of caching and data to be written from the communication bus module are sequentially written in the sector
It is interior.
Another aspect provides a kind of on piece FLASH memory with OTP controller, the on pieces
FLASH memory can carry out the read-write operation of OTP data.The on piece FLASH memory includes：FLASH storage units and
Above-mentioned OTP controller.The OTP controller includes：Communication bus module, processor are used for by the communication bus module
Reading and writing data is carried out on piece FLASH memory and OTP controller；Bus protocol conversion module, with the communication bus mould
Block is communicated, and the bus protocol of the communication bus module is converted to the read-write bus protocol of on piece FLASH memory；Read-write
Status control module is communicated with the bus protocol conversion module, for controlling the on piece FLASH storage units
Read-write state；It with OTP interfaces, is communicated, is used with the bus protocol conversion module and the on piece FLASH memory
In transmission of the OTP data between the OTP controller and the storage unit of the on piece FLASH memory.
In a preferred embodiment, the capacity of the cache module is equal to the single number of the on piece FLASH memory
According to the capacity of sector.The bus type of the communication bus module is AXI or AHB types.
Another aspect of the invention provides a kind of read/writing control method of the OTP data on piece FLASH memory, packet
Include following steps：OTP data inputs are carried out on piece FLASH memory by communication bus module；By the communication bus mould
The bus protocol of block is converted to the read-write bus protocol of on piece FLASH memory；By need be written FLASH memory data and
FLASH memory home address is output to read-write state control module；With the read-write state control module according to control rule
To determine whether to be programmed operation to FLASH memory.
In a preferred embodiment, the control rule includes：Read-write state control module is total to coming from the communication
The FLASH memory inter access address of wire module is made comparisons with the predefined need one or more addresses FLASH to be protected,
Confirm whether inter access address is protected, and when the inter access address is not to be protected address, then the inter access address is straight
The address interface for being output to the FLASH memory is connect, when the inter access address is then to be visited the inside by protection address
It does with asking after predefining transformation in the address interface for being output to FLASH memory.
In a preferred embodiment, the control rule further includes：The read-write state control module is to predetermined free burial ground for the destitute
The state recording that protected data is read in the need one or more addresses FLASH to be protected of location, when protected internal visit
It asks that address is never programmed, then generates corresponding FLASH erasing instructions and programming instruction, and by the number from communication bus module
According to the data-interface for being sent to FLASH memory；When the protected programmed mistake in inter access address, then programming behaviour is skipped
Make.
In a preferred embodiment, the control rule further includes：It is described before carrying out data erasing or programming operation
Read-write state control module checks in the sectors FLASH to be operated whether contain protected data according to predefined rule, such as fans
There are protected data in area, then first read the protected data of the sector and be cached in the cache module, then holds
The erasing operation of the row sector, then successively by the protected data of caching and data to be written from the communication bus module
It is written in the sector.
Compared with prior art, the OTP controller according to the present invention based on piece FLASH memory, utilization and on piece
The OTP controller of FLASH memory close-coupled is deposited to any number of within the scope of arbitrary address on piece FLASH memory
Storage unit does stringent read-write protection, avoids the waste of on piece FLASH storage units, and improves microcontroller and system core
The flexibility of piece design of hardware and software.
Description of the drawings
Fig. 1 is the schematic diagram of the OTP controller based on piece FLASH memory according to an embodiment of the present invention.
Specific implementation mode
Below in conjunction with the accompanying drawings, the specific implementation mode of the present invention is described in detail, it is to be understood that the guarantor of the present invention
Shield range is not restricted by specific implementation.
Unless otherwise explicitly stated, otherwise in entire disclosure and claims, term " comprising " or its change
It changes such as "comprising" or " including " etc. and will be understood to comprise stated element or component, and do not exclude other members
Part or other component parts.
Fig. 1 is the signal according to the OTP controller based on piece FLASH memory of a preferred embodiment of the invention
Figure, the on piece FLASH memory are written and read operation to OTP data.As shown in Figure 1, OTP controller includes：Communication bus mould
Block 101, bus protocol conversion module 102, read-write state control module 103 and OTP interfaces 105.Processor is total by the communication
Wire module 101 is used to carry out reading and writing data, the bus of the communication bus module 101 on piece FLASH memory and OTP controller
Type is AXI or AHB types.Bus protocol conversion module 102 is communicated with the communication bus module 101, by the communication
The bus protocol of bus module 101 is converted to the read-write bus protocol of on piece FLASH memory.Read-write state control module 103
It is communicated with the bus protocol conversion module 102, the read-write state for controlling the on piece FLASH memory.OTP connects
Mouth 105 is communicated with the bus protocol conversion module 102 and the on piece FLASH memory, is existed for OTP data
It is transmitted between OTP controller and the storage unit of the on piece FLASH memory.
In a preferred embodiment, the OTP controller further includes cache module 104, with the on piece FLASH
Memory is into row data communication, the OTP data for caching FLASH memory.
In a preferred embodiment, the capacity of the cache module is equal to the single of the on piece FLASH memory
The capacity of data sector.
Specifically, being to avoid waste FLASH storage units, in embodiments of the present invention, increase in OTP controller
The buffer zone of one piece of FLASH individual datas sector block size caches OTP data.The fan where processor programming OTP data
OTP data are first read out of FLASH memory and are written to slow by Qu Shi, the read-write state control module 103 in OTP controller
In storing module 105, the sectors FLASH are then wiped, then the data of processor write operation are merged with the OTP data that caching gets off and are write
Enter FLASH memory, the address space of memory is utilized to greatest extent.
In another preferred embodiment of the present invention, additionally provides a kind of on piece FLASH with OTP controller and deposit
Reservoir, the on piece FLASH memory are written and read operation to OTP data.The on piece FLASH memory includes：FLASH is stored
Unit and above-mentioned OTP controller.
Below to the work of the on piece FLASH memory according to the preferred embodiment of the present invention with OTP controller original
Reason is briefly described.The read operation of communication bus module 101 is converted to one or more by bus protocol conversion module 102
FLASH reading orders, the reading address of bus is mapped to FLASH memory home address according to predefined rule；On piece data
The write operation of bus is converted to the erasing order and one or more FLASH program commands of one or more sectors FLASH.It reads
Write state control module 103 by from bus protocol conversion module 102 FLASH memory inter access address with it is predefined
Protected one or more FLASH data addresses are needed to make comparisons；If access address is not to be protected address, then the access
Any transformation is not done and is output to FLASH memory address interface in location；If access address is to be protected one of address, then to visiting
Ask that predefined transformation is done in address, such as add fixed offset value, after be output to FLASH memory again.
Before doing programming operation to protected data address, read-write state control module 103 is from piece data memory module
FLASH memory predefined address in read protected data state recording, only when record show this by protection address from
It is not programmed and out-of-date just will produce corresponding FLASH erasing instructions and programming instruction；As record shows this by protection address
It was programmed, then skips this programming operation, and ensured the disposable programmable characteristic of protected location.It is wiped to non-protected data
Except before/programming operation, according to whether protected data is contained in the sectors FLASH of pre-defined rule check operation, such as fanning
There are protected data in area, then first read the protected data of the sectors FLASH and be cached in cache module 104, so
The erasing operation of the sector is executed afterwards, then by the protected data of caching and from the to be written of bus protocol conversion module 102
Data are sequentially written in the sectors FLASH.
In conclusion the OTP controller according to the present invention based on piece FLASH memory, is deposited using on piece FLASH
The OTP controller of reservoir close-coupled does any number of storage unit within the scope of arbitrary address on piece FLASH memory
Stringent read-write protection, avoids the waste of on piece FLASH storage units, and improves microcontroller and System on Chip/SoC software and hardware
The flexibility of design.
It should be understood by those skilled in the art that, embodiments herein can be provided as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the application
Apply the form of example.Moreover, the application can be used in one or more wherein include computer usable program code computer
The computer program production implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.)
The form of product.
The application is with reference to method, the flow of equipment (system) and computer program product according to the embodiment of the present application
Figure and/or block diagram describe.It should be understood that can be realized by computer program instructions every first-class in flowchart and/or the block diagram
The combination of flow and/or box in journey and/or box and flowchart and/or the block diagram.These computer programs can be provided
Instruct the processor of all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine so that the instruction executed by computer or the processor of other programmable data processing devices is generated for real
The device for the function of being specified in present one flow of flow chart or one box of multiple flows and/or block diagram or multiple boxes.
These computer program instructions, which may also be stored in, can guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works so that instruction generation stored in the computer readable memory includes referring to
Enable the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one box of block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device so that count
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, in computer or
The instruction executed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in a box or multiple boxes.It is aforementioned to the present invention specific exemplary embodiment description be for
The purpose of explanation and illustration.These descriptions are not wishing to limit the invention to disclosed precise forms, and it will be apparent that root
According to above-mentioned introduction, can carry out many change and variations.The purpose of selecting and describing the exemplary embodiment is that explaining
The certain principles and practical application of the present invention, so that those skilled in the art can realize and utilize each of the present invention
Kind different exemplary implementation scheme and various chooses and changes.The scope of the present invention be intended to by claims and
Its equivalent form is limited.
Claims (12)
1. a kind of OTP controller based on piece FLASH memory carries out the read-write operation of the on piece FLASH memory
Control, which is characterized in that the OTP controller includes：
Communication bus module, processor are used to carry out on piece FLASH memory and OTP controller by the communication bus module
Reading and writing data；
Bus protocol conversion module is communicated with the communication bus module, by the bus protocol of the communication bus module
Be converted to the read-write bus protocol of on piece FLASH memory；
Read-write state control module is communicated with the bus protocol conversion module, is deposited for controlling the on piece FLASH
The read-write state of reservoir；And
OTP interfaces are communicated with the bus protocol conversion module and the on piece FLASH memory, are used for OTP numbers
According to the transmission between the OTP controller and the storage unit of the on piece FLASH memory.
2. OTP controller as described in claim 1, which is characterized in that the read-write state control module is described logical to coming from
The FLASH memory inter access address and the predefined need one or more addresses FLASH to be protected for believing bus module are made
Compare, confirms whether inter access address is protected, when the inter access address is not to be protected address, then the inter access
Location is directly output to the address interface of the FLASH memory, when the inter access address be by protection address, then it is interior to this
Portion's access is done after predefined transformation in the address interface for being output to FLASH memory.
3. OTP controller as claimed in claim 2, which is characterized in that the read-write state control module is to predefined address
The need one or more addresses FLASH to be protected in read protected data state recording, when protected inter access
Address is never programmed, then generates corresponding FLASH erasing instructions and programming instruction, and by the data from communication bus module
It is sent to the data-interface of FLASH memory；When the protected programmed mistake in inter access address, then programming operation is skipped.
4. OTP controller as claimed in claim 3, which is characterized in that the OTP controller further includes cache module, is being carried out
Before data erasing or programming operation, the read-write state control module checks the sectors FLASH to be operated according to predefined rule
Inside whether contain protected data, as there are protected data in sector, then first the protected data of the sector is read and delayed
It is stored in the cache module, then executes the erasing operation of the sector, then by the protected data of caching and from described logical
The data to be written of letter bus module are sequentially written in the sector.
5. a kind of on piece FLASH memory with OTP controller, the on piece FLASH memory can carry out OTP data
Read-write operation, which is characterized in that the on piece FLASH memory includes：
FLASH storage units；And
OTP controller, the OTP controller include：
Communication bus module, processor are used for on piece FLASH units and OTP controller by the communication bus module into line number
According to read-write；
Bus protocol conversion module is communicated with the communication bus module, by the bus protocol of the communication bus module
Be converted to the read-write bus protocol of on piece FLASH storage units；
Read-write state control module is communicated with the bus protocol conversion module, is deposited for controlling the on piece FLASH
The read-write state of storage unit；With
OTP interfaces are communicated with the bus protocol conversion module and the on piece FLASH storage units, are used for OTP
Transmission of the data between the OTP controller and the FLASH storage units.
6. the on piece FLASH memory with OTP controller as claimed in claim 5, which is characterized in that read-write state controls
Module to from the FLASH memory inter access address of the communication bus module with it is predefined need to it is to be protected one or
Multiple addresses FLASH are made comparisons, and confirm whether inter access address is protected, when the inter access address is not by protecting field
Location, then the inter access address be directly output to the address interface of the FLASH memory, when the inter access address be quilt
Address is protected, then to the inter access is done after predefining transformation in the address interface for being output to FLASH memory.
7. the on piece FLASH memory with OTP controller as claimed in claim 6, which is characterized in that the read-write state
The state note of protected data is read in the control module one or more addresses FLASH to be protected to the need of predefined address
Record then generates corresponding FLASH erasing instructions and programming instruction, and will when protected inter access address is never programmed
Data from communication bus module are sent to the data-interface of FLASH memory；When protected inter access address by
It is programmed, then skip programming operation.
8. the on piece FLASH memory with OTP controller as claimed in claim 7, which is characterized in that the OTP controls
Device further includes cache module, and before carrying out data erasing or programming operation, the read-write state control module is according to predefined rule
It then checks in the sectors FLASH to be operated and whether contains protected data, as there is protected data in sector, then first by the fan
The protected data in area reads and is cached in the cache module, then executes the erasing operation of the sector, then by caching
Protected data and data to be written from the communication bus module are sequentially written in the sector.
9. a kind of read/writing control method of OTP data on piece FLASH memory, includes the following steps：
OTP data inputs are carried out on piece FLASH memory by communication bus module；
The bus protocol of the communication bus module is converted to the read-write bus protocol of on piece FLASH memory；
The data for needing write-in FLASH memory and FLASH memory home address are output to read-write state control module；With
The read-write state control module determines whether to be programmed operation to FLASH memory according to control rule.
10. as claimed in claim 9 to the read/writing control method of the OTP data of on piece FLASH memory, wherein the control
Rule includes：
Read-write state control module to from the FLASH memory inter access address of the communication bus module with it is predefined
It needs the one or more addresses FLASH to be protected to make comparisons, confirms whether inter access address is protected, when the inter access
Location is not to be protected address, then the inter access address is directly output to the address interface of the FLASH memory, when this is interior
Portion's access address is then to the inter access to be done after predefining transformation on the ground for being output to FLASH memory by protection address
Location interface.
11. as claimed in claim 10 to the read/writing control method of the OTP data of on piece FLASH memory, wherein the control
Rule processed further includes：
It reads and is protected in the read-write state control module one or more addresses FLASH to be protected to the need of predefined address
The state recording for protecting data, when protected inter access address is never programmed, then generate corresponding FLASH erasing instructions and
Programming instruction, and the data from communication bus module are sent to the data-interface of FLASH memory；When protected inside
The programmed mistake of access address, then skip programming operation.
12. as claimed in claim 11 to the read/writing control method of the OTP data of on piece FLASH memory, wherein the control
Rule processed further includes：
Before carrying out data erasing or programming operation, the read-write state control module checks to be operated according to predefined rule
Whether contain protected data in the sectors FLASH, as there are protected data in sector, then first by the protected data of the sector
It reads and is cached in the cache module, then execute the erasing operation of the sector, then by the protected data of caching and come
It is sequentially written in the sector from the data to be written of the communication bus module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810684179.5A CN108563590B (en) | 2018-06-28 | 2018-06-28 | OTP controller and control method based on-chip FLASH memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810684179.5A CN108563590B (en) | 2018-06-28 | 2018-06-28 | OTP controller and control method based on-chip FLASH memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108563590A true CN108563590A (en) | 2018-09-21 |
| CN108563590B CN108563590B (en) | 2024-02-23 |
Family
ID=63554821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810684179.5A Active CN108563590B (en) | 2018-06-28 | 2018-06-28 | OTP controller and control method based on-chip FLASH memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108563590B (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109902035A (en) * | 2019-02-03 | 2019-06-18 | 成都皮兆永存科技有限公司 | Composite memory |
| CN110399314A (en) * | 2019-06-25 | 2019-11-01 | 苏州浪潮智能科技有限公司 | A kind of CPU, a kind of electronic equipment and a kind of cpu cache control method |
| CN111159071A (en) * | 2019-12-31 | 2020-05-15 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN111221754A (en) * | 2020-02-24 | 2020-06-02 | 山东华芯半导体有限公司 | Storage device with read-write collision prevention function |
| CN111782288A (en) * | 2020-06-30 | 2020-10-16 | 联想(北京)有限公司 | Electronic device and control method thereof |
| CN113035249A (en) * | 2019-12-24 | 2021-06-25 | 澜起电子科技(昆山)有限公司 | Information tamper-proofing system and method |
| CN116088948A (en) * | 2022-12-28 | 2023-05-09 | 芯动微电子科技(武汉)有限公司 | Method for in-place execution of system on chip from flash memory, electronic device and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1504899A (en) * | 2002-12-04 | 2004-06-16 | 联发科技股份有限公司 | Data management method and configuration manner for memory |
| US20060044934A1 (en) * | 2004-09-02 | 2006-03-02 | Micron Technology, Inc. | Cluster based non-volatile memory translation layer |
| GB0723211D0 (en) * | 2004-05-11 | 2008-01-09 | Spansion Llc | Semiconductor device and control method of the same |
| CN102129486A (en) * | 2010-10-20 | 2011-07-20 | 杭州晟元芯片技术有限公司 | Novel OTP implementation method |
| CN102999453A (en) * | 2012-10-12 | 2013-03-27 | 杭州中天微系统有限公司 | Universal nonvolatile memory control device for system on chip |
| CN208444289U (en) * | 2018-06-28 | 2019-01-29 | 北京智芯微电子科技有限公司 | OTP controller based on piece FLASH memory |
-
2018
- 2018-06-28 CN CN201810684179.5A patent/CN108563590B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1504899A (en) * | 2002-12-04 | 2004-06-16 | 联发科技股份有限公司 | Data management method and configuration manner for memory |
| GB0723211D0 (en) * | 2004-05-11 | 2008-01-09 | Spansion Llc | Semiconductor device and control method of the same |
| US20060044934A1 (en) * | 2004-09-02 | 2006-03-02 | Micron Technology, Inc. | Cluster based non-volatile memory translation layer |
| CN102129486A (en) * | 2010-10-20 | 2011-07-20 | 杭州晟元芯片技术有限公司 | Novel OTP implementation method |
| CN102999453A (en) * | 2012-10-12 | 2013-03-27 | 杭州中天微系统有限公司 | Universal nonvolatile memory control device for system on chip |
| CN208444289U (en) * | 2018-06-28 | 2019-01-29 | 北京智芯微电子科技有限公司 | OTP controller based on piece FLASH memory |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109902035A (en) * | 2019-02-03 | 2019-06-18 | 成都皮兆永存科技有限公司 | Composite memory |
| CN109902035B (en) * | 2019-02-03 | 2023-10-31 | 成都皮兆永存科技有限公司 | composite memory |
| CN110399314A (en) * | 2019-06-25 | 2019-11-01 | 苏州浪潮智能科技有限公司 | A kind of CPU, a kind of electronic equipment and a kind of cpu cache control method |
| CN113035249A (en) * | 2019-12-24 | 2021-06-25 | 澜起电子科技(昆山)有限公司 | Information tamper-proofing system and method |
| WO2021128703A1 (en) * | 2019-12-24 | 2021-07-01 | 澜起电子科技(昆山)有限公司 | Information tamper-proofing system and method |
| CN113035249B (en) * | 2019-12-24 | 2023-09-26 | 澜起电子科技(昆山)有限公司 | Information tamper-proof system and method |
| CN111159071A (en) * | 2019-12-31 | 2020-05-15 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN111159071B (en) * | 2019-12-31 | 2023-08-08 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN111221754A (en) * | 2020-02-24 | 2020-06-02 | 山东华芯半导体有限公司 | Storage device with read-write collision prevention function |
| CN111782288A (en) * | 2020-06-30 | 2020-10-16 | 联想(北京)有限公司 | Electronic device and control method thereof |
| CN116088948A (en) * | 2022-12-28 | 2023-05-09 | 芯动微电子科技(武汉)有限公司 | Method for in-place execution of system on chip from flash memory, electronic device and storage medium |
| CN116088948B (en) * | 2022-12-28 | 2023-08-22 | 芯动微电子科技(武汉)有限公司 | Method for in-place execution of system on chip from flash memory, electronic device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108563590B (en) | 2024-02-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108563590A (en) | OTP controller based on piece FLASH memory and control method | |
| US8010770B2 (en) | Caching device for NAND flash translation layer | |
| CN106484316B (en) | Method for managing a memory device, memory device and controller | |
| JP4004468B2 (en) | Method and system for having large pages supported | |
| JP5002201B2 (en) | Memory system | |
| US6081878A (en) | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices | |
| US7953950B2 (en) | Storage device including flash memory and capable of predicting storage device performance | |
| KR100533682B1 (en) | Data managing device and method for flash memory | |
| US20120246399A1 (en) | Storage Device and Memory Controller | |
| CN110018787A (en) | Based on the system-wide firmware reading/writing method of SSD, device and computer equipment | |
| CN105975404A (en) | Nonvolatile memory device and method of operating the same | |
| CN208444289U (en) | OTP controller based on piece FLASH memory | |
| US20050268026A1 (en) | Memory card, semiconductor device, and method of controlling semiconductor memory | |
| US20220229571A1 (en) | Data storage device with configurable policy-based storage device behavior | |
| EP3057100B1 (en) | Memory device and operating method of same | |
| US20030182497A1 (en) | Information storage apparatus | |
| CN110489050A (en) | The programmed method of data memory device and system information | |
| JP4972410B2 (en) | Method for controlling access in flash memory and system for implementation of such method | |
| JP4316824B2 (en) | MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD | |
| CN108108118A (en) | Method for writing data and storage control | |
| KR100479170B1 (en) | Access control device for memory and method thereof | |
| US6898680B2 (en) | Minimization of overhead of non-volatile memory operation | |
| CN106484630A (en) | The Memory Controller of the access method of flash memory and correlation and electronic installation | |
| JPH06162786A (en) | Information processor using flash memory | |
| CN104881619B (en) | Electronic equipment and the method for realizing non-volatile memory medium write-protect for electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |