CN102129486A - Novel OTP implementation method - Google Patents
Novel OTP implementation method Download PDFInfo
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- CN102129486A CN102129486A CN 201010516812 CN201010516812A CN102129486A CN 102129486 A CN102129486 A CN 102129486A CN 201010516812 CN201010516812 CN 201010516812 CN 201010516812 A CN201010516812 A CN 201010516812A CN 102129486 A CN102129486 A CN 102129486A
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Abstract
The invention relates to a novel OTP (One Time Programmable) implementation method. A part of memory area of a SOC (System On Chip) integrated nonvolatile memory module and a method for combining hardware with system software are adopted to implement two functions below: 1, a memory space for serial numbers is set aside in the memory area of the nonvolatile memory module, and a user cannot write, but only read in the memory space, and unique serial numbers are written in the memory space during chip test; and 2, a special area is partially set aside in the memory area of the nonvolatile memory module, the method for combining hardware with system software is adopted to ensure that the user completes write lock through user configuration parameters when completing write operation for the special area, and once the write operation is locked, the chip cannot modify the write operation-locked area after being re-electrified. The method has the advantages that: the integration of a third-party OTP memory is not required, the chip design complexity is reduced, and the cost is lowered since independent test for OTP is not required during chip test.
Description
Technical field
The present invention relates to the IC design field, especially a kind of new O TP implementation method.
Background technology
The user often needs self-developed product can both be convenient to management in development, and the general so interior chip of product that requires all has unique sequence number conveniently to manage the product of oneself.Cost pressure increases gradually between the like product, need the each side on the product chain all to reduce cost constantly trying every possible means, this point just requires under the situation that does not increase cost as far as possible even reduce cost being applied in the chip design, utilizes existing resource can do more thing.The cost of the chip that function is intact comprises a lot of links, correspond to the design phase, need as far as possible with less logic gate finish satisfactory function (area of chip relates to the cost of chip, the area of single chips big more (logic gate is many more), cost is big more.Chip design generally comprises: design proposal with testing scheme formulation, detailed functions design, chip production, nude film test, Chip Packaging, become flow processs such as built-in testing.The nude film test was meant chip before there be not encapsulation, need need the cooperation of test machine in the time of test to the partial function test of chip, and test machine is sent satisfactory sequential, and nude film could be carried out corresponding action).
As shown in Figure 1, traditional SOC (system on a chip) (SOC, system on chip) generally comprises CPU, storer, Instructions Cache, metadata cache and various interface circuit etc., One Time Programmable (OTP, one time program) storer is to be independent of other storeies, described otp memory is merely able to carry out the storer of one-time programming, all is that the content 1 of storage area is changed over 0 generally.The OTP storage area generally also is divided into 2 main region: 1, serial number area: write in the process of chip production, after production was finished, the user can not change; 2, user's open area: after this part zone produced and finishes, the primary data of All Ranges all was 1, and the user can carry out write operation to this part open zone, and after one grade of write operation was finished, the user can not change.Realize the OTP function in traditional SOC design, need in SOC, integrate the OTP IP that the third party provides.
Since otp memory be with other storeies fully independently, so all need to increase the functional requirement that extra resource satisfies chip in the whole stage of finishing of chip.The deficiency of its technology is: 1, need integrate third-party otp memory chip design the time, increase the complexity of chip design; 2, increased third-party otp memory, the cost of chip design has increase (OTP need take area of chip), because otp memory is a storer independently, so need independently test OTP chip testing the time, Ce Shi cost also can increase to some extent like this.
Summary of the invention
The present invention will solve the shortcoming of above-mentioned prior art, and a kind of new O TP implementation method is provided, and utilizes the function of the method realization OTP that traditional nonvolatile memory is real and software and hardware is coordinated.
The present invention solves the technical scheme that its technical matters adopts: this new O TP implementation method, and step is as follows:
(1), the storer in the SOC system is provided with nonvolatile memory and volatile memory, is provided with the OTP memory block in the nonvolatile memory, described OTP memory partitioning becomes two memory blocks in sequence number memory block and user open zone;
(2), in nude film test, chip is finished the programming of unique sequence number by embedded logic control to the sequence number memory block, makes the user can't change the content of this storage area;
(3), when nonvolatile memory is operated, judge at first whether the zone that will operate is the address area of OTP memory block, if the address area of right and wrong OTP memory block then can carry out according to the operation steps of normal running storer, if the scope of visit is the address area of OTP memory block, then at first judge whether it is the address area of sequence number memory block, if the address area of sequence number memory block, the user can only read to carry out write operation, if the address area in the user open zone of visit OTP, hardware logic judges whether the zone bit of writing complete operation is set, set then can not continue to write, otherwise the user can carry out this regional write operation satisfying under the condition write OTP user open zone.
As preferably, the generation method step of writing the zone bit of complete operation in the OTP user open zone is: reserve a zone bit in the user open zone, the user can only carry out write operation to this zone bit, can not carry out erase operation; In a single day the user all finishes the write operation order, can be to this zone bit set, and chip can be read this zone bit at every turn after powering on; If this zone bit is set, then chip internal can generate the zone bit of writing complete operation with the zone bit correspondence, chip when write operation is carried out in OTP user open zone at first the judgement symbol position whether be set, if be set, then do not carry out write operation to OTP user open zone.
As preferably, described SOC system also comprises CPU, Instructions Cache, metadata cache and interface circuit.
As preferably, described nonvolatile memory is the FLASH storer.
As preferably, described nonvolatile memory is an eeprom memory.
As preferably, the address realm of described OTP memory block is less than the address realm of nonvolatile memory.
The effect that the present invention is useful is: the part storage area of the non-volatile memory modules that employing SOC chip has been integrated, the method of utilizing hardware and system software to combine realizes following two kinds of functions: 1, the storage area of nonvolatile memory is reserved the storage space of sequence number, this part storage space user can only read and can not write, and in chip testing unique sequence number is write in this part zone; 2, the storage area of nonvolatile memory reserves the part special area, the method that adopts software and hardware to combine realizes that the user is when finishing write operation to this part zone, finish by user's configuration parameter and to write locking (, can not make amendment to the zone of this part write operation locking after chip re-powers) in case write operation is locked.Do not need to integrate third-party otp memory, reduced the complexity of chip design, and need when chip testing, independently not test, reduce cost OTP.
Description of drawings
Fig. 1 is the prior art system structured flowchart;
Fig. 2 is a system architecture diagram of the present invention;
Fig. 3 is a synoptic diagram of among the present invention the serial number area of chip being carried out write operation;
Fig. 4 is the temporal and logic relation synoptic diagram of three port correspondences among the present invention;
Fig. 5 is an OTP memory block operating process synoptic diagram among the present invention;
Fig. 6 is the generation synoptic diagram that OTP user writes in the open zone complement mark position among the present invention.
Embodiment
The invention will be further described below in conjunction with drawings and Examples:
The intrasystem basic function of the SOC of the present invention still scheme with traditional is consistent, just when handling the OTP module, adopted relatively particular processing method, under the situation of chip, utilize the subregion of this storer to realize the function that OTP needs at nonvolatile memory.
As shown in Figure 2, SOC of the present invention system comprises CPU, Instructions Cache, metadata cache, volatile memory, various interface circuit and nonvolatile memory.Described nonvolatile memory comprises the OTP memory block, and described OTP memory block is provided with the sequence number memory block and uses the user open zone of operating for the user.In the present embodiment, the address realm of OTP memory block equals the address realm of nonvolatile memory.In other embodiments, nonvolatile memory also can be provided with other functional areas except being provided with the OTP memory block, and therefore, the address realm of described OTP memory block can be less than the address realm of nonvolatile memory.In the present embodiment, described nonvolatile memory can be FLASH or EEPROM, so is provided with, and described nonvolatile memory not only is convenient to user's write operation, also is convenient to the user and carries out erase operation.At nonvolatile memory described in other embodiments of the present invention also can be other nonvolatile memories that can satisfy user's write operation and erase operation.
This new O TP implementation method, concrete steps are as follows:
(1), the storer in the SOC system is provided with nonvolatile memory and volatile memory, is provided with the OTP memory block in the nonvolatile memory, wherein the OTP memory partitioning becomes two memory blocks in sequence number memory block and user open zone;
(2), in nude film test, chip is finished the programming of unique sequence number by embedded logic control to the sequence number memory block, makes the user can't change the content of this storage area;
Fig. 3 is a synoptic diagram of nude film test time the address area of the sequence number memory block of chip being carried out write operation, chip is under test pattern, use three ports to finish write operation, be respectively tck, strobe and tdio, the temporal and logic relation of three port correspondences as shown in Figure 4, whole flow process is divided into 4 sections:
Start section: the opening flag of order;
Cmd section: corresponding order, the ensuing injunctive write order of 001 expression herein;
The Address section: corresponding is address field, the address that this section description will be operated;
Data section: corresponding data segment, the data that correspondence will write in the time of write operation.
Chip is finished write operation to the sequence number district by above-mentioned logic control in nude film test,
(3), as shown in Figure 5, OTP user development area utilizes the software-hardware synergism method of operating to reach the implementation method in traditional OTP zone.The user is when operating nonvolatile memory, judge at first whether the zone that will operate is the address area of OTP memory block, if the address area of right and wrong OTP memory block then can carry out according to the operation steps of normal running storer, if the scope of visit is the address area of OTP memory block, then at first judge whether it is the address area of sequence number memory block, if the address area of sequence number memory block, the user can only read to carry out write operation, if the address area in the user open zone of visit OTP, hardware logic judges whether the zone bit (OTP_USE_W_F) of writing complete operation is set, set then can not continue to write, otherwise the user can carry out this regional write operation satisfying under the condition write OTP user open zone.
Write the generation method of the zone bit of complete operation in the OTP user open zone, concrete steps as shown in Figure 6, reserve a zone bit in the user open zone, the user can only carry out write operation (in order to prevent maloperation to this zone bit, to carry out the affirmation of the logical order relevant before writing with the write operation order), can not carry out erase operation; In a single day the user all finishes the write operation order, can be to this zone bit set, and chip can be read this zone bit at every turn after powering on; If this zone bit is set, then chip internal can generate the zone bit of writing complete operation (OTP_USE_W_F) with the zone bit correspondence, chip when write operation is carried out in OTP user open zone at first judgement symbol position (OTP_USE_W_F) whether be set, if be set, then do not carry out write operation to OTP user open zone.
In addition to the implementation, the present invention can also have other embodiments.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop on the protection domain of requirement of the present invention.
Claims (6)
1. new O TP implementation method, it is characterized in that: step is as follows:
(1), the storer in the SOC system is provided with nonvolatile memory and volatile memory, is provided with the OTP memory block in the nonvolatile memory, wherein the OTP memory partitioning becomes two memory blocks in sequence number memory block and user open zone;
(2), in nude film test, chip is finished the programming of unique sequence number by embedded logic control to the sequence number memory block, makes the user can't change the content of this storage area;
(3), when nonvolatile memory is operated, judge at first whether the zone that will operate is the address area of OTP memory block, if the address area of right and wrong OTP memory block then can carry out according to the operation steps of normal running storer, if the scope of visit is the address area of OTP memory block, then at first judge whether it is the address area of sequence number memory block, if the address area of sequence number memory block, the user can only read to carry out write operation, if the address area in the user open zone of visit OTP, hardware logic judges whether the zone bit of writing complete operation is set, set then can not continue to write, otherwise the user can carry out this regional write operation satisfying under the condition write OTP user open zone.
2. new O TP implementation method according to claim 1, it is characterized in that: the generation method step of writing the zone bit of complete operation in the OTP user open zone is: reserve a zone bit in the user open zone, the user can only carry out write operation to this zone bit, can not carry out erase operation; In a single day the user all finishes the write operation order, can be to this zone bit set, and chip can be read this zone bit at every turn after powering on; If this zone bit is set, then chip internal can generate the zone bit of writing complete operation with the zone bit correspondence, chip when write operation is carried out in OTP user open zone at first the judgement symbol position whether be set, if be set, then do not carry out write operation to OTP user open zone.
3. new O TP implementation method according to claim 1 is characterized in that: described SOC system also comprises CPU, Instructions Cache, metadata cache and interface circuit.
4. new O TP implementation method according to claim 1 is characterized in that: described nonvolatile memory is the Flash storer.
5. new O TP implementation method according to claim 1 is characterized in that: described nonvolatile memory is the eeprom storer.
6. according to any described new O TP implementation method in the claim 1 to 5, it is characterized in that: the address realm of described OTP memory block is less than the address realm of nonvolatile memory.
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| CN102768331A (en) * | 2012-07-26 | 2012-11-07 | 深圳市芯海科技有限公司 | Testing device and testing method for OTP (one time programmable) type MCU (microprogrammed control unit) |
| CN103019950A (en) * | 2012-12-28 | 2013-04-03 | 信利光电(汕尾)有限公司 | Space allocation method and use method of one-time programmable chip and device |
| CN104239276A (en) * | 2014-09-05 | 2014-12-24 | 四川和芯微电子股份有限公司 | SOC (System On Chip) |
| CN105094925A (en) * | 2015-08-25 | 2015-11-25 | 无锡力芯微电子股份有限公司 | Rolling code burning method and system for universal one-time programmable chip |
| CN106571914A (en) * | 2016-11-09 | 2017-04-19 | 深圳市博巨兴实业发展有限公司 | Secret key management device based on OTP device |
| CN106648713A (en) * | 2015-10-28 | 2017-05-10 | 深圳市博巨兴实业发展有限公司 | OTP programming method and device |
| CN108563590A (en) * | 2018-06-28 | 2018-09-21 | 北京智芯微电子科技有限公司 | OTP controller based on piece FLASH memory and control method |
| CN108763149A (en) * | 2018-06-05 | 2018-11-06 | 广州微智科电子科技有限公司 | A kind of Embedded SoC |
| CN111159071A (en) * | 2019-12-31 | 2020-05-15 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN112232004A (en) * | 2020-12-14 | 2021-01-15 | 鹏城实验室 | System-on-chip design scheme test method and system-on-chip |
| CN116482514A (en) * | 2023-04-25 | 2023-07-25 | 苏州领慧立芯科技有限公司 | Apparatus and method for chip power-on auto-calibration |
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| CN102768331B (en) * | 2012-07-26 | 2016-06-15 | 深圳市芯海科技有限公司 | The MCU test set of a kind of OTP type and testing method thereof |
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| CN106571914B (en) * | 2016-11-09 | 2020-03-27 | 深圳市博巨兴微电子科技有限公司 | Secret key management device based on OTP device |
| CN106571914A (en) * | 2016-11-09 | 2017-04-19 | 深圳市博巨兴实业发展有限公司 | Secret key management device based on OTP device |
| CN108763149A (en) * | 2018-06-05 | 2018-11-06 | 广州微智科电子科技有限公司 | A kind of Embedded SoC |
| CN108563590B (en) * | 2018-06-28 | 2024-02-23 | 北京智芯微电子科技有限公司 | OTP controller and control method based on-chip FLASH memory |
| CN108563590A (en) * | 2018-06-28 | 2018-09-21 | 北京智芯微电子科技有限公司 | OTP controller based on piece FLASH memory and control method |
| CN111159071A (en) * | 2019-12-31 | 2020-05-15 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN111159071B (en) * | 2019-12-31 | 2023-08-08 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN112232004B (en) * | 2020-12-14 | 2021-04-09 | 鹏城实验室 | System-on-chip design scheme test method and system-on-chip |
| CN112232004A (en) * | 2020-12-14 | 2021-01-15 | 鹏城实验室 | System-on-chip design scheme test method and system-on-chip |
| CN116482514A (en) * | 2023-04-25 | 2023-07-25 | 苏州领慧立芯科技有限公司 | Apparatus and method for chip power-on auto-calibration |
| CN116482514B (en) * | 2023-04-25 | 2024-01-12 | 苏州领慧立芯科技有限公司 | Apparatus and method for chip power-on auto-calibration |
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Application publication date: 20110720 |