CN108563590B - OTP controller and control method based on-chip FLASH memory - Google Patents
OTP controller and control method based on-chip FLASH memory Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1673—Details of memory controller using buffers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
Abstract
The invention provides an OTP controller and a control method based on an on-chip FLASH memory. The OTP controller includes: the processor is used for reading and writing data of the on-chip FLASH memory and the OTP controller through the communication bus module; the bus protocol conversion module is communicated with the communication bus module and converts the bus protocol of the communication bus module into a read-write bus protocol of the on-chip FLASH memory; the read-write state control module is communicated with the bus protocol conversion module and is used for controlling the read-write state of the on-chip FLASH memory; and an OTP interface which communicates with the bus protocol conversion module and the on-chip FLASH memory and is used for transmitting OTP data between the OTP controller and a storage unit of the on-chip FLASH memory. The OTP controller can read and write the data of the FLASH memory in one-time programming and can protect the OTP data from being rewritten.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to an OTP controller and a control method based on an on-chip FLASH memory.
Background
Microcontrollers and systems on chip often require strict protection of portions of the program code and/or data that can be read by only an authorized user in a specific manner, and once written, cannot be altered or deleted by any user. If these critical codes and/or data are read by unauthorized users or altered/deleted, the performance and reliability of the overall system will be severely impacted.
In early microcontroller and system chip designs, these code and/or data that needs to be protected were cured in Read-Only-Memory (ROM). However, the content of the ROM is fixed during the manufacture of the chip, and the same chip cannot store different codes and/or data in the ROM for different users or applications. In order to improve flexibility, currently, the mainstream design embeds an OTP (One Time Programmable, one-time programmable) EPROM memory based on an antifuse technology or a floating gate technology into a chip, the content of which can be written by a user after the chip leaves the factory, and meanwhile, the content cannot be changed/deleted because the OTP EPROM can only be written once, thereby realizing data protection.
Embedded FLASH memory is a non-volatile memory device that is widely used on microcontrollers and system chips for storing program code and/or data. Compared with OTP EPROM, the embedded FLASH memory has the advantages of large storage scale, repeated programming for a plurality of times and convenient test. Thus, there is now an increasing number of chip designs using embedded FLASH memory instead of OTP EPROM.
Because the embedded FLASH memory is rewritable, to protect key data therein from being rewritten or read by unauthorized users, other hardware or software on the chip is required to control the operations of reading, deleting and programming the embedded FLASH memory. The embedded FLASH memory is characterized in that the internal storage unit is organized according to sectors, the minimum object of the deleting operation is also a sector, and the corresponding software or hardware for controlling the operation of the embedded FLASH memory is also a sector which is also the minimum control object.
At present, a protection circuit for data in an on-chip FLASH memory can only protect the data in one sector or a plurality of sectors with continuous addresses basically, if the data to be protected is smaller than one sector or the data addresses are discontinuous, other storage units of the sector where the protected data are located cannot be read and written by a user as common storage units at will, so that resource waste is caused, and the product cost is increased.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide an OTP controller based on an on-chip FLASH memory, which can read and write data of the FLASH memory in one-time programming.
It is another object of the present invention to provide an OTP controller based on-chip FLASH memory that is capable of protecting OTP data from being overwritten.
In order to achieve the above purpose, the present invention provides an OTP controller based on an on-chip FLASH memory, which controls the read-write operation of the on-chip FLASH memory. The OTP controller includes: the processor is used for reading and writing data of the on-chip FLASH memory and the OTP controller through the communication bus module; the bus protocol conversion module is communicated with the communication bus module and converts the bus protocol of the communication bus module into a read-write bus protocol of the on-chip FLASH memory; the read-write state control module is communicated with the bus protocol conversion module and is used for controlling the read-write state of the on-chip FLASH memory; and an OTP interface which communicates with the bus protocol conversion module and the on-chip FLASH memory and is used for transmitting OTP data between the OTP controller and a storage unit of the on-chip FLASH memory.
In a preferred embodiment, the OTP controller further comprises: and the caching module is in data communication with the on-chip FLASH memory and is used for caching OTP data of the FLASH memory.
In a preferred embodiment, the capacity of the buffer module is equal to the capacity of a single data sector of the on-chip FLASH memory.
In a preferred embodiment, the bus type of the communication bus module is an AXI or AHB type.
In a preferred embodiment, the read-write state control module compares the internal access address of the FLASH memory from the communication bus module with one or more predefined FLASH addresses to be protected, and confirms whether the internal access address is protected, when the internal access address is not the protected address, the internal access address is directly output to the address interface of the FLASH memory, when the internal access address is the protected address, the predefined conversion is performed on the internal access address, and then the internal access address is output to the address interface of the FLASH memory.
In a preferred embodiment, the read-write status control module reads the status record of the protected data from one or more FLASH addresses of the predefined address to be protected, generates corresponding FLASH erase command and programming command when the protected internal access address is never programmed, and sends the data from the communication bus module to the data interface of the FLASH memory; when the protected internal access address has been programmed, the programming operation is skipped.
In a preferred embodiment, before performing the data erasing or programming operation, the read-write state control module checks whether the FLASH sector to be operated contains the protected data according to a predefined rule, if so, reads the protected data of the sector and caches the protected data in the cache module, then performs the erasing operation of the sector, and then sequentially writes the cached protected data and the data to be written from the communication bus module into the sector.
Another aspect of the present invention provides an on-chip FLASH memory with an OTP controller that is capable of performing read and write operations of OTP data. The on-chip FLASH memory comprises: FLASH memory unit, and OTP controller mentioned above. The OTP controller includes: the processor is used for reading and writing data of the on-chip FLASH memory and the OTP controller through the communication bus module; the bus protocol conversion module is communicated with the communication bus module and converts the bus protocol of the communication bus module into a read-write bus protocol of the on-chip FLASH memory; the read-write state control module is communicated with the bus protocol conversion module and is used for controlling the read-write state of the on-chip FLASH storage unit; and an OTP interface which communicates with the bus protocol conversion module and the on-chip FLASH memory and is used for transmitting OTP data between the OTP controller and a storage unit of the on-chip FLASH memory.
In a preferred embodiment, the capacity of the buffer module is equal to the capacity of a single data sector of the on-chip FLASH memory. The bus type of the communication bus module is an AXI or AHB type.
In another aspect, the present invention provides a method for controlling read/write of OTP data in an on-chip FLASH memory, including the steps of: OTP data input is carried out on the on-chip FLASH memory through the communication bus module; converting the bus protocol of the communication bus module into a read-write bus protocol of an on-chip FLASH memory; outputting the data to be written into the FLASH memory and the internal address of the FLASH memory to a read-write state control module; and the read-write state control module determines whether to program the FLASH memory according to the control rule.
In a preferred embodiment, the control rule comprises: the read-write state control module compares the internal access address of the FLASH memory from the communication bus module with one or more FLASH addresses which are predefined and need to be protected, confirms whether the internal access address is protected, and when the internal access address is not the protected address, the internal access address is directly output to the address interface of the FLASH memory, and when the internal access address is the protected address, the predefined conversion is carried out on the internal access address, and then the internal access address is output to the address interface of the FLASH memory.
In a preferred embodiment, the control rule further comprises: the read-write state control module reads the state record of the protected data from one or more FLASH addresses which are required to be protected of the predefined address, generates corresponding FLASH erasing instructions and programming instructions when the protected internal access address is not programmed, and sends the data from the communication bus module to a data interface of the FLASH memory; when the protected internal access address has been programmed, the programming operation is skipped.
In a preferred embodiment, the control rule further comprises: before data erasing or programming operation is performed, the read-write state control module checks whether the FLASH sector to be operated contains protected data or not according to a predefined rule, if so, the protected data of the sector is read out and cached into the cache module, then the erasing operation of the sector is performed, and then the cached protected data and the data to be written from the communication bus module are sequentially written into the sector.
Compared with the prior art, the OTP controller based on the on-chip FLASH memory, provided by the invention, has the advantages that the OTP controller tightly coupled with the on-chip FLASH memory is utilized to strictly read and write protect any number of memory units in any address range in the on-chip FLASH memory, so that the waste of the on-chip FLASH memory units is avoided, and the flexibility of the software and hardware design of a microcontroller and a system chip is improved.
Drawings
Fig. 1 is a schematic diagram of an OTP controller based on-chip FLASH memory according to an embodiment of the invention.
Detailed Description
The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
Fig. 1 is a schematic diagram of an OTP controller based on an on-chip FLASH memory that performs read and write operations on OTP data according to a preferred embodiment of the invention. As shown in fig. 1, the OTP controller includes: a communication bus module 101, a bus protocol conversion module 102, a read-write state control module 103, and an OTP interface 105. The processor is used for reading and writing data from and to the on-chip FLASH memory and the OTP controller through the communication bus module 101, and the bus type of the communication bus module 101 is an AXI or AHB type. The bus protocol conversion module 102 communicates with the communication bus module 101, and converts the bus protocol of the communication bus module 101 into a read-write bus protocol of the on-chip FLASH memory. The read-write state control module 103 communicates with the bus protocol conversion module 102 and is used for controlling the read-write state of the on-chip FLASH memory. An OTP interface 105 communicates with the bus protocol conversion module 102 and the on-chip FLASH memory for OTP data transfer between the OTP controller and the memory cells of the on-chip FLASH memory.
In a preferred embodiment, the OTP controller further includes a caching module 104 in data communication with the on-chip FLASH memory for caching OTP data of the FLASH memory.
In a preferred embodiment, the capacity of the buffer module is equal to the capacity of a single data sector of the on-chip FLASH memory.
Specifically, in order to avoid wasting FLASH memory cells, in the embodiment of the present invention, a buffer area with a size of a single data sector block of a FLASH is added in the OTP controller to buffer OTP data. When the processor programs the sector where the OTP data is located, the read-write state control module 103 in the OTP controller reads the OTP data from the FLASH memory and writes the OTP data into the buffer module 105, then erases the FLASH sector, and then combines the data written by the processor with the buffered OTP data and writes the data into the FLASH memory, thereby maximally utilizing the address space of the memory.
In another preferred embodiment of the present invention, there is further provided an on-chip FLASH memory having an OTP controller, the on-chip FLASH memory performing read-write operations on OTP data. The on-chip FLASH memory comprises: FLASH memory cell, and OTP controller above-mentioned.
The operation principle of the on-chip FLASH memory with OTP controller according to the preferred embodiment of the invention is briefly described below. The bus protocol conversion module 102 converts the read operation of the communication bus module 101 into one or more FLASH read commands, and the read address of the bus is mapped to the internal address of the FLASH memory according to a predefined rule; the write operation of the on-chip data bus is converted into an erase command of one or more FLASH sectors, and one or more FLASH program commands. The read-write state control module 103 compares the FLASH memory internal access address from the bus protocol conversion module 102 with one or more FLASH data addresses predefined to be protected; if the access address is not the protected address, the access address is output to the FLASH memory address interface without any conversion; if the access address is one of the protected addresses, the access address is subjected to predefined transformation, such as adding a fixed offset value, and the like, and then is output to the FLASH memory.
Before performing a programming operation on the protected data address, the read-write state control module 103 reads the protected data state record from the FLASH memory predefined address of the on-chip data storage module, and generates a corresponding FLASH erase instruction and programming instruction only when the record indicates that the protected address is never programmed; if the record indicates that the protected address has been programmed, the programming operation is skipped, and the one-time programmable characteristic of the protected unit is ensured. Before erasing/programming unprotected data, checking whether the protected data is contained in the FLASH sector according to a predefined rule, if so, reading the protected data of the FLASH sector and caching the protected data in the cache module 104, then executing the erasing operation of the sector, and then sequentially writing the cached protected data and the data to be written from the bus protocol conversion module 102 into the FLASH sector.
In summary, according to the OTP controller based on the on-chip FLASH memory, the OTP controller tightly coupled with the on-chip FLASH memory is utilized to strictly read and write protect any number of memory units in any address range of the on-chip FLASH memory, so that the waste of the on-chip FLASH memory units is avoided, and the flexibility of the software and hardware design of the microcontroller and the system chip is improved.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (3)
1. An OTP controller based on an on-chip FLASH memory for controlling read-write operations of the on-chip FLASH memory, the OTP controller comprising:
the processor is used for reading and writing data of the on-chip FLASH memory and the OTP controller through the communication bus module;
the bus protocol conversion module is communicated with the communication bus module and converts the bus protocol of the communication bus module into a read-write bus protocol of the on-chip FLASH memory;
the read-write state control module is communicated with the bus protocol conversion module and is used for controlling the read-write state of the on-chip FLASH memory; and
an OTP interface which is communicated with the bus protocol conversion module and the on-chip FLASH memory and is used for transmitting OTP data between the OTP controller and a storage unit of the on-chip FLASH memory;
the read-write state control module compares the internal access address of the FLASH memory from the communication bus module with one or more predefined FLASH addresses to be protected, confirms whether the internal access address is protected, directly outputs the internal access address to an address interface of the FLASH memory when the internal access address is not the protected address, and outputs the internal access address to the address interface of the FLASH memory after predefined conversion when the internal access address is the protected address;
before data erasure or programming operation, the read-write state control module checks whether the FLASH sector to be operated contains protected data or not according to a predefined rule, if so, the protected data of the sector is read out and cached in the cache module, then the erasure operation of the sector is executed, and then the cached protected data and the data to be written from the communication bus module are sequentially written into the sector;
the read-write state control module reads the state record of the protected data from one or more FLASH addresses of the predefined address, which need to be protected, generates corresponding FLASH erasing instructions and programming instructions when the protected internal access address is not programmed, and sends the data from the communication bus module to a data interface of the FLASH memory; skipping the programming operation when the protected internal access address has been programmed;
wherein, the bus type of the communication bus module is an AXI or AHB type.
2. An on-chip FLASH memory with an OTP controller, the on-chip FLASH memory being capable of performing read-write operations of OTP data, the on-chip FLASH memory comprising:
a FLASH storage unit; and
an OTP controller, the OTP controller comprising:
the processor is used for reading and writing data of the on-chip FLASH unit and the OTP controller through the communication bus module;
the bus protocol conversion module is communicated with the communication bus module and converts the bus protocol of the communication bus module into a read-write bus protocol of the on-chip FLASH storage unit;
the read-write state control module is communicated with the bus protocol conversion module and is used for controlling the read-write state of the on-chip FLASH storage unit; and
an OTP interface which is communicated with the bus protocol conversion module and the on-chip FLASH storage unit and is used for transmitting OTP data between the OTP controller and the FLASH storage unit;
the read-write state control module compares the internal access address of the FLASH memory from the communication bus module with one or more FLASH addresses which are predefined and need to be protected, confirms whether the internal access address is protected, and when the internal access address is not the protected address, the internal access address is directly output to an address interface of the FLASH memory, and when the internal access address is the protected address, the internal access address is subjected to predefined transformation and then is output to the address interface of the FLASH memory;
before data erasure or programming operation, the read-write state control module checks whether the FLASH sector to be operated contains protected data or not according to a predefined rule, if so, the protected data of the sector is read out and cached in the cache module, then the erasure operation of the sector is executed, and then the cached protected data and the data to be written from the communication bus module are sequentially written into the sector;
the read-write state control module reads the state record of the protected data from one or more FLASH addresses of the predefined address, which need to be protected, generates corresponding FLASH erasing instructions and programming instructions when the protected internal access address is not programmed, and sends the data from the communication bus module to a data interface of the FLASH memory; skipping the programming operation when the protected internal access address has been programmed;
wherein, the bus type of the communication bus module is an AXI or AHB type.
3. A read-write control method for OTP data of an on-chip FLASH memory comprises the following steps:
OTP data input is carried out on the on-chip FLASH memory through the communication bus module;
converting the bus protocol of the communication bus module into a read-write bus protocol of an on-chip FLASH memory;
outputting the data to be written into the FLASH memory and the internal address of the FLASH memory to a read-write state control module; and
the read-write state control module determines whether to program the FLASH memory according to a control rule;
wherein the control rule includes:
the read-write state control module compares the internal access address of the FLASH memory from the communication bus module with one or more FLASH addresses which are predefined and need to be protected, confirms whether the internal access address is protected, and when the internal access address is not the protected address, the internal access address is directly output to an address interface of the FLASH memory, and when the internal access address is the protected address, the internal access address is subjected to predefined transformation and then is output to the address interface of the FLASH memory;
wherein the control rule further comprises:
before data erasing or programming operation is carried out, the read-write state control module checks whether the FLASH sector to be operated contains protected data or not according to a predefined rule, if so, the protected data of the sector is read out and cached in the cache module, then the erasing operation of the sector is executed, and then the cached protected data and the data to be written from the communication bus module are sequentially written into the sector;
the read-write state control module reads the state record of the protected data from one or more FLASH addresses of the predefined address, which need to be protected, generates corresponding FLASH erasing instructions and programming instructions when the protected internal access address is not programmed, and sends the data from the communication bus module to a data interface of the FLASH memory; skipping the programming operation when the protected internal access address has been programmed;
wherein, the bus type of the communication bus module is an AXI or AHB type.
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| CN109902035B (en) * | 2019-02-03 | 2023-10-31 | 成都皮兆永存科技有限公司 | composite memory |
| CN110399314B (en) * | 2019-06-25 | 2021-10-15 | 苏州浪潮智能科技有限公司 | CPU, electronic equipment and CPU cache control method |
| CN113035249B (en) * | 2019-12-24 | 2023-09-26 | 澜起电子科技(昆山)有限公司 | Information tamper-proof system and method |
| CN111159071B (en) * | 2019-12-31 | 2023-08-08 | 江苏科大亨芯半导体技术有限公司 | Device and method for realizing OTP (one time programmable) by eFlash memory and OTP memory |
| CN111221754A (en) * | 2020-02-24 | 2020-06-02 | 山东华芯半导体有限公司 | Storage device with read-write collision prevention function |
| CN111782288B (en) * | 2020-06-30 | 2021-11-16 | 联想(北京)有限公司 | Electronic device and control method thereof |
| CN116088948B (en) * | 2022-12-28 | 2023-08-22 | 芯动微电子科技(武汉)有限公司 | Method for in-place execution of system on chip from flash memory, electronic device and storage medium |
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