CN112130613B - Digital low dropout regulator - Google Patents
Digital low dropout regulator Download PDFInfo
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- CN112130613B CN112130613B CN202010904725.9A CN202010904725A CN112130613B CN 112130613 B CN112130613 B CN 112130613B CN 202010904725 A CN202010904725 A CN 202010904725A CN 112130613 B CN112130613 B CN 112130613B
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
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Abstract
The invention discloses a digital low dropout regulator, comprising: a synchronous control loop for adjusting the output voltage of the overshoot and the output voltage of the undershoot; the asynchronous control loop is used for performing table look-up operation to roughly adjust the output voltage of undershoot through the table look-up circuit module; the circuit module is also used for outputting a data selection signal through the finite state machine circuit module based on the change state of the output voltage so that the data selector selects one of an asynchronous transistor array control word, a synchronous transistor array control word, an all-0 transistor array control word and an all-1 transistor array control word to output to the transistor array; and the transistor array is used for controlling the conduction and the closing of each transistor according to the asynchronous transistor array control word, the synchronous transistor array control word, the all-0 transistor array control word or the all-1 transistor array control word and outputting the voltage stabilization voltage. The invention adopts a scheme of asynchronous and synchronous mixed control, and can improve the transient response speed and the adjustment precision of the digital low dropout regulator.
Description
Technical Field
The invention belongs to the technical field of voltage regulators, and particularly relates to a digital low dropout regulator.
Background
A Low Dropout Regulator (LDO) is used as a part of a power management unit in a system on chip, and plays an important role in the performance of the whole system. The traditional LDO is a simulation LDO, an output voltage obtained by feedback is compared with a reference voltage by adopting a high-gain error amplifier, and then the on-resistance of an MOS (metal oxide semiconductor) tube is adjusted to play a role in stabilizing the output voltage. The gain of the error amplifier affects the transient response speed, the tuning accuracy and the loop stability of the system. However, the supply voltage gradually drops with the continuous progress of the integrated circuit process, which makes it difficult for the error amplifier to maintain a sufficiently high gain, thereby resulting in a digital LDO.
The dynamic voltage comparator in the digital LDO replaces an error amplifier, and a plurality of small-size MOS tubes replace a single large-size power tube. The dynamic voltage comparator compares the output voltage with the reference voltage, and the bidirectional shift register controls the conduction state of the transistors in the transistor array according to the output of the dynamic voltage comparator, so that the load current is changed, and the voltage stabilizing effect is achieved.
Although the digital LDO has the advantages of low-voltage operation, insensitivity to PVT changes and convenience in process upgrade compared with the analog LDO, the existing digital LDO has some disadvantages, firstly, the transient response speed is slow, because the existing digital LDO adopts the shift register as the control core, the MOS transistor array control signal changes only when the clock edge comes, and the transient response speed is slow. Increasing the sampling clock frequency is an effective scheme for increasing the transient response speed, but the power consumption of the system where the digital LDO is located is increased, and the problem of compromise between the transient response speed and the power consumption occurs.
Disclosure of Invention
In order to improve the transient response speed and the regulation precision of the digital low dropout regulator and improve the compromise relationship between the transient response speed and the power consumption, the invention provides the digital low dropout regulator.
The technical problem to be solved by the invention is realized by the following technical scheme:
a digital low dropout voltage regulator comprising: a synchronous control loop, an asynchronous control loop, a data selector and a transistor array; wherein the content of the first and second substances,
the synchronous control loop is used for outputting a synchronous transistor array control word for adjusting the output voltage through a variable gain accumulator under the driving of a clock signal when the output voltage of the digital low dropout voltage regulator is uprushed; the synchronous transistor array control word is also used for outputting a synchronous transistor array control word for fine adjustment of the output voltage through a variable gain accumulator under the driving of the clock signal when the output voltage undershoots;
the asynchronous control loop is used for executing table look-up operation through a table look-up circuit module when the output voltage undershoots, and sending asynchronous transistor array control words corresponding to the change state of the output voltage to the data selector so that the data selector outputs the received asynchronous transistor array control words to the transistor array to realize coarse adjustment of the output voltage;
the asynchronous control loop is further used for outputting a data selection signal to the data selector through a finite state machine circuit module based on the change state of the output voltage, so that the data selector responds to the data selection signal to select the asynchronous transistor array control word, the synchronous transistor array control word, the all-0 transistor array control word and the all-1 transistor array control word to be output to the transistor array; wherein the all-1 transistor array control word and the all-0 transistor array control word correspond to a maximum value and a minimum value of the asynchronous transistor array control word, respectively;
and the transistor array is used for controlling the conduction and the closing of each transistor according to the received asynchronous transistor array control word, the synchronous transistor array control word, the all-0 transistor array control word or the all-1 transistor array control word and outputting a voltage-stabilizing voltage.
Optionally, the asynchronous control loop comprises: the asynchronous voltage comparator array, the finite state machine circuit module, the time-to-digital converter and the lookup table circuit module; wherein the content of the first and second substances,
the asynchronous voltage comparator array is used for comparing the output voltage with a multi-gear reference voltage to obtain a state signal of the output voltage; wherein, the multi-gear reference voltage comprises: vREFH2、VREFH1、VREFL1And VREFL2，VREFH2＞VREFH1＞VREFL1＞VREFL2(ii) a The ideal design value of the stabilized voltage is located at VREFL1,VREFH1]To (c) to (d);
the finite state machine circuit module is used for responding to the switching of the state signal to switch the state of the finite state machine circuit module, and outputting a pulse signal, a request signal and the data selection signal according to the state of the finite state machine circuit module; wherein the pulse signal undershoots to V at the first time of the output voltageREFL2Climb back to VREFL1After the above, is located at [ V ]REFL1,VREFH1]Effective when inside; the above-mentionedThe request signal undershoots V at the output voltage for a non-first timeREFL2Climb back to VREFL1After the above, is located at [ V ]REFL1,VREFH1]Effective when inside;
the time-to-digital converter is used for measuring the width of the pulse signal and outputting a measured value of the width of the pulse signal;
the lookup table circuit module is configured to search an asynchronous transistor array control word corresponding to the width measurement value according to a preset mapping relationship, and send the searched asynchronous transistor array control word to the variable gain accumulator and the data selector when the request signal is valid, so that the variable gain accumulator outputs a synchronous transistor array control word for fine-tuning the output voltage based on the received asynchronous transistor array control word after the data selector outputs the asynchronous transistor array control word; the mapping relation is the corresponding relation between different width measurement values of the pulse signal and asynchronous transistor array control words with different sizes.
Optionally, the synchronous control loop comprises: a dynamic voltage comparator and said variable gain accumulator; wherein the content of the first and second substances,
the dynamic voltage comparator is used for comparing the output voltage with the ideal design value and outputting a voltage regulation direction control signal according to the comparison result;
the variable gain accumulator is specifically configured to: receiving the voltage regulation direction control signal, the status signal, and the request signal; and under the driving of the clock signal, outputting a synchronous transistor array control word for adjusting the output voltage to the data selector according to the gain corresponding to the current state of the state signal and the voltage adjusting direction indicated by the voltage adjusting direction control signal and the state of the request signal.
Optionally, the synchronous control loop further includes: a limit cycle oscillation controller;
the limit cycle oscillation controller is used for receiving the state signal and the synchronous transistor array control word; detecting whether limit ring oscillation occurs in the output voltage according to the state signal and the synchronous transistor array control word under the driving of the clock signal; outputting a freeze signal to said variable gain accumulator to cause said variable gain accumulator to freeze an output synchronous transistor array control word when said limit cycle oscillation is detected; and when the output voltage is subjected to overshoot or undershoot again, the freezing signal is set to be invalid.
Optionally, the digital low dropout regulator further comprises: a load capacitance;
the upper polar plate of the load capacitor is connected with the output end of the transistor array, and the lower polar plate of the load capacitor is grounded.
Optionally, the transistor array comprises a plurality of MOS transistors; the width-length ratio of the conducting channels of the MOS tubes is distributed according to binary weight.
Optionally, the states of the finite state machine circuit module at least include: state S0, state S1, state S2, and state S3; wherein the content of the first and second substances,
the state S0 includes: the output voltage drops from steady state to VREFL2The state of the time lapse; the steady state is a state when the output voltage is stabilized at the ideal design value;
the state S1 includes: the output voltage is from VREFL2Following unsteady state up to VREFL1The state of the time lapse;
the state S2 includes: after the finite state machine circuit module is in the state S0 for the last time, the output voltage rises to V for the first timeREFL1Unsteady state of the above, and from VREFL1Above unsteady state down to VREFL2The state of the time lapse;
the state S3 includes: after the finite state machine circuit module is in the state S0 for the last time, the output voltage does not rise to V for the first timeREFL1Unsteady state of the above, and from VREFL1The above non-steady state changes to the state experienced at the steady state;
when the finite state machine circuit module is in a state S0, the data selection signal corresponds to the synchronous transistor array control word; when the finite state machine circuit module is in a state S1, the data selection signal corresponds to the all 0 transistor array control word; when the finite state machine circuit module is in a state S2, the data selection signal corresponds to the all 1 transistor array control word; when the finite state machine circuit module is in a state S3, the data selection signal corresponds to the asynchronous transistor array control word; when the FSM circuit block is not in any of state S0, state S1, state S2, and state S3, the data select signal remains unchanged.
Optionally, when the variable gain accumulator outputs the synchronous transistor array control word to the data selector, if the status signal indicates that the output voltage is at VREFH2In the above, the gain corresponding to the variable gain accumulator is 2; if the state signal indicates that the output voltage is at [ V ]REFH1,VREFH2]In between, or at [ V ]REF L1,VREF H1]In between, or at [ V ]REF L2,VREF L1]In between, or at VREFL2Hereinafter, the gain corresponding to the variable gain accumulator is 1.
The invention has the beneficial effects that:
the digital low dropout regulator provided by the invention adopts an asynchronous and synchronous mixed control mode; the asynchronous control loop executes the table look-up operation through a table look-up circuit module, and can directly output asynchronous transistor array control words corresponding to the change state of the output voltage, thereby realizing digital voltage stabilization operation under event driving, improving the transient response speed of the digital low dropout regulator, and the response delay time under the event driving mode is less influenced by the change of the supply voltage; the synchronous control loop is driven by a clock, so that the regulation precision of the digital low dropout regulator can be ensured, and a system where the digital LDO is located does not need to have higher sampling clock frequency. Therefore, the invention can improve the transient response speed and the regulation precision of the digital low dropout regulator. In addition, in the digital low dropout regulator provided by the invention, the synchronous control loop adopts the variable gain accumulator to replace the traditional fixed gain accumulator, so that the time consumed for adjusting the output voltage is reduced.
In addition, in the digital low dropout regulator provided by the invention, the limit ring oscillation controller in the synchronous control loop can eliminate the limit ring oscillation, so that the compromise relationship between the steady-state ripple and the voltage regulation precision of the digital low dropout regulator is improved.
The present invention will be described in further detail with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic structural diagram of a digital low dropout regulator according to an embodiment of the present invention;
fig. 2 is a detailed structural diagram of a digital low dropout regulator according to an embodiment of the present invention;
fig. 3 is a timing diagram of the operation of the digital low dropout regulator of fig. 2.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
In order to improve the transient response speed and the adjustment precision of the digital low dropout regulator and improve the compromise relationship between the transient response speed and the power consumption, the embodiment of the invention provides the digital low dropout regulator. As shown in fig. 1, a digital low dropout regulator according to an embodiment of the present invention may include: a synchronous control loop 10, an asynchronous control loop 20, a data selector 30, and a transistor array 40; wherein the content of the first and second substances,
Can be used forIt is understood that the synchronous control loop 10 can monitor the varying state of the output voltage, and thus, according to the output voltage VOUTIs adapted to output synchronous control words with different sizes to realize the output voltage VOUTAnd (4) regulating the voltage. Wherein the synchronous control loop 10 monitors the output voltage VOUTThere are various specific implementations of the method, and the output voltage V is subsequently monitored for the asynchronous control loop 20 for clarity of the layout of the schemeOUTAre illustrated.
In the synchronous control loop 10, the clock signal is the clock signal of the system where the digital low dropout regulator is located; the variable gain accumulator is a key device in the synchronous control loop 10 for generating a transistor array control word; compared with the traditional fixed gain accumulator, the variable gain accumulator can reduce the time consumed by the output voltage during the rising.
An asynchronous control loop 20 for providing an output voltage VOUTWhen undershoot occurs, a lookup operation is performed by a lookup table circuit module to match the output voltage VOUTSends the asynchronous transistor array control word corresponding to the changed state to the data selector 30, so that the data selector 30 outputs the received asynchronous transistor array control word to the transistor array 40 to realize coarse adjustment of the output voltage VOUT。
Wherein, the lookup table circuit module is a key module for the asynchronous control loop 20 to realize lookup operation; the lookup table circuit module may have the output voltage V pre-stored thereinOUTWhen undershoot occurs, the output voltage VOUTThe different change states of the asynchronous transistor array control word correspond to different sizes; thus, at the output voltage VOUTWhen undershoot occurs, the corresponding asynchronous transistor array control word can be directly found through the table look-up operation and output to the data selector 30.
In practical application, the lookup table circuit module can be built through a logic gate circuit, the related technology is mature, and details are not repeated in the embodiment of the invention.
The asynchronous control loop 20 is further configured to output a data selection signal to the data selector 30 through a finite state machine circuit module based on a change state of the output voltage, so that the data selector 30 selects an asynchronous transistor array control word, a synchronous transistor array control word, an all-0 control word, and an all-1 control word to be output to the transistor array 40 in response to the data selection signal; wherein, the all-1 transistor array control word and the all-0 transistor array control word respectively correspond to the maximum value and the minimum value of the asynchronous transistor array control word. In practical applications, the all 1 transistor array control word will turn off all MOS transistors in the transistor array 40, resulting in a drop in output voltage; the all 0 control word turns on all MOS transistors in the transistor array 40, causing the output voltage to rise.
It is understood that the asynchronous control loop 20 can monitor the variation state of the output voltage, so as to output different values of asynchronous transistor array control words based on different variation states of the output voltage, thereby realizing the adjustment of the output voltage. There are various specific circuit mechanisms for monitoring the output voltage by the asynchronous control loop 20, and for clarity of layout of the scheme, the specific circuit structure for monitoring the output voltage by the asynchronous control loop 20 is illustrated in the following.
In practical application, the finite state machine circuit module can be built through a logic gate circuit, all-0 transistor array control words and all-1 transistor array control words can be input by a system where the digital low dropout voltage regulator is located, related technologies are mature, and details are not repeated in the embodiment of the invention.
And the transistor array 40 is used for controlling the conduction and the closing of each transistor according to the received asynchronous transistor array control word, the synchronous transistor array control word, the all-0 control word or the all-1 control word and outputting the voltage stabilization voltage. It can be understood that the regulated voltage is the regulated output voltage.
Wherein, the transistor array 40 may include a plurality of MOS transistors; the width-to-length ratios of the conducting channels of the MOS transistors may be distributed according to binary weights.
Next, a specific circuit configuration of the asynchronous control loop 20 will be exemplified. Referring to fig. 2, the asynchronous control loop 20 may include: an asynchronous voltage comparator array 201, a finite state machine circuit module 202, a time-to-digital converter 203, and a lookup table circuit module 204; wherein the content of the first and second substances,
the asynchronous voltage comparator array 201 is used for comparing the output voltage with a multi-gear reference voltage to obtain a state signal of the output voltage; wherein, the reference voltage of many grades includes: vREFH2、VREFH1、VREFL1And VREFL2，VREFH2＞VREFH1＞VREFL1＞VREFL2(ii) a Ideal design value V of stabilized voltage of digital low dropout regulatorREFIs located at [ V ]REFL1,VREFH1]In the meantime. For example, the ideal design value VREFMay be equal to VREFL1And VREFH1The sum is divided by 2, although not limited thereto.
For example, assume that the output voltage is at VREFL2Hereinafter, the state signal output by the asynchronous voltage comparator array 201 may be 4' B1111; the output voltage is in [ V ]REFL2,VREFL1]In between, the state signal output by the asynchronous voltage comparator array 201 may be 4' B1110; the output voltage is in [ V ]REFL1，VREFH1]In between, the state signal output by the asynchronous voltage comparator array 201 may be 4' B1100; the output voltage is in [ V ]REFH1，VREFH2]In between, the state signal output by the asynchronous voltage comparator array 201 may be 4' B1000; the output voltage is at VREFH2In the above, the state signal output by the asynchronous voltage comparator array 201 may be 4' B0000.
It is understood that the asynchronous control loop 20 monitors the output voltage by comparing the state signal output by the array 201 through the asynchronous transformer.
A finite state machine circuit module 202, configured to switch its own state in response to the switching of the state signal, and output a pulse signal, a request signal, and a data selection signal according to its own state; wherein the pulse signal undershoots to V at the first time of the output voltageREFL2Climb back to VREFL1After the above, is located at [ V ]REFL1,VREFH1]Effective when inside; the request signal undershoots at the output voltage for a non-first timeVREFL2Climb back to VREFL1After the above, is located at [ V ]REFL1,VREFH1]Effective when inside.
Here, the state of the finite state machine circuit module 202 may exist in various kinds. For example, the states of the finite state machine circuit module 202 may include: state S0, state S1, state S2, and state S3.
Wherein state S0 is: the output voltage drops from steady state to VREFL2The state of the time lapse; the steady state here is a state where the output voltage is stabilized at an ideal design value.
State S1 is: output voltage from VREFL2Following unsteady state up to VREFL1The state experienced by the time.
State S2 is: after the circuit module of the self-limited state machine is in the state S0 for the last time, the output voltage rises to V for the first timeREFL1Unsteady state of the above, and from VREFL1Above unsteady state down to VREFL2The state experienced by the time.
State S3 is: after the circuit module of the self-limited state machine is in the state S0 for the last time, the output voltage does not rise to V for the first timeREFL1Unsteady state of the above, and from VREFL1The above non-steady state changes to the state experienced at the steady state.
When the finite state machine circuit module 202 is in the state S0, the data selection signal corresponds to the synchronous transistor array control word; when the finite state machine circuit module 202 is in the state S1, the data selection signal corresponds to the all 0 transistor array control word; when the finite state machine circuit module 202 is in the state S2, the data selection signal corresponds to the all 1 transistor array control word; when the finite state machine circuit module 202 is in the state S3, the data selection signal corresponds to the asynchronous transistor array control word; the data select signal remains unchanged when the finite state machine circuit module 202 is not in any of the states S0, S1, S2 and S3.
Based on the states S2 and S3, the pulse signal is valid when the finite state machine circuit module 202 is in the state S2. The request signal is valid when the finite state machine circuit module 202 is in the state S3. For a pulse signal, a high level indicates active and a low level indicates inactive, and the request signal may be set as such.
And a time-to-digital converter 203 for measuring the width of the pulse signal and outputting the measured value of the width of the pulse signal.
The lookup table circuit module 204 is configured to search an asynchronous transistor array control word corresponding to the width measurement value according to a preset mapping relationship, and send the searched asynchronous transistor array control word to the variable gain accumulator and the data selector when the request signal is valid, so that the variable gain accumulator outputs a synchronous transistor array control word for fine-tuning the output voltage based on the received asynchronous transistor array control word after the data selector outputs the asynchronous transistor array control word; the mapping relation is the corresponding relation between different width measurement values of the pulse signals and asynchronous transistor array control words with different sizes.
It can be understood that the mapping relationship stored in the lookup table circuit module 204 stores asynchronous transistor array control words of different sizes corresponding to different change states of the output voltage when the output voltage undershoots.
Therefore, the asynchronous control loop 20 executes the table lookup operation through the table lookup circuit module 204, and can directly output the asynchronous transistor array control word corresponding to the change state of the output voltage, thereby realizing the voltage stabilization operation under event driving, improving the transient response speed of the digital low dropout regulator, and the response delay time under the event driving mode is less affected by the change of the supply voltage.
Next, a specific circuit configuration of the synchronous control loop 10 will be exemplified. Referring to fig. 2, the synchronous control loop 10 may include: a dynamic voltage comparator 101 and a variable gain accumulator 102; wherein the content of the first and second substances,
and the dynamic voltage comparator 101 is used for comparing the output voltage with an ideal design value and outputting a voltage regulation direction control signal according to the comparison result.
When the output voltage is larger than an ideal design value, the voltage regulation direction control signal indicates that the output voltage needs to be reduced; when the output voltage is less than the ideal design value, the voltage regulation direction control signal indicates that the output voltage needs to be increased.
A variable gain accumulator 102 for receiving the voltage adjustment direction control signal, the status signal, and the request signal; under the driving of the clock signal, the synchronous transistor array control word for adjusting the output voltage is output to the data selector 30 according to the gain corresponding to the current state of the state signal and the voltage adjustment direction indicated by the voltage adjustment direction control signal, and according to the state of the request signal. Specifically, when the request signal is invalid, the synchronous transistor array control word output by the variable gain accumulator 102 is mainly used for adjusting the output voltage when the output voltage is in an overshoot state, and when the request signal is valid, the synchronous transistor array control word output by the variable gain accumulator 102 is mainly used for fine adjustment of the output voltage on the basis of the asynchronous transistor array control word sent by the lookup table circuit module when the output voltage is in an undershoot state. In practical applications, after receiving the request signal, the variable gain accumulator 102 may feed back a preparation signal to the finite state machine circuit module 202, where the preparation signal and the request signal are a pair of handshake signals, which when valid indicates that the variable gain accumulator 102 can load the asynchronous control word at this time. For example, when the request signal is high, the variable gain accumulator 102 loads the asynchronous transistor array control word from the lut circuit module and pulls the ready signal high; at this time, the data selector 30 selects the asynchronous transistor array control word to realize coarse adjustment of the output voltage; when the finite state machine circuit block is switched from the state S3 to the state S0, the request signal is pulled low by the finite state machine circuit block, and the ready signal is correspondingly pulled low by the variable gain accumulator 102.
It will be appreciated that the synchronous control loop 10 is driven by a clock signal, whereas the asynchronous control loop 20 is not driven by a clock signal, and data cannot be transferred directly between the two, and therefore the pair of handshake signals, set request signal and ready signal, enables the transfer of asynchronous control words.
Wherein variable gain accumulator 102 outputs synchronous crystals to data selector 30When the transistor array controls the word, if the state signal represents that the output voltage is at VREFH2In the above, the gain corresponding to the variable gain accumulator 102 is 2; if the state signal indicates that the output voltage is at [ V ]REFH1,VREFH2]In between, or at [ V ]REFL1,VREFH1]In between, or at [ V ]REFL2,VREFL1]In between, or at VREFL2Next, the gain corresponding to the variable gain accumulator 102 is 1.
It will be appreciated that the synchronous control loop 10 monitors the output voltage by receiving a status signal from the asynchronous transformer comparator array 201.
In a preferred implementation, the synchronous control loop 10 may further include a limit cycle oscillation controller 103.
The limit cycle oscillation controller 103 is used for receiving a state signal and a synchronous transistor array control word; under the drive of a clock signal, detecting whether limit ring oscillation occurs in output voltage according to a state signal and a synchronous transistor array control word; when the occurrence of limit cycle oscillation is detected, outputting a freeze signal to the variable gain accumulator 102 to cause the variable gain accumulator 102 to freeze the output synchronous transistor array control word; and, when limit cycle oscillation disappears, the freeze signal is deasserted.
Specifically, when the limit cycle oscillation controller 103 detects that the output voltage has a variation trend of "large-small-large" or "small-large-small", based on the state signal and the synchronous transistor array control word, it detects that limit cycle oscillation occurs in the output voltage, and accordingly outputs a freeze signal. When the output voltage is undershot or overshot again, the limit ring oscillation controller 103 sets the freezing signal to be invalid, and the variable gain accumulator 102 restores the size adjustment of the control word of the synchronous transistor array.
Therefore, in the digital low dropout regulator provided by the embodiment of the present invention, the limit cycle oscillation controller in the synchronous control loop 10 can eliminate the limit cycle oscillation, thereby improving the compromise relationship between the steady-state ripple and the voltage regulation precision of the digital low dropout regulator. And moreover, the variable gain accumulator is adopted to replace the traditional fixed gain accumulator, so that the adjustment time of the output voltage during the overshoot is reduced.
In addition, the digital low dropout regulator provided by the embodiment of the invention also comprises a load capacitor COUT(ii) a The upper plate of the load capacitor is connected to the output of the transistor array 40, and the lower plate is grounded.
For clarity, the operation principle of the digital low dropout regulator provided by the embodiment of the present invention is illustrated by an operation timing chart shown in fig. 3.
Starting from the leftmost side of fig. 3, when the digital low dropout regulator is in a steady state, i.e. when the output voltage is at VREFH1And VREFL1Ideal design value V betweenREFWhen the data selection signal is numbered "11", which represents the selection of the synchronous transistor array control word, the finite state machine circuit module 202 is in the state S0; accordingly, the data selector 30 shown in fig. 2 selects the synchronous transistor array control word of input No. 3.
Then, assuming a sudden increase in load current, the output voltage undershoots to less than VREFL2The finite state machine circuit module 202 enters a state S1, where the data select signal is numbered "10" and represents the selection of the all 0 transistor array control word; accordingly, the data selector 30 shown in fig. 2 selects the all 0 transistor array control word of input No. 2, and the output voltage starts to rise.
When the output voltage rises above VREFL1When the logic circuit module 202 enters a state S2, the pulse signal is set to be active at a high level by the logic circuit module 202, and the number of the data selection signal output by the logic circuit module 202 is "01", which represents that all 1 transistor array control words are selected; accordingly, the data selector 30 shown in fig. 2 selects the all 1 transistor array control word of input No. 1, and the output voltage drops again.
When the output voltage drops to less than V againREFL2At this time, the finite state machine circuit module 202 enters the state S1, the pulse signal is set to the low level and is inactive, and the number of the data selection signal outputted from the finite state machine circuit module 202 is "10", which represents that all the data selection signals are selected0 transistor array control word; accordingly, the data selector 30 shown in fig. 2 selects the all 0 transistor array control word of input No. 2, and the output voltage starts to rise.
When the output voltage rises above VREFL1When the asynchronous transistor array control word is selected, the finite state machine circuit module 202 enters a state S3, the request signal is set to be active at a high level, and the number of the data selection signal output by the finite state machine circuit module 202 is "00", which represents that the asynchronous transistor array control word is selected; the variable gain accumulator 102, upon detecting the request signal is pulled high, puts in the asynchronous transistor array control word and pulls the ready signal high. Accordingly, the data selector 30 shown in fig. 2 selects the asynchronous transistor array control word of input No. 0, and the output voltage is adjusted to the ideal design value; at this point, the finite state machine circuit module 202 enters state S0, pulling the request signal low and the variable gain accumulator 102 correspondingly pulls the ready signal low.
In addition, when the output voltage is in an overshoot state, or the up-and-down variation of the output voltage is not enough to trigger the state switching of the finite state machine circuit module 202, the adjustment of the output voltage is controlled by the synchronous voltage control output by the synchronous control loop 10. For the content of the voltage adjustment direction and the adjustment gain when the synchronous control loop 10 adjusts the output voltage, reference may be made to the above description of the synchronous control loop 10, and details are not repeated here.
It is noted that while the present application has been described herein with respect to various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (8)
1. A digital low dropout voltage regulator, comprising: a synchronous control loop, an asynchronous control loop, a data selector and a transistor array; wherein the content of the first and second substances,
the synchronous control loop is used for outputting a synchronous transistor array control word for adjusting the output voltage through a variable gain accumulator under the driving of a clock signal when the output voltage of the digital low dropout voltage regulator is uprushed; the synchronous transistor array control word is also used for outputting a synchronous transistor array control word for fine adjustment of the output voltage through a variable gain accumulator under the driving of the clock signal when the output voltage undershoots;
the asynchronous control loop is used for executing table look-up operation through a table look-up circuit module when the output voltage undershoots, and sending asynchronous transistor array control words corresponding to the change state of the output voltage to the data selector so that the data selector outputs the received asynchronous transistor array control words to the transistor array to realize coarse adjustment of the output voltage;
the asynchronous control loop is further used for outputting a data selection signal to the data selector through a finite state machine circuit module based on the change state of the output voltage, so that the data selector responds to the data selection signal to select the asynchronous transistor array control word, the synchronous transistor array control word, the all-0 transistor array control word and the all-1 transistor array control word to be output to the transistor array; wherein the all-1 transistor array control word and the all-0 transistor array control word correspond to a maximum value and a minimum value of the asynchronous transistor array control word, respectively;
and the transistor array is used for controlling the conduction and the closing of each transistor according to the received asynchronous transistor array control word, the synchronous transistor array control word, the all-0 transistor array control word or the all-1 transistor array control word and outputting a voltage-stabilizing voltage.
2. The digital low dropout regulator of claim 1,
the asynchronous control loop comprises: the asynchronous voltage comparator array, the finite state machine circuit module, the time-to-digital converter and the lookup table circuit module; wherein the content of the first and second substances,
the asynchronous voltage comparator array is used for comparing the output voltage with a multi-gear reference voltage to obtain a state signal of the output voltage; wherein, the multi-gear reference voltage comprises: vREFH2、VREFH1、VREFL1And VREFL2，VREFH2＞VREFH1＞VREFL1＞VREFL2(ii) a The ideal design value of the stabilized voltage is located at VREFL1,VREFH1]To (c) to (d);
the finite state machine circuit module is used for responding to the switching of the state signal to switch the state of the finite state machine circuit module, and outputting a pulse signal, a request signal and the data selection signal according to the state of the finite state machine circuit module; wherein the pulse signal undershoots to V at the first time of the output voltageREFL2Climb back to VREFL1After the above, is located at [ V ]REFL1,VREFH1]Effective when inside; the request signal undershoots to V at the output voltage for a non-first timeREFL2Climb back to VREFL1After the above, is located at [ V ]REFL1,VREFH1]Effective when inside;
the time-to-digital converter is used for measuring the width of the pulse signal and outputting a measured value of the width of the pulse signal;
the lookup table circuit module is configured to search an asynchronous transistor array control word corresponding to the width measurement value according to a preset mapping relationship, and send the searched asynchronous transistor array control word to the variable gain accumulator and the data selector when the request signal is valid, so that the variable gain accumulator outputs a synchronous transistor array control word for fine-tuning the output voltage based on the received asynchronous transistor array control word after the data selector outputs the asynchronous transistor array control word; the mapping relation is the corresponding relation between different width measurement values of the pulse signal and asynchronous transistor array control words with different sizes.
3. The digital low dropout regulator of claim 2, wherein the synchronous control loop comprises: a dynamic voltage comparator and said variable gain accumulator; wherein the content of the first and second substances,
the dynamic voltage comparator is used for comparing the output voltage with the ideal design value and outputting a voltage regulation direction control signal according to the comparison result;
the variable gain accumulator is specifically configured to: receiving the voltage regulation direction control signal, the status signal, and the request signal; and under the driving of the clock signal, outputting a synchronous transistor array control word for adjusting the output voltage to the data selector according to the gain corresponding to the current state of the state signal and the voltage adjusting direction indicated by the voltage adjusting direction control signal and the state of the request signal.
4. The digital low dropout regulator of claim 3, wherein the synchronous control loop further comprises: a limit cycle oscillation controller;
the limit cycle oscillation controller is used for receiving the state signal and the synchronous transistor array control word; detecting whether limit ring oscillation occurs in the output voltage according to the state signal and the synchronous transistor array control word under the driving of the clock signal; outputting a freeze signal to said variable gain accumulator to cause said variable gain accumulator to freeze an output synchronous transistor array control word when said limit cycle oscillation is detected; and when the output voltage is undershot or overshot again, setting the freezing signal to be invalid.
5. The digital low dropout regulator of claim 4, further comprising: a load capacitance;
the upper polar plate of the load capacitor is connected with the output end of the transistor array, and the lower polar plate of the load capacitor is grounded.
6. The digital low dropout regulator of claim 5, wherein the transistor array comprises a plurality of MOS transistors; the width-length ratio of the conducting channels of the MOS tubes is distributed according to binary weight.
7. The digital low dropout regulator of claim 4, wherein the state of the finite state machine circuit module comprises at least: state S0, state S1, state S2, and state S3; wherein the content of the first and second substances,
the state S0 includes: the output voltage drops from steady state to VREFL2The state of the time lapse; the steady state is a state when the output voltage is stabilized at the ideal design value;
the state S1 includes: the output voltage is from VREFL2Following unsteady state up to VREFL1The state of the time lapse;
the state S2 includes: after the finite state machine circuit module is in the state S0 for the last time, the output voltage rises to V for the first timeREFL1Unsteady state of the above, and from VREFL1Above unsteady state down to VREFL2The state of the time lapse;
the state S3 includes: after the finite state machine circuit module is in the state S0 for the last time, the output voltage does not rise to V for the first timeREFL1Unsteady state of the above, and from VREFL1The above non-steady state changes to the state experienced at the steady state;
when the finite state machine circuit module is in a state S0, the data selection signal corresponds to the synchronous transistor array control word; when the finite state machine circuit module is in a state S1, the data selection signal corresponds to the all 0 transistor array control word; when the finite state machine circuit module is in a state S2, the data selection signal corresponds to the all 1 transistor array control word; when the finite state machine circuit module is in a state S3, the data selection signal corresponds to the asynchronous transistor array control word; when the FSM circuit block is not in any of state S0, state S1, state S2, and state S3, the data select signal remains unchanged.
8. The digital low dropout regulator of claim 7 wherein the variable gain accumulator outputs the synchronous transistor array control word to the data selector if the status signal indicates that the output voltage is at VREFH2In the above, the gain corresponding to the variable gain accumulator is 2; if the state signal indicates that the output voltage is at [ V ]REFH1,VREFH2]In between, or at [ V ]REFL1,VREFH1]In between, or at [ V ]REFL2,VREFL1]In between, or at VREFL2Hereinafter, the gain corresponding to the variable gain accumulator is 1.
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