WO2018001328A1

WO2018001328A1 - Power regulation device and method, chip system and method for operating chip system

Info

Publication number: WO2018001328A1
Application number: PCT/CN2017/090876
Authority: WO
Inventors: 毕杰
Original assignee: 中兴通讯股份有限公司
Priority date: 2016-06-30
Filing date: 2017-06-29
Publication date: 2018-01-04
Also published as: CN107565813A

Abstract

A power regulation device and method, chip system and method for operating the chip system. The power regulation device comprises a controller (21) and a digital-to-analog converter (22). The controller converts a voltage adjustment quantity fed back by a load chip (33) into a digital feedback voltage signal adapted to a power chip (31), and outputs the same to the digital-to-analog converter; the digital-to-analog converter converts the digital feedback voltage signal into an analog feedback voltage signal, and outputs the same to a power chip so as to regulate supply voltage. The power regulation device can be used to implement an adaptive supply voltage regulation function, thereby reducing the power consumption of a load chip.

Description

Power adjustment device and method, chip system and method for operating chip system

Technical field

This document relates to, but is not limited to, the field of integrated circuit technology, and in particular, to a power supply adjusting device and method, a chip system, and a method for operating a chip system.

Background technique

At present, reducing device power consumption has become one of the main goals of communication device design. AVS (adaptive voltage scaling) is a technology that effectively reduces the power consumption of chips in network devices. AVS is based on the performance change of the tracking system load chip, and adaptive voltage adjustment is made by APC (Automatic Power Control). APC accurately transmits the performance (frequency) and temperature change of the system load chip to the external power management unit through PWI (Power Indication). The power management unit automatically adjusts the voltage supplied to the system load chip according to performance requirements to make the load The chip operates at the lowest voltage and frequency that ensures the application software is operating correctly, reducing chip power consumption.

Referring to FIG. 1 , FIG. 1 is a schematic block diagram of an AVS power supply adjusting device, which includes a CPU chip, and the CPU chip includes an HPM (Hardware Performance Monitor), a CMU (Clock Master Unit), and an APC. The APC is connected to a DC-DC DC-DC power chip external to the power conditioning device, and the DC-DC power chip includes a PMU (Phasor Measurement Unit); when the CMU requests a new frequency for a new working state, and When setting a new HPM clock for this working state, APC first determines the open-loop adjustment voltage required by the load chip according to the new frequency requirement, and initializes the CPU core power supply through the DC-DC power supply chip. After the initial adjustment is completed, the CPU runs at the new frequency. At this time, the APC uses the internal parameters of the CPU monitored by the HPM to determine the adjustment voltage required by the load chip again until the new frequency is met. However, when the voltage of the load chip is adjusted, the AVS power supply adjusting device needs to adopt a specific power chip to realize voltage regulation. The PMU needs to be set inside the power chip to implement the AVS function, resulting in a common power chip that does not contain the power control unit. The voltage of the load chip cannot be adjusted, which reduces the versatility of the AVS power supply adjustment device and also increases Added cost.

Summary of the invention

The following is an overview of the topics detailed in this document. This Summary is not intended to limit the scope of the claims.

Embodiments of the present invention provide a power supply adjusting device and method, a chip system, and a method for operating a chip system, which can improve the versatility of the power adjusting device.

Embodiments of the present invention provide a power adjustment device including: a controller and a digital to analog converter;

The controller is configured to convert a voltage adjustment amount fed back by the load chip into a digital feedback voltage signal adapted to the power chip and output to the digital-to-analog converter;

The digital to analog converter is configured to convert the digital feedback voltage signal into an analog feedback voltage signal and output to a power chip to adjust a power supply voltage.

An embodiment of the present invention further provides a chip system, including: a power chip, a load chip, and a power adjustment device as described above;

The power chip is configured to supply a voltage to the load chip;

The power adjustment device is configured to convert a voltage adjustment amount fed back by the load chip into an analog feedback voltage signal matched with the power chip and output the signal to the power chip;

The power chip adjusts the power voltage according to the analog feedback voltage signal.

The embodiment of the invention further provides a power supply adjustment method, including:

Converting the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal adapted to the power chip;

The digital feedback voltage signal is converted into an analog feedback voltage signal and output to a power chip to adjust the power supply voltage.

The embodiment of the invention further provides a method for operating a chip system, comprising:

The power chip supplies voltage to the load chip;

Converting, by the power adjustment device as described above, the voltage adjustment amount fed back by the load chip into an analog feedback voltage signal adapted to the power chip;

The beneficial effects of the embodiments of the present invention are:

A power supply adjusting apparatus and method, a chip system, and a method for operating a chip system according to an embodiment of the present invention include a controller and a digital-to-analog converter, and the controller converts a voltage adjustment amount fed back by the load chip into a number adapted to the power chip. The feedback voltage signal is output to a digital-to-analog converter, and the digital-to-analog converter converts the digital feedback voltage signal into an analog feedback voltage signal and outputs it to the power chip to adjust the power supply voltage, thereby implementing an adaptive power supply voltage adjustment function and reducing the load chip. Power consumption. At the same time, the power adjustment device converts the voltage adjustment output of the load chip into an analog signal that the power chip can support, so that the power chip can realize the adaptive voltage adjustment function of the load chip by using an ordinary power converter, thereby reducing the cost. At the same time, it also increases the versatility of the power supply adjustment device.

Other aspects will be apparent upon reading and understanding the drawings and detailed description.

BRIEF abstract

Figure 1 is a block diagram of the AVS power supply adjustment device;

2 is a schematic diagram of a power adjustment device according to Embodiment 1 of the present invention;

3 is a schematic diagram of a chip system according to Embodiment 2 of the present invention;

4 is a schematic diagram of a power adjustment device according to Embodiment 3 of the present invention;

FIG. 5 is a schematic diagram of a chip system according to Embodiment 3 of the present invention; FIG.

6 is a flowchart of adjusting an AVS power supply according to Embodiment 4 of the present invention;

FIG. 7 is a flowchart of a method for adjusting a power supply according to an embodiment of the present invention;

FIG. 8 is a flowchart of a method for operating a chip system according to an embodiment of the present invention.

Embodiments of the invention

The embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

Embodiment 1

The embodiment of the present invention provides a power supply adjusting device, please refer to FIG. 2, FIG. 2 is a schematic diagram of a power adjusting device according to an embodiment, the power adjusting device includes a controller 21 and a digital-to-analog converter 22; The controller 21 is configured to convert the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal adapted to the power chip and output to the digital-to-analog converter 22, and the digital-to-analog converter 22 is configured to convert the digital feedback voltage signal into analog feedback. The voltage signal is output to the power chip to adjust the power supply voltage. Through the power adjustment device provided in this embodiment, the load chip can perform adaptive power supply voltage regulation through an ordinary power chip, so that the load chip can work normally at the minimum voltage required, thereby effectively reducing power consumption of the power source.

In this embodiment, the voltage adjustment amount fed back by the load chip is converted into an analog feedback voltage signal matched by the power chip, so that the power chip can adopt a general-purpose DC-DC power converter, and the power converter can be used for various types of loads. The chip provides voltage and dynamically adjusts the voltage of various types of load chips, so that the core power (core power) required by the load chip can be accurately adjusted to the minimum voltage required for the load chip to work normally, thereby reducing the power consumption of the chip. At the same time, since various types of load chips have their own definitions for the PWI bus interface for controlling the external power conversion circuit, for example, the intel processor chip has two parallel bus interfaces VID and serial bus interface SVID for the PWI bus interface. The definition is such that the voltage adjustment between the processor chip and the power chip can be performed through the matching PWI bus interface, which greatly reduces the versatility of the power adjustment device and increases the cost. The power adjustment device can convert the voltage adjustment amount fed back by the processor into an analog feedback voltage signal suitable for the general power chip to implement the AVS function, thereby improving the versatility of the entire power adjustment device and implementing the AVS of the processor chip at a lower cost. Power adjustment function.

Optionally, when the controller 21 converts the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal matched with the power chip, the controller can obtain digital feedback by directly decoding or by looking up the table through a LUT (lookup table). Voltage signal. When the voltage adjustment amount is a voltage difference, and the voltage difference is a m bit feedback voltage signal, the m bit feedback voltage signal is directly converted into an n bit feedback voltage signal by decoding or table lookup, the n bit feedback The voltage signal is a digital feedback voltage signal; when the voltage adjustment amount is the target voltage value, the target voltage value is an m bit feedback voltage signal, and the controller 21 can convert the m bit feedback voltage signal by decoding or looking up the table. The n bit feedback voltage signal is a voltage difference signal.

In the LUT table, the voltage values before and after the conversion, that is, the correspondence between the m-bit voltage value and the n-bit voltage value, or the m-bit voltage difference and the n-bit voltage difference, or even the m-bit voltage are included. The correspondence between the value and the n-bit voltage difference, the LUT table is information stored according to the voltage state of the load chip. When the m-bit feedback voltage signal fed back to the controller 21 by the load chip does not have a necessary logical relationship with the n-bit feedback voltage signal, the corresponding n-bit feedback voltage signal is queried through the LUT table stored in the memory 23; when the m-bit feedback voltage signal When there is a logic relationship with the n bit feedback voltage signal, the n bit feedback voltage signal can be directly decoded by the decoder 212. That is, when the n-bit feedback voltage signal cannot be directly decoded, the signal can be searched from the LUT table, or can be directly translated by the decoder 212 when the corresponding n-bit feedback voltage signal is not found in the LUT table. code.

Optionally, the controller 21 includes a bus interface unit 211 and a decoder 212. The bus interface unit 211 is configured to receive a voltage adjustment amount fed back by the load chip and output to the decoder 212, and the decoder 212 is set to the voltage. The adjustment amount is decoded to obtain the digital feedback voltage signal, and the digital feedback voltage signal is output to the digital-to-analog converter 22. Further, the power supply adjusting device further includes a memory 23 in which a lookup table is stored, and a digital feedback voltage signal corresponding to the voltage adjustment amount is found through a lookup table and output to the digital to analog converter 22.

Optionally, the bus interface unit 211 is configured to receive the voltage adjustment amount fed back by the load chip, and send the voltage adjustment amount to the decoder 212, and the decoder 212 is configured to convert the voltage adjustment amount into a number adapted to the power chip. The voltage signal is fed back and output to the digital to analog converter 22. The digital feedback voltage signal is the aforementioned n bit feedback voltage signal. Optionally, the bus interface unit 211 is configured to receive the voltage adjustment amount in the PWI bus format and parse the m bit feedback voltage signal; the decoder 212 is configured to convert the m bit feedback voltage signal into an n bit feedback voltage signal. The PWI bus format includes a serial bus format and a parallel bus format. Correspondingly, the PWI bus interface includes a serial bus interface and a parallel bus interface, and the serial bus interface such as a commonly used SMBUS (System Management Bus), parallel. The bus interface can be an m-bit parallel bus interface, such as the processor's programmable general-purpose IO pin GPIO (General Purpose Input Output) [1:m].

The bus interface unit 211 of the controller 21 is provided with at least one power management bus interface. Of course, a plurality of PWI bus interfaces can also be provided externally, and different interfaces can be adapted to different load chips. When the PWI bus interface includes at least two, the load chip selects one of the at least two power management bus interfaces that meets the requirements and is connected to the controller 21. Optionally, the load chip selects a PWI bus interface that is adapted to itself from the bus interface unit 211 and is connected to the controller 21. By setting A plurality of types of PWI bus interfaces enable different types of load chips to convert signals into signals compatible with a common power chip by using the power conversion device provided in this embodiment, thereby implementing the AVS function. Even if a plurality of chips of different PWI bus interfaces exist on a single board in the network device, the voltage of the chip can be adjusted by the power conversion device provided in this embodiment, thereby avoiding an increase in the material type of the power chip circuit, which is disadvantageous to the board. Cost control and board generation control, while using the same type of universal power chip can reduce the board area as much as possible in circuit design.

The controller 21 is configured to convert the m-bit feedback voltage signal into an n-bit feedback voltage signal, and then quickly convert the n-bit feedback voltage signal into an analog feedback voltage signal through a high-precision DAC (digital-to-analog converter 22) of the power conversion device. The Vdac is output, and the Vdac is fed back to the Vsensep pin of the power chip for AVS voltage regulation.

Optionally, the power adjusting device further includes a resistor unit 24 configured to provide a power negative feedback path for the analog feedback voltage signal output by the digital-to-analog converter 22, and output the analog feedback voltage signal to the power chip.

Optionally, the resistor unit 24 is mainly configured to provide a negative feedback path for the analog feedback voltage signal output by the digital-to-analog converter 22, and output the analog feedback voltage signal to the power chip. In addition, the resistor unit 24 is also provided to provide a filtering function for the analog feedback voltage, so that the analog feedback voltage is more stable, thereby helping the entire system to achieve stable AVS power supply adjustment.

It should be understood that some devices inside the power adjustment device can also implement the operations performed by the power adjustment device by using a programmable logic chip or an integrated circuit well known in the art in a pure hardware or hardware chip with software, and are compatible with different types of load chips. Required PWI (Power Indication) bus interface.

Optionally, the power adjustment device provided in this embodiment further includes a control switch (the switch S1 in the figure), and the control switch is configured to control the working state of the power adjustment device according to the control signal sent by the load chip, that is, the load chip can pass through the status interface. The power adjustment device sends a control signal to control the operating state of the power adjustment device.

Optionally, in order to prevent the load chip from driving the PWI bus interface to perform AVS voltage regulation when the AVS control function has not been started, the load chip outputs a PWI status control signal to the controller 21 in the power adjustment device, and when the signal is invalid, the controller 21 Set to turn off S1 by this control signal, from The output of the analog feedback voltage signal is turned off; when the signal is valid, the controller 21 is set to turn on S1 by the control signal, thereby turning on the output of the analog feedback voltage signal. The S1 switch is disposed between the output end of the digital-to-analog converter 22 and the input end of the resistor unit 24, and the S1 switch is the above-mentioned control switch.

The power supply adjusting device provided in this embodiment enables the AVS voltage adjustment function of the load chip to be implemented at a lower cost by using a common power chip. At the same time, since different load chips can pass the power adjusting device provided in this embodiment. The output voltage adjustment amount is converted to obtain an analog feedback voltage signal applicable to the universal power chip, so that various types of load chips can adopt an ordinary power chip, which greatly improves the versatility of the power adjustment device and also effectively controls The material cost of the single-board power chip is smaller than the occupied area of the power chip on the circuit board.

Embodiment 2

This embodiment provides a chip system based on the first embodiment. Referring to FIG. 3, FIG. 3 is a schematic diagram of a chip system according to the embodiment. The chip system includes a power chip 31, a load chip 33, and the first embodiment. For the detailed description of the power supply adjustment device, refer to the relevant part of the first embodiment, and the detailed description of the embodiment will not be repeated.

In the chip system, the power chip 31 is arranged to supply a voltage to the load chip 33, and the power adjusting device 32 is arranged to convert the voltage adjustment amount fed back from the load chip 33 into an analog feedback voltage signal adapted to the power chip 31 and output it to the power chip. 31. The power chip 31 adjusts the power supply voltage according to the analog feedback voltage signal, thereby implementing the AVS voltage regulation function.

Optionally, the foregoing load chip 33 may use a processor chip with HPM (Hardware Performance Monitor) or a programmable chip that can implement HPM functions, such as an FPGA, etc., which can be implemented by HPM or HPM function. The programming chip monitors the performance parameters of the load chip 33 and calculates the voltage adjustment amount based on the monitored performance parameters. After the power supply voltage regulation is completed and stabilized for one time, the HPM inside the load chip 33 or the programmable chip capable of implementing the HPM function will continue to monitor the internal temperature of the load chip 33 or the circuit delay condition. If the target value is not reached, the power supply adjusting device is passed. The power supply feedback network formed by the power chip 31 and the load chip 33 repeatedly and repeatedly fine-tunes the power supply voltage until the target value range requirement is met, thereby realizing the AVS power supply dynamic adjustment function.

The power chip 31 can utilize a common low-voltage high-current DC-DC power chip (DC-DC power supply) The conversion module) implements the AVS function. The DC-DC power supply chip has a remote compensation function, and is internally provided with a CMP (voltage comparator) unit. The input end of the CMP unit Vsensep is connected to the input end of the power chip Vsensep. The Vsensep pin of the power chip performs feedback compensation on the voltage adjustment output of the load chip 33, thereby implementing an adaptive voltage adjustment function. It should be understood that the power chip 31 provided in this embodiment is only used to explain the present invention, and other common power chips having low current and large current characteristics, which are well known to those skilled in the art, may be used, which is not limited thereto.

For other load chips (such as processor chips or programmable chips) that do not have a dedicated AVS module, the dynamic voltage regulation function similar to AVS cannot be implemented. For this reason, the power supply adjustment device provided in this embodiment does not contain a dedicated power supply through the power feedback network. The voltage adjustment amount of the processor chip or the programmable chip output of the AVS module is fed back to the power chip 31, and the voltage adjustment is repeatedly performed continuously, thereby realizing dynamic adjustment of the AVS power supply. The power feedback network mainly includes a power adjustment device 32. The power adjustment device 32 is configured to convert a voltage adjustment amount of a processor chip or a programmable chip output that does not include a dedicated AVS module to obtain an analog feedback voltage signal, and simulate the simulation. The feedback voltage signal is fed back to the power chip 31, and the power supply voltage is adjusted by the power chip 31, so that the voltage required by the load chip is accurately adjusted to the minimum voltage required for the load chip to work normally, and the power consumption is effectively reduced.

Optionally, the load chip 33 is configured to calculate a voltage adjustment amount by hardware or software according to the monitored internal performance parameter, or obtain a voltage adjustment amount by looking up a table. For the hardware mode, a special integrated circuit can be used, such as a decoder, or the chip internally uses a target voltage value (pre-stored voltage value) directly soldered on the chip circuit board, and directly reads the soldered when the voltage adjustment amount is acquired. Target voltage value, this method is suitable for obtaining the target voltage value; for software mode, the voltage adjustment amount can be obtained by looking up the table, the table includes the correspondence relationship between the chip parameter and the voltage, such as a specific frequency, temperature or process and target voltage Correspondence.

The obtained voltage adjustment amount may be a target voltage value or a voltage difference value. When the target voltage value is obtained, the above direct soldering method may be adopted, and of course, software or other hardware may be used. When the voltage difference is obtained, the difference between the obtained target voltage value and the actual voltage value is obtained, and the voltage difference value is obtained. When the number of voltages adjusted by the chip is large, the conversion efficiency can be improved by the voltage difference, and the voltage regulation efficiency is also increased accordingly; when the number of voltages adjusted by the chip is small, the target voltage value or The voltage difference can be any, and this will not be limited. In addition, when at least one of the internal performance parameters of the chip (such as clock frequency, power supply voltage, temperature, silicon aging, process offset) changes, the chip acquires a new target voltage value as a voltage adjustment amount by looking up the table. Alternatively, the voltage difference obtained by making the difference between the target voltage value and the actual voltage value is used as the voltage adjustment amount and is regulated by the power source chip 31.

Optionally, the power adjustment device 32 in the chip system is provided with at least two power management bus interfaces, and the load chip 33 is configured to select one of the at least two power management bus interfaces to meet the requirement and connect to the power adjustment device 32, thereby It is ensured that each type of load chip 33 can perform AVS voltage adjustment by the power supply adjusting device 32 provided in this embodiment.

Optionally, in order to prevent the load chip 33 from driving the PWI bus interface to perform AVS voltage regulation when the AVS control function has not been activated, the load chip 33 is configured to send a control signal to the power adjustment device 32 through the control interface to control the working state of the power adjustment device 32. . Optionally, the load chip 33 outputs a PWI status control signal to the controller in the power adjustment device 32. When the signal is invalid, the power adjustment device 32 is configured to turn off the S1 by the control signal, thereby turning off the output of the analog feedback voltage signal. When the signal is active, the power adjustment device 32 is set to turn on S1 by the control signal, thereby turning on the output of the analog feedback voltage signal.

Through the chip system provided in this embodiment, different types of load chips can implement the AVS voltage adjustment function by using a common power chip (ie, a DC-DC power converter), and at the same time, the power feedback network of the chip system can enable The load chip with the AVS module also implements the AVS function, thereby accurately adjusting the voltage required by the load chip to the minimum voltage required for the load chip to operate normally, and effectively reducing the power consumption of the power supply.

Embodiment 3

Optionally, FIG. 4 is a schematic diagram of a power adjustment device according to the embodiment. The power adjustment device includes a controller 41, a digital-to-analog converter 42, a memory 43, a resistor unit 44, and a control switch 45 (ie, S1). ). The controller 41 is connected to the digital-to-analog converter 42 having a bit width of n; the controller 41 is connected to the processor via a PWI bus interface PWI0status, through which the processor controls the state of the controller 41, the controller 41 is connected to the control switch 45 to control the on and off of S1, and S1 is provided between the digital to analog converter 42 and the resistance unit 44. In addition, the memory 43 stores a LUT lookup table, and the voltage adjustment amount fed back by the processor is converted by the LUT table. Of course, the bus interface unit 411 and the n-m decoder 412 are provided inside the controller 41, and the bus interface is single. The element 411 is configured to receive the voltage adjustment amount fed back by the load chip, and to analyze the voltage adjustment amount of the m bit, and the decoder 412 is configured to decode the voltage adjustment amount of the m bit to obtain an n-bit digital feedback voltage signal. For details, refer to the related content in the first embodiment, and details are not described herein again. Through the control switch 45 in FIG. 4, it is possible to prevent the processor from driving the PWI interface to perform AVS voltage regulation when the AVS control function has not been activated; the processor only needs to output the PWI0status control signal to the controller 41, and when the signal is invalid, the controller 41 The control switch 45 is turned off by the control signal, thereby turning off the output of the feedback voltage; when the signal is valid, the controller 41 turns on the control switch 45 by the control signal, thereby turning on the output of the analog feedback voltage signal.

Optionally, FIG. 5 is a schematic diagram of a chip system according to the embodiment. In FIG. 5, the DC-DC power converter 51, the power adjustment device 52, the processor 53, and the power filter 54 are included. The power adjustment device 52 includes a controller 521, a digital-to-analog converter 522, a resistance module 523, and a control switch 524. The DC-DC power conversion module 51 is internally provided with a CMP unit, and the output of the DC-DC power conversion module is realized by the CMP unit. Voltage adjustment; the processor 53 includes a hardware performance monitor 531, the performance parameter of the processor 53 is monitored by the hardware performance monitor 531, and the voltage adjustment amount is calculated according to the monitoring result; the resistance module 523 includes a first resistor R1, a second The resistor R2 and the feedback resistor Rdac are provided with a capacitor Cdac for filtering between the feedback resistor Rdac and the ground; and the feedback voltage output from the power adjusting device 52 to the DC-DC power conversion module 51 is Vdac.

Optionally, the output of the CMP unit is connected to the input of the power filter 54, the output of the power filter 54 is connected to the Vdd_core of the processor 53 (the core power of the processor); the Vdd_sense+ pin of the processor 53 and the CMP The Vsensep interface of the unit is connected, the Vdd_sense interface of the processor 53 is connected and grounded to the Vsensen interface of the CMP unit, the PWI bus interface PWI_status of the processor 53 is connected to the input of the controller 521, and the PWI bus interface PWI_core0 of the processor 53 is controlled. The PWI0 interface of the 521 is connected; the output of the digital-to-analog converter 522 is connected between the feedback resistor Rdac and the capacitor Cdac, and the resistor Rdac is connected between the capacitor Cdac and the first resistor R1, the first resistor R1, the second resistor R2, and One end of the feedback resistor Rdac is commonly connected to the Vsensep interface, and the second resistor R2 is connected between the Vdd_sense interface of the processor 53 and the Vsensep interface of the CMP unit. The first resistor R1 is connected to the Vdd_sense+ interface of the processor 53 and the CMP unit. Between the Vsensep interfaces. It should be understood that the PWI bus interface of the processor 53 The PWI_status control signal may be a fixed pin signal of the processor 53 or a general programmable pin such as GPIO; in addition, the DC-DC power converter 51 of FIG. 5 has a remote compensation function, and is generally far away. For the power chip Vsensep interface of the end compensation function, the remote compensation feedback voltage interface includes Vsensep and Vsensen, and Vsensen is generally connected and grounded to the Vdd_sense- of the processor 53, wherein the Vdd_sense- can be internal to the processor 53, the DC-DC power supply. Any one of the internal and external networks of the converter 51 is grounded; the Vsensep interface can be regarded as the inverting end of the comparator in the DC-DC power converter 51 as shown in FIG. 5 (ie, the "-" end in the figure. And the in-phase termination of the comparator is connected to the internal reference voltage Vref of the DC-DC power converter 51, which is often a fixed voltage value.

In the chip system, the DC-DC power converter 51 filters through the power source filter 54, outputs the filtered output voltage Vacs to the processor 53, supplies power to the core power supply Vdd_core of the CPU, and the processor 53 is set to pass the hardware performance monitor. The performance parameter of 531 and the output voltage Vavs calculate the voltage adjustment amount, and output the voltage adjustment amount to the controller 521 through the PWI bus interface in the PWI bus format, and the controller 521 is configured to parse out the m bit from the voltage adjustment amount ( Transmitting the voltage signal, then converting the m bit feedback voltage signal into an n bit feedback voltage signal, converting the n bit feedback voltage signal into an analog feedback voltage signal through the digital to analog converter 522 and outputting it to the DC-DC power converter 51, The DC-DC power converter 51 is arranged to adjust the power supply voltage by the CMP unit to implement the AVS voltage regulating function. Optionally, if the AVS voltage regulation precision required by the processor 53 is high or the range of the power supply voltage adjustment is required to be wide, the m bit feedback voltage signal fed back by the processor 53 has a wide number of bits, and the corresponding n bit feedback voltage signal The number of bits is also wide. In addition, in order to prevent the processor 53 from driving the PWI bus interface to perform AVS voltage regulation when the AVS control function has not been activated, the processor 53 is arranged to output a PWI status control signal to the controller 521, and when the signal is invalid, the control controller 521 interrupts Vdac. Output.

Optionally, for the power feedback network in FIG. 5, when the output voltage of the DC-DC power converter 51 is in a steady state after being adjusted by the AVS, the CMP unit inside the DC-DC power converter 51 can be considered to be in a negative feedback state. And within the power supply adjustment range, the CMP unit is in the linear amplification working area, so the Vsensep pin voltage is approximately equal to Vref. For the Vsensep pin node, the following formula can be derived using Kirchhoff's law:

It can be known from the formula (1) that Vdac is a negative feedback voltage for the Vavs output, that is, the Vavs output from the power chip 51 decreases as Vdac increases. Therefore, the VAVs output can be reduced by feedback of different Vdac voltages to achieve AVS voltage regulation; in addition, Vavs is composed of (1+R1/R2)*Vref and (R1/Rdac)*(Vref-Vdac), the former A fixed value, the latter being the feedback voltage portion. When the controller 521 has no output, S1 is turned off in FIG. 5, and Vref=Vdac, that is, the second term of the above formula is 0, and Vavs at this time is determined by the first item. This case is applicable to the case where the power chip 51 is just powered on and the processor 53 has not started the AVS voltage regulating function. At this time, the PWI status in FIG. 5 is invalid, and the first item Vstart=(1+R1/R2)*Vref is defined. This voltage determines the startup voltage at which the processor 53 is powered up.

According to formula (1), the AVS power supply voltage adjustment process of the chip system is as follows:

Immediately after power-on, the DC-DC power converter 51 outputs the Vavs voltage to supply the core power (and Vdd core) of the processor 53. At this time, Vavs=Vstart, the voltage value is from the internal Vref of the power chip 51 and the ratio of R1 and R2. determine. The HPM hardware performance monitor 531 inside the processor 53 begins to operate when the processor 53 core is functioning properly. When the HPM detects a temperature anomaly or the internal circuit delay of the chip is significantly lower or higher than the target delay, the AVS voltage regulation requirement will be triggered. The voltage feedback amount of the m bit in the processor 53 can be calculated or checked according to the above formula in hardware or software. The table is obtained. Then, the PWI_core0 bus is triggered to send the m bit feedback voltage information to the power adjustment device 52. The power adjustment device 52 internally obtains the n-bit digital voltage signal through direct decoding or through the LUT table, and performs internal high-precision fast digital-to-analog conversion. The 522 is converted to a Vdac output and finally fed back to the Vsensep pin of the DC-DC power supply chip 51 for AVS voltage regulation.

When the power supply voltage regulation is completed and stabilized for a period of time, the HPM inside the processor 53 will continue to detect the internal temperature of the chip or the circuit delay. If the target value is not met, the power supply voltage adjustment is performed through the repeated feedback voltage adjustment amount of the above adjustment process. The AVS power supply dynamic adjustment function is realized until the target value range requirement is met. If the processor 53 needs to operate at a higher frequency according to the application requirements, the AVS voltage adjustment can also be performed through the above adjustment process, except that the adjustment is often triggered by the frequency requirement change, when the processor 53 judges the work by software or hardware. When the frequency needs to change, first turn off the internal HPM and then trigger the PWI bus interface feedback voltage adjustment. After waiting for the power converter 51 to regulate and finish for a period of time, change the internal operating frequency of the chip and re-open the HPM for more accurate AVS power adjustment. The chip system provided by the embodiment of the invention can ensure that the processor 53 obtains more accurate electricity. Source voltage.

Embodiment 4

FIG. 6 is a flowchart of adjusting an AVS power supply according to an embodiment of the present invention, and the specific adjustment process is as follows:

S601: After power-on, the power chip outputs Vavs voltage to supply power to the core power of the CPU, at this time Vavs=Vstart;

S602: The CPU chip determines whether to change the working frequency by hardware or software, and if yes, performs step S604, and if not, performs step S603;

S603: The CPU turns on the HPM module, and the HPM starts real-time monitoring of internal performance parameters, and performs step S605;

S604: The CPU turns off the HPM module, and performs step S606.

S605: The HPM determines whether the internal performance parameter of the chip is abnormal. If the performance parameter is abnormal, the step S606 is performed. If the performance parameter is not detected, the step S605 is continued.

Optionally, the HPM continuously monitors the internals of the CPU chip. Once the degree of deviation between the internal parameters of the chip and the target parameter is exceeded, the voltage feedback amount of the m bit is calculated or checked according to the above formula (1) by hardware or software.

S606: the CPU chip calculates the voltage adjustment amount by hardware or software, and triggers the PWI_core0 bus to send the signal with the m bit feedback voltage to the power adjustment device, and performs step S607;

S607: The power adjustment device determines, according to the PWI status control signal, whether to receive the voltage adjustment amount in the PWI bus format. If the control signal is valid, perform step S609; otherwise, perform step S608;

S608: The power adjustment device is disconnected from S1, and Vdac has no output, and the process ends;

S609: The power adjustment device closes S1, receives and parses out the m bit feedback voltage signal through the PWI bus interface, decodes through a decoder inside the power adjustment device, or outputs n bits through a lookup table stored in the internal memory of the power adjustment device. Feedback the voltage signal, and then driving the DAC to output an analog feedback voltage signal Vdac to the power chip, and performing the S610 step;

S610: The CPU chip waits for a fixed power adjustment response delay, and then re-enters the step S602 to start the next round of AVS power adjustment process.

Embodiment 4

The power supply adjustment method is the same as that of the power supply adjustment device provided in the first embodiment. Therefore, the power supply adjustment method will not be specifically described in this embodiment. As shown in FIG. 7, the power supply adjustment method provided in this embodiment specifically includes the following steps:

S701 converts the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal matched with the power chip;

S702 converts the digital feedback voltage signal into an analog feedback voltage signal and outputs it to the power chip to adjust the power supply voltage.

Optionally, converting the digital feedback voltage signal into an analog feedback voltage signal and outputting to the power chip to adjust the power voltage includes:

The digital feedback voltage signal is converted into an analog feedback voltage signal, the analog feedback voltage signal is adjusted, and the adjusted analog feedback voltage signal is output to the power chip to adjust the power supply voltage.

Optionally, converting the voltage adjustment amount fed back by the load chip into the analog feedback voltage signal adapted by the power chip enables the power chip provided by the embodiment to adopt a general-purpose DC-DC power conversion module, and the power conversion module can be These types of load chips provide voltage and dynamically adjust the voltage of various types of load chips, so that the core power (core power) required by the load chip can be accurately adjusted to the minimum voltage required for the load chip to work normally, thereby reducing Chip power consumption. At the same time, since various types of load chips have their own definitions for the PWI bus interface for controlling the external power conversion circuit, for example, the intel processor chip has two definitions of parallel bus VID and serial bus SVID for the PWI bus interface. Therefore, each type of processor chip and the power chip need to pass the matched PWI bus interface to perform voltage regulation, which greatly reduces the versatility of the power supply adjusting device and increases the cost. For this, the external power supply is adopted in this embodiment. The conversion unit converts the voltage adjustment amount fed back by the processor into an analog feedback voltage signal applicable to the general power chip to implement the AVS function, thereby improving the versatility of the entire power adjustment device and realizing the AVS power supply adjustment function of the processor chip at a low cost. .

Optionally, when the controller converts the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal matched with the power chip, the digital feedback voltage can be obtained by direct decoding or by looking up the table through a LUT (lookup table). signal. When the voltage adjustment amount is the voltage difference, and the voltage difference is the m bit feedback voltage signal, the m bit feedback voltage signal is directly converted by decoding or table lookup. The n bit feedback voltage signal is a digital feedback voltage signal; when the voltage adjustment amount is a target voltage value, the target voltage value is a m bit feedback voltage signal, and the controller can decode or check The manner of the table converts the m bit feedback voltage signal into an n bit feedback voltage signal, which is a voltage difference signal.

In the LUT table, the voltage values before and after the conversion, that is, the correspondence between the m bit voltage value and the n bit voltage value, or the m bit voltage difference and the n bit voltage difference, or even the m bit voltage value and the n bit are included. Correspondence of voltage difference values, the LUT table is information stored according to the voltage state of the load chip. When the m bit feedback voltage signal fed back to the controller by the load chip does not have a necessary logical relationship with the n bit feedback voltage signal, the corresponding n bit feedback voltage signal is queried through the LUT table stored in the memory; when the m bit feedback voltage signal and n When the bit feedback voltage signal has a logical relationship, the n bit feedback voltage signal can be directly decoded by the decoder. That is, when the n-bit feedback voltage signal cannot be directly decoded, the signal can be searched from the LUT table, or when the corresponding n-bit feedback voltage signal is not found in the LUT table, the decoder can be directly decoded. .

Optionally, the bus interface unit 211 of the controller 21 is provided with at least one power management bus interface. Of course, a plurality of PWI bus interfaces may also be provided externally, and different interfaces may be adapted to different load chips. When the PWI bus interface includes at least two, the load chip selects one of the at least two power management bus interfaces that meets the requirements and is connected to the controller 21. Optionally, the load chip selects a PWI bus interface adapted from itself from the bus interface unit 211, and is connected to the controller 21. By setting a plurality of types of PWI bus interfaces, different types of load chips can be converted into signals compatible with a common power chip by using the power conversion device provided in this embodiment, thereby realizing the AVS function. Even if a plurality of chips of different PWI bus interfaces exist on a single board in the network device, the voltage of the chip can be adjusted by the power conversion device provided in this embodiment, thereby avoiding an increase in the material type of the power chip circuit, which is disadvantageous to the board. Cost control and board generation control, while using the same type of universal power chip can reduce the board area as much as possible in circuit design.

Optionally, the embodiment further provides a method for operating a chip system, which corresponds to the chip system in the second embodiment. Therefore, the description of the partial chip system will not be repeated herein. As shown in FIG. 8, the method for operating a chip system includes:

The S801 power chip supplies voltage to the load chip;

The S802 converts the voltage adjustment amount fed back by the load chip into an analog feedback voltage signal matched with the power chip by the foregoing power adjustment device;

The S803 power chip adjusts the power supply voltage based on the analog feedback voltage signal.

The load chip can adopt a processor chip with HPM module or a programmable chip capable of realizing HPM function, such as an FPGA, etc., and can perform performance on a load chip through an HPM module or a programmable chip capable of implementing HPM function. The parameters are monitored and the voltage adjustment is calculated based on the monitored performance parameters. When the power supply voltage regulation is completed and stabilized for one time, the HPM module inside the load chip or the programmable chip that can realize the HPM function will continue to monitor the internal temperature of the load chip or the circuit delay. If the target value is not reached, the power adjustment device is passed. The entire power feedback network repeats the feedback voltage adjustment amount to adjust the power supply voltage until the target value range is met, thereby realizing the AVS power supply dynamic adjustment function.

The power chip can realize the AVS function by using a common low-voltage high-current DC-DC power chip (DC-DC power conversion module). The DC-DC power chip has a remote compensation function, and is internally provided with a CMP (voltage comparator). The unit, the input terminal Vsensep of the CMP unit is connected with the input terminal Vsensep of the power chip, and the voltage adjustment amount of the load chip output is feedback-compensated by the Vsensep pin of the power chip, thereby realizing the adaptive voltage adjustment function. It should be understood that the power chip provided in this embodiment is only used to explain the present invention, and other common power chips having low current and large current characteristics, which are well known to those skilled in the art, may be used, which is not limited thereto.

For other load chips (such as processor chips or programmable chips) that do not have a dedicated AVS module, the dynamic voltage regulation function similar to AVS cannot be implemented. For this reason, the power supply adjustment device provided in this embodiment does not contain a dedicated power supply through the power feedback network. The voltage adjustment amount of the processor chip or the programmable chip output of the AVS module is fed back to the power chip, and the voltage adjustment is repeated continuously, thereby realizing the dynamic adjustment of the AVS power supply. The power feedback network mainly includes a power adjustment device, and the power adjustment device converts a processor chip that does not include a dedicated AVS module or a voltage adjustment amount of the programmable chip output, obtains an analog feedback voltage signal, and feeds back the analog feedback voltage signal. To the power chip, the power supply voltage is adjusted by the power chip, so that the voltage required by the load chip is accurately adjusted to the minimum voltage required for the load chip to work normally, and the power consumption of the power source is effectively reduced.

The obtained voltage adjustment amount may be a target voltage value or a voltage difference value, when the target voltage is acquired For the value, the above direct soldering method can be used, and of course, software or other hardware can be used. When the voltage difference is obtained, the difference between the obtained target voltage value and the actual voltage value is obtained, and the voltage difference value is obtained. When the number of voltages adjusted by the chip is large, the conversion efficiency can be improved by the voltage difference method, and the voltage regulation efficiency is also improved accordingly; when the number of voltage bits adjusted by the chip is small, the target voltage value or the voltage difference can be used. This will not be limited. In addition, when at least one of the internal performance parameters of the chip (such as clock frequency, power supply voltage, temperature, silicon aging, process offset) changes, the chip acquires a new target voltage value as a voltage adjustment amount by looking up the table. Or the voltage difference obtained by the difference between the target voltage value and the actual voltage value is used as the voltage adjustment amount and is regulated by the power chip.

The method for operating the chip system provided by the embodiment of the invention enables the AVS voltage adjustment function of the load chip to be implemented at a lower cost by using a universal power chip, and at the same time, the power supply provided by the embodiment can be used for different load chips. The adjusting device converts the output voltage adjustment amount to obtain an analog feedback voltage signal applicable to the universal power chip, so that various types of load chips can adopt an ordinary power chip, which greatly improves the versatility of the chip system and is also effective. The material cost of the single-board power chip is controlled, and the occupied area of the smaller power chip on the circuit board.

The above is a detailed description of the embodiments of the present invention in conjunction with the specific embodiments, and the specific embodiments of the present invention are not limited to the description. It will be apparent to those skilled in the art that the present invention may be made without departing from the spirit and scope of the invention.

Industrial applicability

The above technical solution can realize the adaptive power supply voltage adjustment function, reduce the power consumption of the load chip, and enable the power supply chip to realize the adaptive voltage adjustment function of the load chip by using an ordinary power converter, thereby reducing the cost while reducing the cost. It also increases the versatility of the power supply adjustment device.

Claims

A power adjustment device includes: a controller (21) and a digital to analog converter (22);

The controller (21) is arranged to convert the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal adapted to the power chip and output to the digital-to-analog converter (22);

The digital to analog converter (22) is configured to convert the digital feedback voltage signal into an analog feedback voltage signal and output to a power chip to adjust the power supply voltage.
The power supply adjusting device according to claim 1, wherein said controller (21) comprises: a bus interface unit (211) and a decoder (212);

The bus interface unit (211) is configured to receive a voltage adjustment amount fed back by the load chip, and output the voltage adjustment amount to the decoder (212);

The decoder (212) is arranged to decode the voltage adjustment amount to obtain the digital feedback voltage signal, and output the digital feedback voltage signal to the digital-to-analog converter (22);

The device also includes:

The memory (23) is arranged to store a lookup table by which the digital feedback voltage signal corresponding to the voltage adjustment amount is found and output to the digital to analog converter (22).
The power supply adjusting device of claim 1, further comprising:

The resistor unit (24) is arranged to provide a power supply negative feedback path for the analog feedback voltage signal output by the digital to analog converter, and output the analog feedback voltage signal to the power chip.
The power supply adjusting device of claim 1, further comprising:

The control switch (S1) is arranged to control the operating state of the device in accordance with a control signal transmitted by the load chip.
A power supply adjusting device according to any one of claims 1 to 4, wherein said bus interface unit (211) is provided with at least two power management bus interfaces.
A chip system comprising: a power chip (31), a load chip (33), and the power supply adjusting device (32) according to any one of claims 1 to 5;

The power chip (31) is configured to supply a voltage to the load chip (33); and adjust a power voltage according to the analog feedback voltage signal;

The power adjustment device (32) is configured to convert a voltage adjustment amount fed back by the load chip (33) into an analog feedback voltage signal matched with the power chip (31) and output the signal to the power chip (31) .
The chip system of claim 6 wherein said power conditioning device (32) is provided with at least two power management bus interfaces, said load chip (33) being arranged from said at least two power management bus interfaces An interface that meets the requirements is selected to be connected to the power conditioning device (32).
The chip system of claim 6

The load chip (33) is further configured to send a control signal to the power adjustment device (32) through the control interface to control an operating state of the power adjustment device (32).
A power supply adjustment method includes:

Converting the voltage adjustment amount fed back by the load chip into a digital feedback voltage signal adapted to the power chip (S701);

The digital feedback voltage signal is converted into an analog feedback voltage signal and output to a power supply chip to adjust a power supply voltage (S702).
The power conversion method according to claim 9, wherein said converting said digital feedback voltage signal into an analog feedback voltage signal and outputting to a power supply chip to adjust a power supply voltage (S702) includes:

Converting the digital feedback voltage signal into the analog feedback voltage signal;

Adjusting the analog feedback voltage signal;

The adjusted analog feedback voltage signal is output to the power chip to adjust the power supply voltage.
A method of operating a chip system, comprising:

The power chip supplies a voltage to the load chip (S801);

The power adjustment device according to any one of claims 1 to 5 converts the voltage adjustment amount fed back by the load chip into an analog feedback voltage signal adapted to the power chip (S802);

The power chip adjusts the power supply voltage according to the analog feedback voltage signal (S803).