JP4922882B2 - Variable voltage regulator - Google Patents

Description

  The present invention relates to a voltage variable regulator for changing an output voltage of a semiconductor device or the like.

  FIG. 10 is a diagram illustrating an example of a circuit of a voltage variable regulator (hereinafter sometimes simply referred to as a “regulator”) 1 according to the related art.

  The voltage variable regulator 1 includes an input terminal VIN, an output terminal VOUT, a GND (ground) terminal, a power supply start terminal EN, a voltage setting terminal A, and a voltage setting terminal B as terminals. As an example of voltage setting, it is assumed that four voltage settings are provided at two terminals of voltage setting terminals A and B.

  When there are many types of voltage setting values, this is handled by increasing the number of voltage setting terminals. The regulator 1 includes, as circuit elements, a PMOS transistor 2 for driving the regulator output, and an error amplifier 3 that amplifies the difference between the reference voltage VREF and the feedback voltage value Vf.

The error amplifier 3 performs power supply start control by a power supply start terminal EN.
In the regulator 1 shown in FIG. 10, the power start terminal EN is “H” active, and when the power start terminal EN is “H (High)”, the power is turned on and the power start terminal EN is “L (Low)”. "", The power is turned off. The regulator 1 further includes a variable resistor 5 controlled by the voltage setting terminals A and B, and changes the voltage value of the output terminal VOUT by changing the feedback voltage value Vf depending on the combination of the states of the voltage setting terminals A and B. Let

  FIG. 11 is a diagram illustrating an example of the internal configuration of the variable resistor 5. The variable resistor 5 includes a resistor element 6, an NMOS transistor 7, and an inverter element 8, and changes the ON state and OFF state of the NMOS transistor according to the voltage setting terminals A and B, thereby changing the variable resistance value of the variable resistor 5. .

Thereby, the voltage value of the output terminal VOUT can be adjusted by the voltage level of the feedback voltage value Vf, which is a detection voltage obtained by dividing the voltage value by the resistance element 4 and the variable resistor 5.
A voltage setting example of the voltage variable regulator 1 is shown in Table 1.

  First, when the power activation terminal EN is at “L” level, that is, the logical value is “0”, the regulator 1 is in the OFF state, and when the power activation terminal EN is at “H” level, that is, when the logical value is “1”. The regulator 1 is in an ON state.

  When the power supply startup terminal EN is at “H” level, that is, the regulator 1 is in the ON state, the voltage value of the output terminal VOUT is changed from 5 to 8 V as shown in Table 1 by the combination of the voltage setting terminals A and B. be able to.

  As described above, the regulator 1 is a circuit having a feedback configuration that drives and controls the PMOS transistor 2 via the error amplifier 3 so that the reference voltage VREF and the feedback voltage value Vf are equal.

  For example, Patent Document 1 discloses a configuration example of a high voltage generation circuit that changes a voltage according to an input signal in order to realize a stable operation with respect to a load and a voltage level that change according to each operation mode. ing.

  Patent Document 2 describes a configuration example of a voltage variable regulator in which the feedback amount control unit operates stably and has a high ripple removal rate.

JP 2003-15751 A JP 2003-330551 A

The conventional voltage variable regulator 1 has the following problems.
In the voltage variable regulator 1, since the power start terminal EN and the voltage setting terminals A and B of the regulator 1 exist as independent terminals, the number of terminals constituting the entire circuit increases, and the number of control terminals of the regulator 1 also increases. It will increase.

  If the number of terminals increases, the allowable number of terminals of the package on which the circuit is mounted is exceeded, and the number of terminals is increased to cope with it. Therefore, the package must be enlarged.

  Further, in the voltage variable regulator 1, if the power start-up terminal EN becomes “H” level before the voltage setting is determined, the power is turned on, and an unexpected voltage value is applied to the output terminal VOUT. Will be output.

  For example, as shown in the voltage waveform diagram of FIG. 12, the power supply start terminal EN becomes “H” level before the voltage setting terminals A and B, and the voltage setting terminals A and B immediately become “H” level. In such a case, an unexpected voltage value of 5 V (voltage setting terminals (A, B) = (L, L)) is output to the output terminal VOUT, and the expected voltage value thereafter. 8V (voltage setting terminals (A, B) = (H, H)) is output.

  If the voltage setting terminals A and B are changed while the power supply start terminal is at the “H” level, an unexpected voltage value is output to the output terminal VOUT depending on the timing.

  For example, as shown in the voltage waveform diagram of FIG. 13, when the power activation terminal EN is at “H” level, the voltage setting terminal A becomes “H” level, and immediately after that, the voltage setting terminal B becomes “H” level. Then, an unexpected voltage value 7V (voltage setting terminal (A, B) = (H, L)) is output to the output terminal VOUT, and an expected voltage value 8V (voltage setting terminal (A, B)) immediately after that is output. = (H, H)) is output.

  An object of the present invention is to provide a variable voltage regulator capable of reducing the number of terminals and reducing the size of a package.

The present invention includes an error amplifier that amplifies a voltage difference between a reference voltage and a feedback voltage;
A logical sum circuit that outputs a logical sum of all voltage setting terminals by changing the voltage level of at least one of the voltage setting terminals ;
A delay circuit that delays an output signal output from the OR circuit and input to the error amplifier to control the error amplifier between the OR circuit and the error amplifier ;
The voltage variable regulator is characterized in that the operation of the error amplifier is controlled in accordance with an output of an OR circuit.

  In addition, the present invention is characterized by including an adjustment circuit that adjusts the output timing of the output signal of the voltage setting terminal.

  According to the present invention, the logical sum of all voltage setting terminals is output by changing the voltage level of at least one of the error amplifier that amplifies the voltage difference between the reference voltage and the feedback voltage and the voltage setting terminal. An OR circuit, and controls the operation of the error amplifier according to the output of the OR circuit.

  Thus, by providing the OR circuit, it is possible to use both the voltage setting terminal and the power supply start-up terminal, and the voltage setting of the voltage variable regulator and the power ON / OFF control can be performed only by the voltage setting terminal. .

  Therefore, it is not necessary to provide a power start terminal, and the number of terminals can be reduced. Further, by reducing the number of terminals, it is possible to reduce the size of the package on which the regulator is mounted.

In addition , a delay circuit is provided that delays an output signal output from the OR circuit and input to the error amplifier to control the error amplifier between the OR circuit and the error amplifier.
As a result, it is possible to prevent the power from being turned on and outputting an unexpected voltage before the voltage setting is confirmed, and the power can be started after the voltage setting is confirmed. it can.

  Further, according to the present invention, the adjusting circuit for adjusting the output timing of the output signal of the voltage setting terminal is provided.

  As a result, it is possible to prevent an unexpected voltage value from being output when the voltage setting terminal is changed while the power is on, and the voltage value is determined after the voltage setting is confirmed. It can be changed.

FIG. 1 is a circuit diagram showing an internal configuration of a voltage variable regulator 10 which is a premise of the present invention.

  The voltage variable regulator 10 has an input terminal VIN, an output terminal VOUT, a GND (ground) terminal, a voltage setting terminal A, and a voltage setting terminal B as terminals, a PMOS transistor 2 for driving the regulator output, and a reference voltage as circuit elements. An error amplifier 3 that amplifies the difference between VREF and the feedback voltage value Vf, a resistance element 4, a variable resistor 5, and an OR circuit 11 are provided.

  The PMOS transistor 2 is for driving the output of the regulator 10, and the error amplifier 3 amplifies the difference between the reference voltage VREF and the feedback voltage value Vf. The variable resistor 5 is controlled by voltage setting terminals A and B.

  By changing the voltage level of one of the voltage setting terminals A and B of the voltage variable regulator 10, the voltage level of the OR circuit 11 of the voltage setting terminals A and B changes, and the reference voltage VREF and the feedback voltage value Control of ON state and OFF state of the error amplifier 3 that amplifies the voltage difference of Vf is performed.

  Specifically, the output signal AMP_EN of the OR circuit 11 is set based on the outputs of the voltage setting terminals A and B, and thereby the ON state and OFF state of the error amplifier 3 are controlled.

As a result, the voltage setting and the power supply start setting can be performed at the same time, and it is not necessary to provide the power supply start terminal EN, so that the number of terminals can be reduced. By reducing the number of terminals, it is possible to reduce the size of the package on which the variable voltage regulator is mounted.
Table 2 shows a setting example.

  When the voltage setting terminals A and B are at “L” level (logic value is 0), the output signal AMP_EN indicating the logical sum is at “L” level, and at this time, the power supply of the regulator 10 is turned off. When at least one of the voltage setting terminals A and B becomes “H” level (logical value is 1), the output signal AMP_EN indicating the logical sum becomes “H” level, and the power supply of the regulator 10 is turned on. At this time, the voltage values set at the voltage setting terminals A and B as shown in Table 2 are output to the output terminal VOUT.

  For example, the voltage setting terminal (A, B) = (L, H) is 6V, the voltage setting terminal (A, B) = (H, L) is 7V, and the voltage setting terminal (A, B) = (H, H) Then, 8V is output.

In the above configuration, as shown in the waveform diagram of FIG. 2, the voltage level of one of the voltage setting terminals A and B becomes “H” before the state of the voltage setting terminals A and B is determined. There is a case where an unexpected voltage value is output to the output terminal VOUT due to the H ”level and the internal power supply activation signal AMP_EN being turned on.

FIG. 3 is a circuit diagram showing the internal configuration of the voltage variable regulator 20 according to the first embodiment of the present invention . The voltage variable regulator 20 has a configuration that solves the problem of the first embodiment as described above.

The present embodiment is different from the voltage variable regulator 10 in that a delay circuit 21 is provided in the output section of the OR circuit 11.

  By providing the delay circuit 21, the power supply of the regulator 20 can be started after the voltage values of the voltage setting terminals A and B are determined.

  FIG. 4 is a diagram illustrating the configuration of the delay circuit 21. As shown in the figure, the delay circuit 21 is composed of two buffers 22 connected in series, and realizes a delay circuit by analog delay.

FIG. 5 shows a voltage waveform diagram of the regulator 20 of the first embodiment. First, when the voltage setting terminals A and B change, the resistance value of the variable resistor 5 changes and the voltage setting value of the output terminal VOUT (voltage setting terminals (A, B) = (H, H)) is determined. .

  Thereafter, the signal AMP_EN that has passed through the delay circuit 21 from the voltage setting terminals A and B changes to “H” level, the regulator 20 is turned on, and the voltage setting terminals A and B are connected in advance to the output terminal VOUT. The expected voltage value set in is output.

According to the configuration of the present embodiment, the regulator power supply can be started after the voltage value is determined, so that an unexpected voltage value can be prevented from being output.

In the configuration of the present embodiment, as shown in the waveform diagram of FIG. 6, the voltage setting terminal B is changed to “H” level while the power supply is started with the voltage setting terminal A set to “H” level, and then the voltage setting is performed. When the terminal A is changed to the “L” level, an unexpected voltage value 8V (voltage setting terminals (A, B) = (H, H)) may be output.

FIG. 7 is a circuit diagram showing an internal configuration of the voltage variable regulator 30 according to the second embodiment. The voltage variable regulator 30 has a configuration that solves the problem of the first embodiment as described above.

The second embodiment is different from the first embodiment in that the timing adjustment circuit 31 is interposed between the voltage setting terminals A and B and the variable resistor 5.

  By providing the timing adjustment circuit 31, it is possible to prevent an unexpected voltage value from being output to the output terminal VOUT.

  FIG. 8 is a diagram illustrating an internal configuration of the timing adjustment circuit 31. As shown in FIG. 8, the timing adjustment circuit 31 includes a timer 32 and a SW control unit 33. When the voltage of either voltage setting terminal A or B changes, the timer 32 starts, the timer 32 starts counting up for a certain time, and the counter unit 32a connected to the voltage setting terminal A or the counter unit connected to the voltage setting terminal B The state of the voltage setting terminals A and B when the count value of 32b matches the set value of the register is held in the SW control unit 33. The SW control unit 33 turns on or off the SW (SW_A, SW_B) of the NMOS transistor 7 in the variable resistor 5.

  The counter value of the timer 32 is reset at the next clock when the count value of the counter unit 32a or the counter unit 32b of the timer 32 matches the set value of the register.

In the present embodiment, as shown in the voltage waveform diagram of FIG. 9, the timer 32 starts counting at the next clock when the voltage setting terminal B changes to the “H” level, and the count value is the set value of the register (in this example). In this case, when it coincides with “7”), the SW (SW_A, SW_B) of the NMOS transistor 7 of the variable resistor 5 is turned ON or OFF, and the counter value of the timer 32 is reset.

With the configuration of the present embodiment, the voltage value can be changed even after the voltage setting is confirmed.

It is a circuit diagram which shows the internal structure of the voltage variable regulator 10 used as the premise of this invention. 4 is a diagram illustrating an example of an output waveform of the voltage variable regulator 10. FIG. It is a circuit diagram which shows the internal structure of the voltage variable regulator 20 which is 1st Embodiment. 2 is a diagram illustrating a configuration of a delay circuit 21. FIG. 4 is a diagram illustrating an example of an output waveform of the voltage variable regulator 20. FIG. 4 is a diagram illustrating an example of an output waveform of the voltage variable regulator 20. FIG. It is a circuit diagram which shows the internal structure of the voltage variable regulator 30 which is 2nd Embodiment. 2 is a diagram illustrating an internal configuration of a timing adjustment circuit 31. FIG. 4 is a diagram illustrating an example of an output waveform of the voltage variable regulator 30. FIG. It is a figure which shows the example of the circuit of the voltage variable regulator 1 by a prior art. 2 is a diagram illustrating an example of an internal configuration of a variable resistor 5. FIG. It is a figure which shows the example of the output waveform of the conventional voltage variable regulator 1. FIG. It is a figure which shows the example of the output waveform of the conventional voltage variable regulator 1. FIG.

Explanation of symbols

1, 10, 20, 30 Voltage variable regulator 2 PMOS transistor 3 Error amplifier 4 Resistive element 5 Variable resistor 11 OR circuit 21 Delay circuit 31 Timing adjustment circuit 32 Timer 33 SW control unit

Claims (2)

An error amplifier that amplifies the voltage difference between the reference voltage and the feedback voltage;
A logical sum circuit that outputs a logical sum of all voltage setting terminals by changing the voltage level of at least one of the voltage setting terminals ;
A delay circuit that delays an output signal output from the OR circuit and input to the error amplifier to control the error amplifier between the OR circuit and the error amplifier ;
A voltage variable regulator characterized in that the operation of the error amplifier is controlled in accordance with an output of an OR circuit. Voltage variable regulator according to claim 1, characterized in that it comprises an adjusting circuit for adjusting the output timing of the output signal of the voltage setting terminal.

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