TWI785657B - Power regulation circuit - Google Patents
Power regulation circuit Download PDFInfo
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- TWI785657B TWI785657B TW110122685A TW110122685A TWI785657B TW I785657 B TWI785657 B TW I785657B TW 110122685 A TW110122685 A TW 110122685A TW 110122685 A TW110122685 A TW 110122685A TW I785657 B TWI785657 B TW I785657B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/66—Regulating electric power
Abstract
Description
本發明係關於一種功率調節電路,尤指一種當受測電壓升高可使放電電流下降,從而使放電功率平穩之功率調節電路。 The invention relates to a power regulating circuit, especially a power regulating circuit which can reduce the discharge current when the measured voltage rises, thereby making the discharge power stable.
電源系統中常須對電容做放電動作,以滿足規格之要求,放電功率必須因應不同外部因素加以調節才能有足夠之安全性。 In the power system, it is often necessary to discharge the capacitor to meet the requirements of the specifications. The discharge power must be adjusted in response to different external factors in order to have sufficient safety.
為了不讓放電功率過大,可採取以下方法,可使用複數個放電元件,且控制致能一部分或全部放電元件,以調整放電程度。此外,可調整放電元件的占空比(duty cycle),以調整放電元件放電及不放電之時間的比例,使放電功率之最大值不超過安全條件的限制。上述操作中,常使用定電流的放電元件,當於電容測得之受測電壓上升時,放電功率也隨之上升。因此,當受測電壓上升時,放電功率易超過最大容許值,而造成危險。定電流的放電元件須於放電處之電壓接近最高值時預留餘量(margin),以避免放電功率超過最大容許值,此亦造成放電效率不佳。 In order to prevent the discharge power from being too large, the following method can be adopted. A plurality of discharge elements can be used, and some or all of the discharge elements can be controlled to adjust the discharge degree. In addition, the duty cycle of the discharge element can be adjusted to adjust the ratio of the discharge and non-discharge time of the discharge element, so that the maximum value of the discharge power does not exceed the limit of the safety condition. In the above operation, a constant current discharge element is often used. When the measured voltage measured on the capacitor increases, the discharge power also increases. Therefore, when the measured voltage rises, the discharge power will easily exceed the maximum allowable value, causing danger. The constant current discharge element must reserve a margin when the voltage at the discharge point is close to the maximum value, so as to avoid the discharge power exceeding the maximum allowable value, which also causes poor discharge efficiency.
實施例提供一種功率調節電路,包含一偵測單元、一控制單元及一放電元件。該偵測單元包含一第一端耦接於一電容以接收一感應電流,及一第二端。該控制單元用以根據該感應電流產生一控制電流,包含一第一端耦接於該偵測單元之該第二端,一第二端用以產生該控制電流,及一第三端。該放電元件用以根據該控制電流產生一放電電流,包含一第一端耦接於該控制單元之 該第三端,及一第二端耦接於該電容及該偵測單元之該第一端,以產生該放電電流。該電容透過該放電電流而放電,且當該偵測單元之該第一端之一受測電壓升高,該感應電流及該控制電流上升,且該放電電流下降。 The embodiment provides a power regulation circuit, which includes a detection unit, a control unit and a discharge element. The detection unit includes a first end coupled to a capacitor for receiving an induced current, and a second end. The control unit is used to generate a control current according to the induced current, and includes a first terminal coupled to the second terminal of the detection unit, a second terminal for generating the control current, and a third terminal. The discharge element is used to generate a discharge current according to the control current, including a first terminal coupled to the control unit The third end and a second end are coupled to the capacitor and the first end of the detection unit to generate the discharge current. The capacitance is discharged through the discharge current, and when the measured voltage of the first end of the detection unit increases, the induction current and the control current increase, and the discharge current decreases.
100:功率調節電路 100: Power regulation circuit
110:偵測單元 110: Detection unit
120:控制單元 120: Control unit
130:放電元件 130: discharge element
N11,N21,N31:第一端 N11, N21, N31: first end
N12,N22,N32:第二端 N12, N22, N32: Second terminal
N23:第三端 N23: third terminal
VDD,VSS:參考電壓端 VDD, VSS: reference voltage terminal
C:電容 C: Capacitance
ISEN:感應電流 I SEN : sense current
VDISC:受測電壓 V DISC : The measured voltage
IDISC:放電電流 I DISC : Discharge current
ICTL:控制電流 I CTL : control current
RSEN,RCTL:電阻 R SEN , R CTL : resistance
SW1,SW2:開關 SW1, SW2: switch
T1,T2,T3,T31,T32:電晶體 T1, T2, T3, T31, T32: Transistor
VCTL:電壓 V CTL : Voltage
VCTH:預定電壓 V CTH : predetermined voltage
A,B:線 A,B: line
第1圖至第3圖為相異實施例中,功率調節電路的示意圖。 FIG. 1 to FIG. 3 are schematic diagrams of power regulation circuits in different embodiments.
第4圖係第3圖之放電功率及受測電壓之關係圖。 Figure 4 is the relationship between the discharge power and the measured voltage in Figure 3.
第1圖為實施例中,功率調節電路100的示意圖。功率調節電路100可包含偵測單元110、控制單元120及放電元件130。
FIG. 1 is a schematic diagram of a
偵測單元110包含第一端N11及第二端N12,第一端N11耦接於電容C以接收感應電流ISEN。控制單元120用以根據感應電流ISEN產生控制電流ICTL。控制單元120包含第一端N21、第二端N22及第三端N23,第一端N21耦接於偵測單元110之第二端N12,且第二端N22用以產生控制電流ICTL。放電元件130用以根據控制電流ICTL產生放電電流IDISC。放電元件130包含第一端N31及第二端N32,第一端N31耦接於控制單元120之第三端N23,且第二端N32耦接於電容C及偵測單元110之第一端N11,以產生放電電流IDISC。電容C可透過放電電流IDISC而放電,且當偵測單元110之第一端N11(亦即放電之節點)之受測電壓VDISC升高,感應電流ISEN及控制電流ICTL可上升,且放電電流IDISC可下降。
The
由於電容C之放電功率(下文以P表示)可為放電電流IDISC及受測電壓VDISC之乘積(亦即,P=VDISC×IDISC),當受測電壓VDISC升高,使放電電流IDISC下降,可使放電功率P穩定。因此,可達成自適應控制(adaptive control),實現 定放電功率之放電操作,從而避免放電功率過高造成的危險,亦可避免預留過多餘量而導致放電效率不佳。 Since the discharge power of the capacitor C (represented by P below) can be the product of the discharge current I DISC and the measured voltage V DISC (that is, P=V DISC ×I DISC ), when the measured voltage V DISC increases, the discharge The current I DISC decreases to stabilize the discharge power P. Therefore, adaptive control can be achieved to realize the discharge operation with constant discharge power, thereby avoiding the danger caused by excessive discharge power, and also avoiding the poor discharge efficiency due to the reserve of excess margin.
第2圖為另一實施例中,功率調節電路100的示意圖。如第2圖所示,放電元件130可包含電晶體T1,電晶體T1可包含第一端、第二端及控制端,其中第一端可耦接於放電元件130之第二端N32,控制端可耦接於放電元件130之第一端N31,且第二端可耦接於參考電壓端VSS。參考電壓端VSS可例如為地端或低電壓端。
FIG. 2 is a schematic diagram of a
如第2圖所示,控制單元120可包含電晶體T2及電阻RCTL。電晶體T2可包含第一端、第二端及控制端,其中控制端可耦接於控制單元120之第一端N21,且第二端可耦接於參考電壓端VSS。電阻RCTL可包含第一端及第二端,其中第一端可耦接於參考電壓端VDD,且第二端可耦接於電晶體T2之第一端。參考電壓端VDD可例如為電源電壓端或高電壓端。
As shown in FIG. 2 , the
根據實施例,控制單元120可包含開關SW1及開關SW2。開關SW1可耦接於電晶體T2之第一端,及控制單元120之第三端N23之間。開關SW2可耦接於控制單元120之第三端N23,及參考電壓端VSS之間。當開關SW1及SW2之一者導通時,開關SW1及SW2之另一者截止。當開關SW1導通且開關SW2截止時,可執行實施例之操作,以調節及穩定電容C的放電功率。當開關SW1截止且開關SW2導通時,電容C可不放電。開關SW1及開關SW2可視需求選擇性設置。
According to an embodiment, the
如第2圖所示,偵測單元110可包含電阻RSEN及電晶體T3。電阻RSEN包含第一端及第二端,其中第一端可耦接於偵測單元110之第一端N11。電晶體T3可包含第一端、控制端及第二端,其中第一端可耦接於電阻RSEN之第二端,控制端可耦接於電晶體T3之第一端及偵測單元110之第二端N12,且第二端可耦接於參考電壓端VSS。
As shown in FIG. 2 , the
第2圖中,受測電壓VDISC及電晶體T3之門檻電壓VTH之差值,除以電 阻RSEN之阻值,所得之商可為感應電流ISEN,如下所示:ISEN=(VDISC-VTH)/RSEN。第2圖中,電晶體T3及T2可形成電流鏡,故感應電流ISEN可正比於控制電流ICTL,故上述等式可表示為;換言之,當戚應電壓VDISC上升,感應電流ISEN及控制電流ICTL可隨之上升。由於電晶體T2之第一端的電壓VCTL可為參考電壓端VDD之電壓值減去電阻RCTL兩端之跨壓,亦即可表示為VCTL=VDD-(ICTL×RCTL),因此當感應電壓VDISC上升且控制電流ICTL隨之上升時,電壓VCTL可下降。 In Figure 2, the difference between the measured voltage V DISC and the threshold voltage V TH of the transistor T3 is divided by the resistance value of the resistor R SEN , and the resulting quotient can be the induced current I SEN , as shown below: I SEN =( V DISC -V TH )/R SEN . In Figure 2, transistors T3 and T2 can form a current mirror, so the induced current I SEN can be proportional to the control current I CTL , so the above equation can be expressed as ; In other words, when the responsive voltage V DISC rises, the sense current I SEN and the control current I CTL can rise accordingly. Since the voltage V CTL at the first terminal of the transistor T2 can be the voltage value of the reference voltage terminal VDD minus the voltage across the two ends of the resistor R CTL , that is, it can be expressed as V CTL =VDD-(I CTL ×R CTL ), Therefore, when the induced voltage V DISC increases and the control current I CTL increases accordingly, the voltage V CTL may decrease.
當開關SW1導通以平穩放電功率時,關於電壓VCTL及放電電流IDISC之關係,可表示為IDISC=1/2×μ0×Cox×(VCTL-VTH)2,其中μ0可為電子的移動率,Cox為電晶體T1之氧化層的電容,VTH為電晶體T1之門檻電壓。因此,當電壓VCTL下降,則放電電流IDISC可隨之下降。 When the switch SW1 is turned on to stabilize the discharge power, the relationship between the voltage V CTL and the discharge current I DISC can be expressed as I DISC =1/2×μ 0 ×C ox ×(V CTL -V TH ) 2 , where μ 0 It can be the mobility of electrons, C ox is the capacitance of the oxide layer of transistor T1, and V TH is the threshold voltage of transistor T1. Therefore, when the voltage V CTL decreases, the discharge current I DISC can decrease accordingly.
根據上述,當感應電壓VDISC上升,電壓VCTL可下降,且放電電流IDISC可隨之下降,故可調節及平穩放電功率,其中放電功率為感應電壓VDISC及放電電流IDISC之乘積。 According to the above, when the induced voltage V DISC increases, the voltage V CTL can decrease, and the discharge current I DISC can decrease accordingly, so the discharge power can be adjusted and stabilized, wherein the discharge power is the product of the induced voltage V DISC and the discharge current I DISC .
第2圖中,電晶體T1、T2及T3可為N型金氧半電晶體。根據實施例,第2圖之電晶體亦可採用雙極性電晶體。 In FIG. 2, the transistors T1, T2 and T3 can be N-type metal oxide semiconductor transistors. According to an embodiment, the transistor in FIG. 2 may also be a bipolar transistor.
第3圖為另一實施例中,功率調節電路100的示意圖。第3圖中,控制單元120及放電元件130相似於第2圖,故不重述。如第3圖所示,偵測單元110可包含電阻RSEN、電晶體T31及電晶體T32。電阻RSEN可包含第一端及第二端,其中第一端可耦接於偵測單元110之第一端N11。電晶體T31可包含第一端、控制端及第二端,其中第一端可耦接於電阻RSEN之第二端,且控制端可接收預定電壓VCTH。電晶體T32可包含第一端、控制端及第二端,第一端可耦接於電晶體T31之第二端,控制端可耦接於電晶體T32之第一端及偵測單元110之第二端N12,且第二端可耦接於參考電壓端VSS。
FIG. 3 is a schematic diagram of a
第3圖中,受測電壓VDISC減去預定電壓VCTH,再減去電晶體T32之門檻電壓VTH所得的差值,除以電阻RSEN之阻值,所得之商可為感應電流ISEN,其可表示為:。相似於第2圖,當受測電壓VDISC上升,感應電流ISEN及控制電流ICTL可隨之上升,使電壓VCTL下降,導致放電電流IDISC下降,從而平穩電容C之放電功率。 In Figure 3, the difference obtained by subtracting the measured voltage V DISC from the predetermined voltage V CTH , and then subtracting the threshold voltage V TH of the transistor T32, divided by the resistance value of the resistor R SEN , the resulting quotient can be the induced current I SEN , which can be expressed as: . Similar to Figure 2, when the measured voltage V DISC increases, the sense current I SEN and the control current I CTL can increase accordingly, causing the voltage V CTL to decrease, resulting in a decrease in the discharge current I DISC , thereby stabilizing the discharge power of the capacitor C.
第3圖中,預定電壓VCTH可為啟動自適應控制之閾值電壓。當受測電壓VDISC小於預定電壓VCTH及門檻電壓VTH之和(亦即,當VDISC<VCTH+VTH)時,感應電流ISEN可接近零,使控制電流ICTL也接近零,此情況下由於電阻RCTL兩端幾乎無壓降,故電壓VCTL大約等於參考電壓端VDD之電壓,可使電晶體T1之控制端的電壓約為固定電壓。此情況下,放電元件130執行的放電係為傳統的定電流放電操作,故放電功率將隨受測電壓VDISC之上升而升高,無法執行定功率之放電操作。當受測電壓VDISC大於或等於預定電壓VCTH及門檻電壓VTH之和(亦即,當VDISC VCTH+VTH)時,功率調節電路100可執行定功率之放電操作。
In FIG. 3, the predetermined voltage V CTH may be a threshold voltage for enabling adaptive control. When the measured voltage V DISC is less than the sum of the predetermined voltage V CTH and the threshold voltage V TH (that is, when V DISC <V CTH +V TH ), the sense current I SEN can be close to zero, so that the control current I CTL is also close to zero In this case, since there is almost no voltage drop across the resistor R CTL , the voltage V CTL is approximately equal to the voltage of the reference voltage terminal VDD, so that the voltage of the control terminal of the transistor T1 is approximately a fixed voltage. In this case, the discharge performed by the
第3圖中,電晶體T1、T2及T32可為N型金氧半電晶體,且電晶體T31可為P型金氧半電晶體。根據實施例,第3圖之電晶體亦可採用雙極性電晶體。 In FIG. 3 , the transistors T1 , T2 and T32 can be N-type MOS transistors, and the transistor T31 can be P-type MOS transistors. According to an embodiment, the transistor in FIG. 3 may also be a bipolar transistor.
第4圖係第3圖之放電功率及受測電壓VDISC之關係圖。第4圖中,橫軸可為受測電壓VDISC,縱軸可為放電功率,線A可對應於不使用功率調節電路100的定電流放電操作,且線B可對應於使用功率調節電路100之定功率放電操作。如線A所示,根據定電流放電操作,放電功率將隨受測電壓VDISC之上升而升高,故可能導致功率過高之危險。如線B所示,於受測電壓VDISC大於一預定值(例如15伏特)後,放電功率可約為定值,故可實現定功率放電操作。第4圖所示的電壓及功率之數值僅為舉例,實施例不限於此。第2圖之電路的放電功率及受測電壓VDISC之關係圖相似於第4圖,故不贅述。
Figure 4 is the relationship between the discharge power and the measured voltage V DISC in Figure 3. In Figure 4, the horizontal axis can be the measured voltage V DISC , and the vertical axis can be the discharge power. Line A can correspond to the constant current discharge operation without using the
總上,實施例提供的功率調節電路100,可用以實現定功率之放電操
作,故可達成自適應控制,從而避免放電功率過高造成的危險,亦可避免預留過多餘量而導致放電效率不佳等缺失,故對於處理本領域長期難題,實有助益。
In summary, the
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變化與修飾,皆應屬本發明之涵蓋範圍。 The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.
100:功率調節電路 100: Power regulation circuit
110:偵測單元 110: Detection unit
120:控制單元 120: Control unit
130:放電元件 130: discharge element
N11,N21,N31:第一端 N11, N21, N31: first end
N12,N22,N32:第二端 N12, N22, N32: Second terminal
N23:第三端 N23: third terminal
VDD:參考電壓端 VDD: reference voltage terminal
C:電容 C: Capacitance
ISEN:感應電流 I SEN : sense current
VDISC:受測電壓 V DISC : The measured voltage
IDISC:放電電流 I DISC : Discharge current
ICTL:控制電流 I CTL : control current
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CN115509292A (en) | 2022-12-23 |
TW202301065A (en) | 2023-01-01 |
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