CN111208858A - Digital low dropout regulator - Google Patents

Digital low dropout regulator Download PDF

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Publication number
CN111208858A
CN111208858A CN202010042828.9A CN202010042828A CN111208858A CN 111208858 A CN111208858 A CN 111208858A CN 202010042828 A CN202010042828 A CN 202010042828A CN 111208858 A CN111208858 A CN 111208858A
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mos transistor
output end
voltage
signal
input end
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CN111208858B (en
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史江义
赵博
叶晓伟
马佩军
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Xidian University
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Xidian University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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Abstract

The invention belongs to the field of voltage regulators, and particularly relates to a digital low dropout regulator, which comprises: the transient response circuit comprises a voltage input end, a voltage output end, a first reference voltage input end, a second reference voltage input end, a third reference voltage input end, a voltage comparator, a transient detector, a coarse adjustment controller, a fine adjustment controller, a first transistor array, a second transistor array and a load capacitor, and a method combining coarse adjustment and fine adjustment is adopted, so that the transient response speed and the transient response precision are improved.

Description

Digital low dropout regulator
Technical Field
The invention belongs to the field of voltage regulators, and particularly relates to a digital low dropout regulator.
Background
With the continuous decrease of the process size, the system on chip becomes the mainstream of the integrated circuit design with the advantages of low power consumption, high efficiency, small area and the like, and a low dropout regulator (LDO) is used as a part of a power management unit in the system on chip, plays a crucial role in the performance of the whole system, and has an important significance in researching the integrated LDO on chip with fast transient response.
Conventional LDOs are analog LDOs that are regulated using high gain error amplifiers, which have the advantages of high bandwidth, low ripple, fast transient response, and high power supply rejection ratio, and are suitable for applications that are sensitive to power rail noise, such as analog circuits and radio frequency circuits. However, at supply voltages close to sub-threshold, there is not enough voltage margin for the error amplifier in analog LDO to control the power transistor to operate in saturation region, and the error amplifier cannot get high gain-bandwidth product at low supply voltage and is difficult to integrate with digital unit, in these cases, digital LDO appears.
Referring to fig. 1, fig. 1 is a schematic diagram of a conventional digital LDO structure including a voltage comparator, a bidirectional shift register and a transistor array. The voltage comparator detects an error between the output voltage and the reference voltage at a rising edge of each clock, and the bidirectional shift register performs a shift left or shift right operation according to an output of the voltage comparator, adjusts the number of transistors opened in the transistor array in the form of a temperature code, and thus plays a role in adjusting the output voltage. The digital LDO with the structure is an ideal choice suitable for SoC application because the control logic is a digital circuit, the digital LDO can work at a supply voltage close to a subthreshold value, and the process upgrading can be carried out more easily.
Although digital LDOs have the advantages of low voltage operation and easy process scaling compared to analog LDOs, the response speed is slow because the shift register can only open or close one MOS switch per clock cycle. In order to accelerate the transient response, the clock frequency can be increased, but the quiescent current is increased, so that the problem of mutual restriction between the transient response speed and the power consumption of the digital LDO is caused.
Wang shao, in its published paper "research and design of analog-digital LDO for tire pressure monitoring system" (university of chinese science and technology, university of china, thesis 2018.05), proposed a digital LDO based on asynchronous bidirectional pipeline structure, where the whole circuit has no clock signal, and relies on the operation of each small unit to generate a pulse signal to trigger the operation of the next unit, so as to achieve voltage regulation. The structure greatly reduces power consumption and enhances transient response because a clock signal is not used, but the delay unit is sensitive to PVT changes and is possibly unpredictable near a supply voltage close to a subthreshold value, and the robustness of the circuit is reduced.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a digital low dropout regulator. The technical problem to be solved by the invention is realized by the following technical scheme:
a digital low dropout voltage regulator comprising:
voltage input terminal VIN；
Voltage output terminal VOUT；
First reference voltage input terminal VREF；
Second reference voltage input terminal VREFH；
Third reference voltage input terminal VREFL；
A voltage comparator having an inverting input connected to the first reference voltage input VREFFor inputting a first reference voltage; the non-inverting input end of the voltage comparator is connected with the voltage output end VOUTFor receiving an output voltage; a comparison signal output end of the voltage comparator outputs a comparison signal;
a transient detector having a first signal input connected to the second reference voltage input VREFHFor receiving a second reference voltage; the second signal input end of the transient detector is connected with the third reference voltage input end VREFLFor receiving a third reference voltage; the third signal input end of the transient detector is connected with the voltage output end VOUTFor receiving the output voltage; the transient detector is used for comparing the output voltage, the second reference voltage and the third reference voltage to obtain a transient detection signal;
a first signal input end of the coarse tuning controller is connected with a signal output end of the transient detector and is used for receiving the transient detection signal; a second signal input end of the coarse tuning controller is connected with a comparison signal output end of the voltage comparator and used for receiving the comparison signal; the coarse tuning controller is used for outputting a coarse tuning control word according to the comparison signal and the transient detection signal and generating a fine tuning enable signal;
a first signal input end of the fine tuning controller is connected with the transient detector and used for receiving the transient detection signal; a second signal input end of the fine tuning controller is connected with a comparison signal output end of the voltage comparator and used for receiving the comparison signal; a third signal input end of the fine tuning controller is connected with a first signal output end of the coarse tuning controller and used for receiving the fine tuning enable signal; the fine adjustment controller is used for outputting a fine adjustment control word according to the comparison signal, the transient detection signal and the fine adjustment enabling signal;
a first transistor array having a voltage terminal connected to the voltage input terminal VIN(ii) a The signal input end of the first transistor array is connected with the second signal output end of the coarse tuning controller and used for receiving the coarse tuning control word; the output end of the first transistor array is connected with the voltage output end VOUTFor outputting the output voltage; the first transistor array is used for controlling the on and off of transistors in the first transistor array according to the coarse control word so as to adjust the output voltage;
a second transistor array having a voltage terminal connected to the voltage input terminal VIN(ii) a The signal input end of the second transistor array is connected with the signal output end of the fine tuning controller and used for receiving the fine tuning control word; the output end of the second transistor array is connected with the voltage output end VOUTFor outputting the output voltage; the second transistor array is used for controlling the on and off of the transistors in the second transistor array according to the fine adjustment control word so as to adjust the output voltage;
load capacitance COUTSaid load capacitance COUTThe upper electrode plate of the load capacitor C is respectively connected with the output end of the first transistor array and the output end of the second transistor array, and the load capacitor COUTThe lower plate of the anode is grounded.
In one embodiment of the present invention, the transient detector includes a first asynchronous dynamic comparator, a second asynchronous dynamic comparator, an exclusive or gate, a first inverter, a first delay unit, and a nand gate;
the non-inverting input end of the first asynchronous dynamic comparator is connected with the second reference voltage input end VREFH(ii) a The inverting input end of the first asynchronous dynamic comparator is connected with the voltage output end VOUT(ii) a The non-inverting input end of the second asynchronous dynamic comparator is connected with the third reference voltage input end VREFL(ii) a The inverting input end of the second asynchronous dynamic comparator is connected with the voltage output end VOUT(ii) a A first input end of the exclusive-or gate is connected with an output end of the first asynchronous dynamic comparator; a second input end of the exclusive-or gate is connected with an output end of the second asynchronous dynamic comparator; the output end of the exclusive-or gate is respectively connected with the input end of the first inverter and the input end of the first delay unit; the output end of the first inverter is connected with the first input end of the NAND gate; the output end of the first delay unit is connected with the second input end of the NAND gate, and the output end of the NAND gate, which is used as the output end of the transient detector, is respectively connected with the coarse adjustment controller and the fine adjustment controller.
In one embodiment of the present invention, the coarse tuning controller includes a binary search controller, a binary search encoder, a first frequency multiplier, a first nor gate, a second inverter, and a second delay unit;
a first signal input end of the binary search controller is used as a first signal input end of the coarse tuning controller and is connected with a signal output end of the transient detector; a second signal input end of the binary search controller is used as a second signal input end of the coarse tuning controller and is connected with a comparison signal output end of the voltage comparator; a first signal output end of the binary search controller is used as a second signal output end of the coarse tuning controller and is connected with the first transistor array; the first signal output end of the binary search controller is also connected with the signal input end of the binary search encoder, and the binary search encoder is sequentially connected with the first frequency multiplier in series; a first input end of the first nor gate is connected with a signal output end of the first frequency multiplier, a second input end of the first nor gate is connected with an output end of the second phase inverter, an input end of the phase inverter is connected with a signal output end of the transient detector, an output end of the first nor gate is connected with the second delay unit, and an output end of the second delay unit is connected with a clock signal input end of the binary search controller; and a second signal output end of the binary search controller is used as a first signal output end of the coarse tuning controller and is connected with the fine tuning controller.
In one embodiment of the invention, the fine-tuning controller comprises: the linear search controller, the linear search encoder, the second frequency multiplier, the second NOR gate and the third delay unit;
a first signal input end of the linear search controller is used as a first signal input end of the fine tuning controller and is connected with a signal output end of the transient detector; a second signal input end of the linear search controller is used as a second signal input end of the fine tuning controller and is connected with a comparison signal output end of the voltage comparator; a signal output end of the linear search controller is used as a signal output end of the fine tuning controller and is connected with the second transistor array; the signal output end of the linear search controller is sequentially connected with the linear search encoder and the second frequency multiplier in series; the signal output end of the second frequency multiplier is connected with the first input end of the second NOR gate, the second input end of the second NOR gate is used as the third signal input end of the fine tuning controller and is connected with the first signal output end of the coarse tuning controller, the output end of the second NOR gate is connected with the signal input end of the third delay unit, and the signal output end of the third delay unit is connected with the clock signal input end of the linear search controller.
In one embodiment of the invention, the first transistor array comprises MOS transistors M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15；
The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15Are all connected with the voltage input end VIN(ii) a The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15All the drain electrodes of the first and second transistors are connected with the voltage output end VOUT(ii) a The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15The drain electrodes of the two capacitors are connected with the load capacitor COUTThe upper plate of (1); the MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15The grid electrodes of the coarse tuning controller are all connected with the second signal output end of the coarse tuning controller.
In one embodiment of the invention, the second transistor array comprises MOS transistors M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29；
The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29Are all connected with the voltage input end VIN(ii) a The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29All the drain electrodes of the first and second transistors are connected with the voltage output end VOUT(ii) a The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29The drain electrodes of the two capacitors are connected with the load capacitor COUTThe upper plate of (1); the MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29The grid electrodes of the first and second switches are all connected with the signal output end of the fine tuning controller.
The invention has the beneficial effects that:
the invention adopts a method combining coarse adjustment and fine adjustment, when the load current generates transient, the coarse adjustment controller is started, the fine adjustment controller is closed, after the coarse adjustment is finished, the coarse adjustment controller is closed, and the fine adjustment controller is started; therefore, by adopting a control mode of combining the coarse adjustment controller and the fine adjustment controller, the transient response speed is improved, and the adjustment precision is also ensured.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a conventional digital LDO architecture;
fig. 2 is a schematic structural diagram of a digital low dropout regulator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a transient detector in the digital LDO according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a coarse tuning controller in a digital low dropout regulator according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating a fine tuning controller of a digital LDO according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a first transistor array in the digital low dropout regulator according to the embodiment of the present invention;
fig. 7 is a schematic structural diagram of a second transistor array in the digital low dropout regulator according to the embodiment of the present invention;
FIG. 8 is a detailed structural diagram of a digital LDO according to an embodiment of the present invention;
fig. 9 is a schematic diagram of transient simulation results of the digital low dropout regulator according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a digital low dropout regulator according to an embodiment of the present invention, including:
voltage input terminal VIN；
Voltage output terminal VOUT；
First reference voltage input terminal VREF；
Second reference voltage input terminal VREFH；
Third reference voltage input terminal VREFL；
A voltage comparator having an inverting input connected to the first reference voltage input VREFFor inputting a first reference voltage; the non-inverting input end of the voltage comparator is connected with the voltage output end VOUTFor receiving an output voltage; a comparison signal output end of the voltage comparator outputs a comparison signal;
a transient detector having a first signal input connected to the second reference voltage input VREFHFor receiving a second reference voltage; the second signal input end of the transient detector is connected with the third reference voltage input end VREFLFor receiving a third reference voltage; the third signal input end of the transient detector is connected with the voltage output end VOUTFor receiving the output voltage; the transient detector is used for comparing the output voltage, the second reference voltage and the third reference voltage to obtain a transient detection signal;
a first signal input end of the coarse tuning controller is connected with a signal output end of the transient detector and is used for receiving the transient detection signal; a second signal input end of the coarse tuning controller is connected with a comparison signal output end of the voltage comparator and used for receiving the comparison signal; the coarse tuning controller is used for outputting a coarse tuning control word according to the comparison signal and the transient detection signal and generating a fine tuning enable signal;
a first signal input end of the fine tuning controller is connected with the transient detector and used for receiving the transient detection signal; a second signal input end of the fine tuning controller is connected with a comparison signal output end of the voltage comparator and used for receiving the comparison signal; a third signal input end of the fine tuning controller is connected with a first signal output end of the coarse tuning controller and used for receiving the fine tuning enable signal; the fine adjustment controller is used for outputting a fine adjustment control word according to the comparison signal, the transient detection signal and the fine adjustment enabling signal;
a first transistor array having a voltage terminal connected to the voltage input terminal VIN(ii) a The signal input end of the first transistor array is connected with the second signal output end of the coarse tuning controller and used for receiving the coarse tuning control word; the output end of the first transistor array is connected with the voltage output end VOUTFor outputting the output voltage; the first transistor array is used for controlling the on and off of transistors in the first transistor array according to the coarse control word so as to adjust the output voltage;
a second transistor array having a voltage terminal connected to the voltage input terminal VIN(ii) a The signal input end of the second transistor array is connected with the signal output end of the fine tuning controller and used for receiving the fine tuning control word; the output end of the second transistor array is connected with the voltage output end VOUTFor outputting the output voltage; the second transistor array is used for controlling the on and off of the transistors in the second transistor array according to the fine adjustment control word so as to adjust the output voltage;
load capacitance COUTSaid load capacitance COUTThe upper electrode plate of the load capacitor C is respectively connected with the output end of the first transistor array and the output end of the second transistor array, and the load capacitor COUTThe lower plate of the anode is grounded.
Specifically, the voltage comparator is an asynchronous dynamic comparator, and a clock signal does not need to be additionally connected.
The invention adopts a method combining coarse adjustment and fine adjustment, when the load current generates transient, the coarse adjustment controller is started, the fine adjustment controller is closed, after the coarse adjustment is finished, the coarse adjustment controller is closed, and the fine adjustment controller is started; therefore, by adopting a control mode of combining the coarse adjustment controller and the fine adjustment controller, the transient response speed is improved, and the adjustment precision is also ensured.
In an embodiment of the present invention, please refer to fig. 3, fig. 3 is a schematic structural diagram of a transient detector in a digital low dropout regulator according to an embodiment of the present invention, where the transient detector includes a first asynchronous dynamic comparator, a second asynchronous dynamic comparator, an xor gate, a first inverter, a first delay unit, and a nand gate;
the non-inverting input end of the first asynchronous dynamic comparator is connected with the second reference voltage input end VREFH(ii) a The inverting input end of the first asynchronous dynamic comparator is connected with the voltage output end VOUT(ii) a The non-inverting input end of the second asynchronous dynamic comparator is connected with the third reference voltage input end VREFL(ii) a The inverting input end of the second asynchronous dynamic comparator is connected with the voltage output end VOUT(ii) a A first input end of the exclusive-or gate is connected with an output end of the first asynchronous dynamic comparator; a second input end of the exclusive-or gate is connected with an output end of the second asynchronous dynamic comparator; the output end of the exclusive-or gate is respectively connected with the input end of the first inverter and the input end of the first delay unit; the output end of the first inverter is connected with the first input end of the NAND gate; the output end of the first delay unit is connected with the second input end of the NAND gate, and the output end of the NAND gate, which is used as the output end of the transient detector, is respectively connected with the coarse adjustment controller and the fine adjustment controller.
Specifically, the transient detector detects whether a transient occurs in the load by comparing the second reference voltage, the third reference voltage, and the output voltage, and obtains a transient detection signal.
In an embodiment of the present invention, please refer to fig. 4, fig. 4 is a schematic structural diagram of a coarse tuning controller in a digital low dropout regulator according to an embodiment of the present invention, where the coarse tuning controller includes a binary search controller, a binary search encoder, a first frequency multiplier, a first nor gate, a second inverter, and a second delay unit;
a first signal input end of the binary search controller is used as a first signal input end of the coarse tuning controller and is connected with a signal output end of the transient detector; a second signal input end of the binary search controller is used as a second signal input end of the coarse tuning controller and is connected with a comparison signal output end of the voltage comparator; a first signal output end of the binary search controller is used as a second signal output end of the coarse tuning controller and is connected with the first transistor array; the first signal output end of the binary search controller is also connected with the signal input end of the binary search encoder, and the binary search encoder is sequentially connected with the first frequency multiplier in series; a first input end of the first nor gate is connected with a signal output end of the first frequency multiplier, a second input end of the first nor gate is connected with an output end of the second phase inverter, an input end of the phase inverter is connected with a signal output end of the transient detector, an output end of the first nor gate is connected with the second delay unit, and an output end of the second delay unit is connected with a clock signal input end of the binary search controller; and a second signal output end of the binary search controller is used as a first signal output end of the coarse tuning controller and is connected with the fine tuning controller.
Further, the adjusting time of the coarse adjusting controller is fixed and is not influenced by the change of the load current.
The coarse tuning controller of the invention adopts a binary search algorithm, has fixed tuning time, is not influenced by the variation range of the load current and has quick transient response.
In an embodiment of the present invention, referring to fig. 5, fig. 5 is a schematic structural diagram of a fine tuning controller in a digital low dropout regulator provided in an embodiment of the present invention, where the fine tuning controller includes: the linear search controller, the linear search encoder, the second frequency multiplier, the second NOR gate and the third delay unit;
a first signal input end of the linear search controller is used as a first signal input end of the fine tuning controller and is connected with a signal output end of the transient detector; a second signal input end of the linear search controller is used as a second signal input end of the fine tuning controller and is connected with a comparison signal output end of the voltage comparator; a signal output end of the linear search controller is used as a signal output end of the fine tuning controller and is connected with the second transistor array; the signal output end of the linear search controller is sequentially connected with the linear search encoder and the second frequency multiplier in series; the signal output end of the second frequency multiplier is connected with the first input end of the second NOR gate, the second input end of the second NOR gate is used as the third signal input end of the fine tuning controller and is connected with the first signal output end of the coarse tuning controller, the output end of the second NOR gate is connected with the signal input end of the third delay unit, and the signal output end of the third delay unit is connected with the clock signal input end of the linear search controller.
Specifically, when the load current generates transient state, so that the output voltage is higher than a second reference voltage or lower than a third reference voltage, the transient state detector outputs a transient state detection signal, the transient state detection signal is used for resetting the coarse tuning controller and the fine tuning controller, triggering the coarse tuning controller to generate an internal clock, and starting coarse tuning; and when the coarse adjustment is finished, the internal clock of the coarse adjustment controller stops overturning, and generates a fine adjustment enabling signal, and the fine adjustment enabling signal triggers the fine adjustment controller to generate the internal clock and start the fine adjustment.
The coarse tuning controller and the fine tuning controller of the invention also adopt self-clock control, thus eliminating the dependence of external clock. The internal clock can be generated only when the load current is in transient state, and no clock signal is generated in steady state, so that the power consumption is reduced. And the coarse adjustment controller and the fine adjustment controller are both integrated by standard units, so that the process portability of the digital LDO is improved.
In one embodiment of the present invention, please refer to FIG. 6, which illustratesFig. 6 is a schematic structural diagram of a first transistor array in the digital low dropout regulator provided in the embodiment of the present invention, where the first transistor array includes a MOS transistor M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15；
The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15Are all connected with the voltage input end VIN(ii) a The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15All the drain electrodes of the first and second transistors are connected with the voltage output end VOUT(ii) a The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15The drain electrodes of the two capacitors are connected with the load capacitor COUTThe upper plate of (1); the MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15The grid electrodes of the coarse tuning controller are all connected with the second signal output end of the coarse tuning controller.
In particular, the transistors in the first transistor array are sized according to a binary weight distribution, wherein the MOS transistors M10The current of the MOS transistor M is 10 times of the standard current11The current of the MOS transistor M is 20 times of the standard current12The current of the MOS transistor M is 40 times of the standard current13The current of the MOS transistor M is 80 times of the standard current14The current of the MOS tube M is 160 times of the standard current15Is 320 times the standard current.
In an embodiment of the present invention, referring to fig. 7, fig. 7 is a schematic structural diagram of a second transistor array in a digital low dropout regulator provided in an embodiment of the present invention, where the second transistor array includes a MOS transistor M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29；
The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29Are all connected with the voltage input end VIN(ii) a The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29All the drain electrodes of the first and second transistors are connected with the voltage output end VOUT(ii) a The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29The drain electrodes of the two capacitors are connected with the load capacitor COUTThe upper plate of (1); the MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29The grid electrodes of the first and second switches are all connected with the signal output end of the fine tuning controller.
Specifically, the MOS transistor M in the second transistor array20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29Are all standard currents, and the sum of the currents provided in the second transistor array is equal to the minimum size transistor M of the first transistor array10The current that can be supplied.
Further, referring to fig. 8, fig. 8 is a detailed structural schematic diagram of a digital low dropout regulator according to an embodiment of the present invention, in which a voltage comparator compares an error between an output voltage and a first reference voltage, and when the output voltage is lower than the first reference voltage, an output of the voltage comparator is at a high level; when the output voltage is higher than the first reference voltage, the output of the voltage comparator is at a low level; the method comprises the steps that two asynchronous dynamic comparators are input with a second reference voltage and a third reference voltage respectively in transient detection, when load current generates transient and the output voltage is smaller than the third reference voltage or larger than the second reference voltage, the transient detector generates a transient detection signal (namely a reset signal), the coarse adjustment controller and the fine adjustment controller are reset, and meanwhile, the generation of an internal clock of the coarse adjustment controller is triggered.
After the COARSE tuning controller is reset by the transient detection signal, COARSE tuning control words COARSE [5:0] are output and changed into 011111, the MOS transistor M15 with the maximum size in the first transistor array is opened, other MOS transistors are closed, the output signal of the binary search encoder is at a low level at the moment, and a first rising edge of an internal clock signal is generated; when the output voltage is less than the first reference voltage, the output of the voltage comparator is high level, and the output of the COARSE tuning control word COARSE [5:0] is changed into 001111; when the output voltage is greater than the first reference voltage, the comparison signal DIR output by the voltage comparator is at a low level, and the output COARSE tuning control word COARSE [5:0] is converted into 101111; when the COARSE tuning control word COARSE [5:0] is changed to 001111 or 101111, the output of the binary search encoder is at a high level, a second rising edge of the clock signal is generated, the binary search controller continues to perform COARSE tuning on the output voltage of the digital LDO at the second rising edge of the clock signal, and the subsequent clock generation principle is consistent with that described above, and is not repeated here. After five clock cycles, the coarse tuning control bits of all MOS tubes in the first transistor array are determined, the output of the binary search code is kept at a high level, the internal clock is not generated any more, the coarse tuning controller is in a sleep state, the power consumption of the digital LDO is reduced, and after the coarse tuning is finished, the coarse tuning controller generates a Fine tuning enable signal Fine _ En and simultaneously triggers the Fine tuning controller.
After the transient detection signal resets the FINE tuning controller, the FINE tuning control words FINE [9:0] of the FINE tuning controller are all high level, and all MOS transistors in the second transistor array are closed; after the coarse adjustment is finished, the Fine adjustment enable signal Fine _ En triggers the output signal of the Fine adjustment controller to perform left shift or right shift operation, and more or less MOS (metal oxide semiconductor) tubes are opened, so that the output voltage of the digital LDO (low dropout regulator) is adjusted.
Further, the first transistor array and the second transistor array are also connected to one end of the load current, and the other end of the load current is grounded.
Referring to fig. 9, fig. 9 is a schematic diagram of a transient simulation result of the digital low dropout regulator according to the embodiment of the present invention, where the simulation experiment is performed under conditions that an input voltage is 600mV, an output voltage is 550mV, a load capacitance is 200pF, a load current jumps between 1mA and 64mA, a switching time is 10ns, an output voltage undershoot caused by a current jump from 1mA to 64mA is 93mV, and a recovery time is 105 ns. The output voltage overshoot caused by the current jump from 64mA to 1mA is 48mV, and the recovery time is 80 ns.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (6)

1. A digital low dropout voltage regulator, comprising:
voltage input terminal (V)IN)；
Voltage output terminal (V)OUT)；
First reference voltage input terminal (V)REF)；
Second reference voltage input terminal (V)REFH)；
Third reference voltage input terminal (V)REFL)；
A voltage comparator having an inverting input connected to the first reference voltage input (V)REF) For inputting a first reference voltage; the non-inverting input terminal of the voltage comparator is connected to the voltage output terminal (V)OUT) For receiving an output voltage; a comparison signal output end of the voltage comparator outputs a comparison signal;
a transient detector having a first signal input connected toThe second reference voltage input terminal (V)REFH) For receiving a second reference voltage; the second signal input terminal of the transient detector is connected to the third reference voltage input terminal (V)REFL) For receiving a third reference voltage; a third signal input of the transient detector is connected to the voltage output (V)OUT) For receiving the output voltage; the transient detector is used for comparing the output voltage, the second reference voltage and the third reference voltage to obtain a transient detection signal;
a first signal input end of the coarse tuning controller is connected with a signal output end of the transient detector and is used for receiving the transient detection signal; a second signal input end of the coarse tuning controller is connected with a comparison signal output end of the voltage comparator and used for receiving the comparison signal; the coarse tuning controller is used for outputting a coarse tuning control word according to the comparison signal and the transient detection signal and generating a fine tuning enable signal;
a first signal input end of the fine tuning controller is connected with the transient detector and used for receiving the transient detection signal; a second signal input end of the fine tuning controller is connected with a comparison signal output end of the voltage comparator and used for receiving the comparison signal; a third signal input end of the fine tuning controller is connected with a first signal output end of the coarse tuning controller and used for receiving the fine tuning enable signal; the fine adjustment controller is used for outputting a fine adjustment control word according to the comparison signal, the transient detection signal and the fine adjustment enabling signal;
a first transistor array having a voltage terminal connected to the voltage input terminal (V)IN) (ii) a The signal input end of the first transistor array is connected with the second signal output end of the coarse tuning controller and used for receiving the coarse tuning control word; the output terminal of the first transistor array is connected to the voltage output terminal (V)OUT) For outputting the output voltage; the first transistor array is used for controlling the on and off of transistors in the first transistor array according to the coarse control word so as to adjust the output voltage;
a second transistor array having a voltage terminal connected to the voltage input terminal (V)IN) (ii) a The signal input end of the second transistor array is connected with the signal output end of the fine tuning controller and used for receiving the fine tuning control word; the output end of the second transistor array is connected with the voltage output end (V)OUT) For outputting the output voltage; the second transistor array is used for controlling the on and off of the transistors in the second transistor array according to the fine adjustment control word so as to adjust the output voltage;
load capacitance (C)OUT) Said load capacitance (C)OUT) Respectively connected to the output terminals of the first and second transistor arrays, and the load capacitor (C)OUT) The lower plate of the anode is grounded.
2. The digital low dropout regulator of claim 1, wherein the transient detector comprises a first asynchronous dynamic comparator, a second asynchronous dynamic comparator, an exclusive or gate, a first inverter, a first delay cell, and a nand gate;
the non-inverting input terminal of the first asynchronous dynamic comparator is connected with the second reference voltage input terminal (V)REFH) (ii) a The inverting input terminal of the first asynchronous dynamic comparator is connected to the voltage output terminal (V)OUT) (ii) a The non-inverting input end of the second asynchronous dynamic comparator is connected with the third reference voltage input end (V)REFL) (ii) a The inverting input terminal of the second asynchronous dynamic comparator is connected to the voltage output terminal (V)OUT) (ii) a A first input end of the exclusive-or gate is connected with an output end of the first asynchronous dynamic comparator; a second input end of the exclusive-or gate is connected with an output end of the second asynchronous dynamic comparator; the output end of the exclusive-or gate is respectively connected with the input end of the first inverter and the input end of the first delay unit; the output end of the first inverter is connected with the first input end of the NAND gate; the output end of the first delay unit is connected with the second input end of the NAND gate, and the output end of the NAND gate is used asThe output end of the transient detector is respectively connected with the coarse adjustment controller and the fine adjustment controller.
3. The digital low dropout regulator of claim 1, wherein the coarse control comprises a binary search controller, a binary search encoder, a first frequency multiplier, a first nor gate, a second inverter, and a second delay unit;
a first signal input end of the binary search controller is used as a first signal input end of the coarse tuning controller and is connected with a signal output end of the transient detector; a second signal input end of the binary search controller is used as a second signal input end of the coarse tuning controller and is connected with a comparison signal output end of the voltage comparator; a first signal output end of the binary search controller is used as a second signal output end of the coarse tuning controller and is connected with the first transistor array; the first signal output end of the binary search controller is also connected with the signal input end of the binary search encoder, and the binary search encoder is sequentially connected with the first frequency multiplier in series; a first input end of the first nor gate is connected with a signal output end of the first frequency multiplier, a second input end of the first nor gate is connected with an output end of the second phase inverter, an input end of the phase inverter is connected with a signal output end of the transient detector, an output end of the first nor gate is connected with the second delay unit, and an output end of the second delay unit is connected with a clock signal input end of the binary search controller; and a second signal output end of the binary search controller is used as a first signal output end of the coarse tuning controller and is connected with the fine tuning controller.
4. The digital low dropout regulator of claim 1 wherein the fine tuning controller comprises: the linear search controller, the linear search encoder, the second frequency multiplier, the second NOR gate and the third delay unit;
a first signal input end of the linear search controller is used as a first signal input end of the fine tuning controller and is connected with a signal output end of the transient detector; a second signal input end of the linear search controller is used as a second signal input end of the fine tuning controller and is connected with a comparison signal output end of the voltage comparator; a signal output end of the linear search controller is used as a signal output end of the fine tuning controller and is connected with the second transistor array; the signal output end of the linear search controller is sequentially connected with the linear search encoder and the second frequency multiplier in series; the signal output end of the second frequency multiplier is connected with the first input end of the second NOR gate, the second input end of the second NOR gate is used as the third signal input end of the fine tuning controller and is connected with the first signal output end of the coarse tuning controller, the output end of the second NOR gate is connected with the signal input end of the third delay unit, and the signal output end of the third delay unit is connected with the clock signal input end of the linear search controller.
5. The digital low dropout regulator of claim 1 wherein the first transistor array comprises MOS transistors M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15；
The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15Are all connected to the voltage input terminal (V)IN) (ii) a The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15Are all connected to the voltage output terminal (V)OUT) (ii) a The MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15Are all also connected to the load capacitance (C)OUT) The upper plate of (1); the MOS tube M10MOS transistor M11MOS transistor M12MOS transistor M13MOS transistor M14And MOS transistor M15The grid electrodes of the coarse tuning controller are connected with the second signal output of the coarse tuning controllerAnd (4) an end.
6. The digital low dropout regulator of claim 1 wherein the second array of transistors comprises MOS transistors M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29；
The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29Are all connected to the voltage input terminal (V)IN) (ii) a The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29Are all connected to the voltage output terminal (V)OUT) (ii) a The MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29Are all also connected to the load capacitance (C)OUT) The upper plate of (1); the MOS tube M20MOS transistor M21MOS transistor M22MOS transistor M23MOS transistor M24MOS transistor M25MOS transistor M26MOS transistor M27MOS transistor M28And MOS transistor M29The grid electrodes of the first and second switches are all connected with the signal output end of the fine tuning controller.
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