CN112103339A - 薄膜晶体管、像素电路、显示屏、电子设备 - Google Patents

薄膜晶体管、像素电路、显示屏、电子设备 Download PDF

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CN112103339A
CN112103339A CN202010913724.0A CN202010913724A CN112103339A CN 112103339 A CN112103339 A CN 112103339A CN 202010913724 A CN202010913724 A CN 202010913724A CN 112103339 A CN112103339 A CN 112103339A
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程才权
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Guangdong Oppo Mobile Telecommunications Corp Ltd
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Abstract

本申请公开了一种薄膜晶体管、像素电路、显示屏、电子设备。薄膜晶体管包括基板、半导体层、设置在基板和半导体层之间的第一绝缘层、栅极层、设置在栅极层和半导体层之间的第二绝缘层、设置在第一绝缘层与基板之间的屏蔽层，屏蔽层的电位为预设电位。本申请的薄膜晶体管、像素电路、显示屏、电子设备由于第一绝缘层与基板之间设置有预设电位的屏蔽层，因此，栅极层的电压不会引起基板上的电荷吸附，减少了栅极层的电压所吸附的电荷量，从而能够减小吸附的电荷对薄膜晶体管的驱动电流造成的影响，进而能够使得应用该薄膜晶体管的显示屏的显示亮度更加均匀。

Description

薄膜晶体管、像素电路、显示屏、电子设备
技术领域
本申请涉及显示技术领域，特别是一种薄膜晶体管、像素电路、显示屏、电子设备。
背景技术
在相关技术中，在显示屏的驱动电路驱动像素发光以显示画面时，驱动电路中的薄膜晶体管的栅极层会吸附电荷，其中，栅极层的电压不同，吸附的电荷量也不同。吸附的电荷会对栅极层的电压造成影响，从而影响薄膜晶体管的驱动电流，进而影响显示屏的发光亮度，使得显示屏的发光亮度不均匀。
发明内容
本申请的实施方式提供了一种薄膜晶体管、像素电路、显示屏、电子设备。
本申请实施方式的薄膜晶体管包括基板、半导体层、设置在基板和半导体层之间的第一绝缘层、栅极层、设置在栅极层和半导体层之间的第二绝缘层、设置在第一绝缘层与基板之间的屏蔽层，屏蔽层的电位为预设电位。
本申请实施方式的像素电路包括薄膜晶体管，所述薄膜晶体管包括基板、半导体层、设置在基板和半导体层之间的第一绝缘层、栅极层、设置在栅极层和半导体层之间的第二绝缘层、设置在第一绝缘层与基板之间的屏蔽层，屏蔽层的电位为预设电位。
本申请实施方式的显示屏包括像素电路，像素电路包括薄膜晶体管，所述薄膜晶体管包括基板、半导体层、设置在基板和半导体层之间的第一绝缘层、栅极层、设置在栅极层和半导体层之间的第二绝缘层、设置在第一绝缘层与基板之间的屏蔽层，屏蔽层的电位为预设电位。
本申请实施方式的电子设备包括壳体和上述显示屏，所述显示屏设置在所述壳体上。
本申请实施方式的薄膜晶体管、像素电路、显示屏、电子设备由于第一绝缘层与基板之间设置有预设电位的屏蔽层，因此，栅极层的电压不会引起基板上的电荷吸附，减少了栅极层的电压所吸附的电荷量，从而能够减小吸附的电荷对薄膜晶体管的驱动电流造成的影响，进而能够使得应用该薄膜晶体管的显示屏的显示亮度更加均匀。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
本申请的上述和/或附加的方面和优点从结合下面附图对实施方式的描述中将变得明显和容易理解，其中：
图1是本申请某些实施方式的电子设备的结构示意图；
图2是本申请某些实施方式的薄膜晶体管的结构示意图；
图3是本申请某些实施方式的像素电路的结构示意图。
具体实施方式
下面详细描述本申请的实施方式，所述实施方式的实施方式在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本申请，而不能理解为对本申请的限制。
请一并参阅图1和图2，本申请实施方式的电子设备1000包括显示屏300，显示屏300包括像素电路200，像素电路200包括薄膜晶体管100，薄膜晶体管100包括基板10、半导体层20、设置在基板10和半导体层20之间的第一绝缘层30、栅极层50、设置在栅极层50和半导体层20之间的第二绝缘层40、设置在第一绝缘层30与基板10之间的屏蔽层60，屏蔽层60的电位为预设电位。
在相关技术中，在显示屏的驱动电路驱动像素发光以显示画面时，驱动电路中的薄膜晶体管的栅极层会吸附电荷，其中，栅极层的电压不同，吸附的电荷量也不同。吸附的电荷会对栅极层的电压造成影响，从而影响薄膜晶体管的驱动电流，进而影响显示屏的发光亮度，使得显示屏的发光亮度不均匀。
本申请实施方式的薄膜晶体管100由于第一绝缘层30与基板10之间设置有预设电位的屏蔽层60，因此，栅极层50的电压不会引起基板10上的电荷吸附，减少了栅极层50的电压所吸附的电荷量，从而能够减小吸附的电荷对薄膜晶体管100的驱动电流造成的影响，进而能够使得应用该薄膜晶体管100的显示屏300的显示亮度更加均匀。
具体地，薄膜晶体管100(Thin Film Transistor，TFT)可以对各个独立的像素进行控制，薄膜晶体管100的反应时间较快，约80毫秒，使用薄膜晶体管100能够有效的提高反应时间。薄膜晶体管100具有迁移率高、制作工艺简单、大面积均匀性好和制造成本低等优点。薄膜晶体管100包括基板10，在一个例子中，显示屏300为柔性有源矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)显示屏，基板10可以使用聚酰亚胺(Polyimide，PI)材料作为基板，聚酰亚胺材料具有稳定性高、可耐极低温、机械性能优良和介电性能良好等特点。通过将薄膜晶体管器件形成在聚酰亚胺材料基板上，可以极大的扩展显示屏300的应用场景。柔性有源矩阵有机发光二极体显示屏的驱动是电流发光，可以使用开关薄膜晶体管和驱动薄膜晶体管控制电流。薄膜晶体管100包括半导体层20，在一个例子中，半导体层20可以是多晶硅(Low Temperature Poly-Silicon，LTPSi)材料，多晶硅又简称为P-Si，使用多晶硅材料的半导体层20具有制造成本低、电子迁移速率快、结构简单、稳定性高和制作出的薄膜电路面积更小等优点。在另一个例子中，半导体层20可以是非晶硅材料，例如为氢化非晶硅，氢化非晶硅通过将非晶硅中的悬空键采用氢填充，经过氢化后的氢化非晶硅的悬空键的密度显著减小，使得隙态密度降低至10E16/cm3以下，从而降低载流子通过隙态进行复合的概率，使得半导体层20表现出较好的电学性能。薄膜晶体管100包括设置在基板10和半导体层20之间的第一绝缘层30，第一绝缘层30可以隔绝基板10与半导体层20之间的电子传输，避免了薄膜晶体管100在工作过程中发生漏电或者短路的现象。第一绝缘层30可以为氧化硅、氮化硅、氧化硅、氧化锆以及有机材料中的一种或者多种材料的组合。薄膜晶体管100包括栅极层50，栅极层50可以为金属材料，当栅极层50上有不同大小电压时，栅极层50会吸附不同数量的电荷，吸附的电荷数量不同会导致显示屏300显示的亮度不同，因此可以通过电压数据线来调节显示器300的亮度。薄膜晶体管100包括设置在栅极层50和半导体层20之间的第二绝缘层40，第二绝缘层40可以隔绝栅极层50与半导体层20之间的电子传输，避免了薄膜晶体管100在工作过程中发生漏电或者短路的现象。薄膜晶体管100包括设置在第一绝缘层30与基板10之间的屏蔽层60，屏蔽层60的电位为预设电位。屏蔽层60可以是多晶硅材料的屏蔽层60，也可以是金属材料的屏蔽层60，屏蔽层60具有预设电位，预设电位可以是阳极电源电压，也可以是阴极电源电压，还可以是显示屏300具有的固定电位，甚至可以是单独接入一个地的电位，此处不做限定。屏蔽层60具有预设电位，因此，栅极层50的电压不会引起基板10上的电荷吸附，减少了吸附的电荷量，从而能够减小吸附的电荷对薄膜晶体管100的驱动电流造成的影响，进而能够使得应用该薄膜晶体管100的显示屏300的显示亮度更加均匀。
在一个例子中，薄膜晶体管100可以是PMOS，PMOS为低电平导通的薄膜晶体管，例如当栅极层50上导通电压为0V时，显示器300显示的画面为黑画面；当栅极层50上导通电压为-3V时，显示器300显示的画面为白画面。若薄膜晶体管100未设置有预设电位的屏蔽层60，则电荷可以吸附在基板10和第二绝缘层40上，而且栅极层50导通电压的大小不同会导致吸附在基板10和吸附在第二绝缘层40上的电荷数量不同，且吸附在基板10与第二绝缘层40上的电荷是相反的电性，例如在薄膜晶体管100为PMOS时，第二绝缘层40上吸附的是正电荷，基板10上吸附的是负电荷。栅极层50导通电压越大吸附的电荷数量越多，对显示器300显示的画面影响越大。若将栅极层50上导通电压改为-1.5V时，原先导通电压为-3V的栅极层50所吸附的电荷量较多，原先导通电压为0V的栅极层50上所吸附的电荷量较少，因此吸附的电荷对导通电压为-3V、显示白画面的薄膜晶体管100的影响大于导通电压为0V、显示黑画面的薄膜晶体管100，吸附的电性相反的电荷对于半导体层20的影响是叠加影响。原先栅极层50上导通电压为-3V、显示白画面的薄膜晶体管100更改后的电压可能会达不到-1.5V，例如为-1.3V，而原先栅极层50上导通电压为0V、显示黑画面的薄膜晶体管100更改后的电压可能会更接近-1.5V，因此原先栅极层50上导通电压为-3V、显示白画面的薄膜晶体管100的显示画面相对于原先栅极层50上导通电压为0V、显示黑画面的薄膜晶体管100的显示画面更暗，画面亮度有明显区别。若薄膜晶体管100设置有预设电位的屏蔽层60，则栅极层50的电压不会引起基板10上的电荷吸附，因此可以减少一半的吸附电荷量。若将栅极层50上导通电压改为-1.5V时，原先栅极层50上导通电压为-3V、显示白画面的薄膜晶体管100更改后的电压可能为-1.4V，同样在-1.5V的导通电压下，原先栅极层50上导通电压为-3V、显示白画面的薄膜晶体管100的显示画面亮度相对于原先栅极层50上导通电压为0V、显示黑画面的薄膜晶体管100的显示画面亮度不会有明显的区别。设置有预设电位的屏蔽层60能够减少栅极层50所吸附的电荷量，从而能够减小吸附的电荷对薄膜晶体管100的驱动电流造成的影响，进而能够使得应用该薄膜晶体管100的显示屏300的显示亮度更加均匀。
请再次参阅图1，在某些实施方式中，薄膜晶体管100的周边开设有过孔304，过孔304用于穿设连接线64，连接线64用于连接屏蔽层60与具有预设电位的连接端以使屏蔽层60的电位为预设电位，连接线64可以是金属连接线。在某些实施方式中，显示屏300包括显示区域301和非显示区域302，像素电路200形成在显示区域301内，过孔304形成在非显示区域302。连接线64穿过过孔304并连接屏蔽层与具有预设电位的连接端以使屏蔽层60的电位为预设电位。
在某些实施方式中，薄膜晶体管100的周边涂覆有导电层，屏蔽层60通过导电层与具有预设电位的连接端连接以使屏蔽层60的电位为预设电位。在某些实施方式中，显示屏300包括显示区域301和非显示区域302，像素电路200形成在显示区域301内，导电层可以涂覆在非显示区域302。导电层可以是导电胶或者导电银浆等导电材料，具体地，导电胶是一种固化或干燥后具有一定导电性能的胶粘剂，它通常以基体树脂和导电填料即导电粒子为主要组成成分，通过基体树脂的粘接作用把导电粒子结合在一起，形成导电通路，实现导电连接。导电银浆可以是聚合物银导电浆料，也可以是烧结型银导电浆料，导电银浆具有固化温度低，粘接强度极高、电性能稳定等特点。
在某些实施方式中，连接端包括电源阳极、电源阴极或接地端。若连接端为电源阳极则预设电位为阳极电源电压；若连接端为电源阴极则预设电位为阴极电源电压；若连接端为接地端则预设电位为零。
在某些实施方式中，薄膜晶体管100还包括第三绝缘层70、漏极层80和源极层90，漏极层80和源极层90通过半导体层20连接，第三绝缘层70设置在漏极层80和栅极层50之间，第三绝缘层70还设置在源极层90和栅极层50之间。第三绝缘层70可以隔绝漏极层80与栅极层50之间的电子传输，第三绝缘层70还可以隔绝在源极层90和栅极层50之间的电子传输，避免了薄膜晶体管100在工作过程中发生漏电或者短路的现象。漏极层80可以采用金、银、铜、铬、铝等金属中任意一项或者多项的合金材料。源极层90也可以采用金、银、铜、铬、铝等金属中任意一项或者多项的合金材料。
具体地，请参阅图3，像素电路200包括薄膜晶体管100，薄膜晶体管100包括栅极层50和半导体层20，当选通像素电路200时，像素电路200的薄膜晶体管100在栅极层50上导通电压，半导体层20在适当的导通电压的影响下作为通道感应出电子并进行导通，薄膜晶体管100漏极层80、源极层90和栅极层50导通形成电场。
在某些实施方式中，请再次参阅图3，像素电路200包括驱动电压端201、数据信号线202、扫描信号线203、开关晶体管204、存储电容205、发光元件206和接地端207。驱动电压端201与薄膜晶体管100的源极层90连接，薄膜晶体管100的漏极层80与发光元件206连接，薄膜晶体管100的栅极层50与存储电容205连接。开关晶体管204的栅极层与存储电容205连接，开关晶体管204的源极层与驱动电压端201连接，开关晶体管204的漏极层与数据信号线202连接，像素电路200可以通过控制开关晶体管204的截止或导通来控制像素电路200的工作状态。数据信号线202用于输入数据电压Vdata，存储电容205用于存储数据电压Vdata，薄膜晶体管100用于根据数据电压Vdata驱动发光元件206发光，驱动电压端101的驱动电压可以用ELVDD表示。
本申请公开一种显示屏300，显示屏300包括上述任意一种实施方式的像素电路200。显示屏300还包括显示区域301和非显示区域302，像素电路200形成在显示区域301内，过孔304和导电层可以形成在非显示区域302。
本申请公开一种电子设备1000，电子设备1000包括壳体500和上述任意一种实施方式的显示屏300，显示屏300设置在壳体500上。电子设备1000可包括手机、电脑、电子手表等。
请再次参阅图1，在某些实施方式中，电子设备1000包括处理器400，处理器400可以控制像素电路200的工作状态，处理器400可以是指驱动板。驱动板可以是中央处理单元(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(DigitalSignal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现成可编程门阵列(Field-Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。
在本申请的实施方式的描述中，参考术语“一个实施方式”、“某些实施方式”、“示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合所述实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
尽管已经示出和描述了本申请的实施方式，本领域的普通技术人员可以理解：在不脱离本申请的原理和宗旨的情况下可以对这些实施方式进行多种变化、修改、替换和变型，本申请的范围由权利要求及其等同物限定。

Claims (12)

1.一种薄膜晶体管，其特征在于，所述薄膜晶体管包括：
基板；
半导体层；
设置在所述基板和所述半导体层之间的第一绝缘层；
栅极层；
设置在所述栅极层和所述半导体层之间的第二绝缘层；
设置在所述第一绝缘层与所述基板之间的屏蔽层，所述屏蔽层的电位为预设电位。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管的周边开设有过孔，所述过孔用于穿设连接线，所述连接线用于连接所述屏蔽层与具有所述预设电位的连接端以使所述屏蔽层的电位为所述预设电位。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管的周边涂覆有导电层，所述屏蔽层通过所述导电层与具有所述预设电位的连接端连接以使所述屏蔽层的电位为所述预设电位。
4.根据权利要求2或3所述的薄膜晶体管，其特征在于，所述连接端包括电源阳极、电源阴极或接地端。
5.根据权利要求1所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括第三绝缘层、漏极层和源极层，所述漏极层和所述源极层通过所述半导体层连接，所述第三绝缘层设置在所述漏极层和所述栅极层之间，所述第三绝缘层还设置在所述源极层和所述栅极层之间。
6.一种像素电路，其特征在于，所述像素电路包括薄膜晶体管，所述薄膜晶体管包括：
基板；
半导体层；
设置在所述基板和所述半导体层之间的第一绝缘层；
栅极层；
设置在所述栅极层和所述半导体层之间的第二绝缘层；
设置在所述第一绝缘层与所述基板之间的屏蔽层，所述屏蔽层的电位为预设电位。
7.根据权利要求6所述的像素电路，其特征在于，所述薄膜晶体管的周边开设有过孔，所述过孔用于穿设连接线，所述连接线用于连接所述屏蔽层与具有所述预设电位的连接端以使所述屏蔽层的电位为所述预设电位。
8.根据权利要求6所述的像素电路，其特征在于，所述薄膜晶体管的周边涂覆有导电层，所述屏蔽层通过所述导电层与具有所述预设电位的连接端连接以使所述屏蔽层的电位为所述预设电位。
9.根据权利要求7或8所述的像素电路，其特征在于，所述连接端包括电源阳极、电源阴极或接地端。
10.根据权利要求6的像素电路，其特征在于，所述薄膜晶体管还包括第三绝缘层、漏极层和源极层，所述漏极层和所述源极层通过所述半导体层连接，所述第三绝缘层设置在所述漏极层和所述栅极层之间，所述第三绝缘层还设置在所述源极层和所述栅极层之间。
11.一种显示屏，其特征在于，所述显示屏包括权利要求6-10中任意一项所述的像素电路。
12.一种电子设备，其特征在于，所述电子设备包括壳体和权利要求11所述的显示屏，所述显示屏设置在所述壳体上。
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