CN112100914A - SiC power tube threshold voltage degradation model under temperature and voltage stress - Google Patents
SiC power tube threshold voltage degradation model under temperature and voltage stress Download PDFInfo
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Abstract
The invention discloses a SiC power tube threshold voltage degradation model under temperature and voltage stress, which comprises the following specific steps: firstly, establishing a single stress degradation model of the threshold voltage of the SiC power MOSFET under temperature stress and voltage stress according to an Arrhenius model, an inverse power law model and a degradation time model; and then fusing the obtained two single-stress threshold voltage degradation models into a threshold voltage degradation model of the SiC power MOSFET under temperature and voltage coupling dual stress by using three radial basis neurons. According to the invention, a single stress physical degradation model of the threshold voltage of the SiC power MOSFET is combined with the radial basis neuron, and a more universal threshold voltage degradation model under the working condition of simultaneously considering temperature and voltage dual stress is established, so that the degradation trend of the SiC power MOSFET can be accurately evaluated.
Description
Technical Field
The invention relates to a threshold voltage degradation model of a SiC power tube under temperature and voltage stress, belonging to the field of reliability evaluation and component degradation.
Background
With the continuous progress and improvement of power semiconductor devices in the aspects of structural design, process flow, material quality and the like, power switching tubes are widely applied to circuit systems such as photovoltaic inverters, switching power supplies and the like, and the traditional silicon-based devices approach intrinsic limits in the aspects of voltage blocking capability, switching frequency, control bandwidth and the like due to the performance limitation of silicon materials. Third-generation semiconductor materials represented by wide bandgap materials such as silicon carbide (SiC) have unique properties such as large forbidden bandwidth, high breakdown electric field, small dielectric constant and the like, so that the third-generation semiconductor materials become ideal substitute materials for manufacturing high-power, high-voltage, high-frequency and high-temperature electronic devices at present, and are paid attention to the fields such as aviation power supplies, smart power grids and the like which need high-temperature, high-voltage and high-efficiency power transformers. Research statistics show that the failure rate of a circuit caused by a power tube exceeds 30%, so that the method is particularly important for monitoring the degradation trend and early failure of the SiC power switch tube.
Compared with the traditional silicon material power tube, the research on the SiC power tube still mainly stays on failure mechanism, failure mode and characteristic parameter change trend, and the research on the degradation model of the characteristic parameter of the failure is less. At home and abroad, the on-resistance of the SiC power tube is mostly selected as a degradation characteristic parameter of a device for research, the research on the evolution trend of threshold voltage faults and degradation models is less, and the research is mainly focused under a single stress environment at present, and the deep research on the degradation trend and modeling analysis of the SiC power tube under multiple stresses is not carried out. Due to the complex and variable stress and the coupling correlation among the stresses, the degradation rate of the device is influenced by a plurality of stress changes (especially temperature stress and voltage stress) and time changes at the same time under the actual working condition. The variation trend of the characteristic parameters of the device is more complicated due to the coupling correlation among the stresses, and the parameter degradation model of the multi-stress device obtained by simply combining the parameter degradation models under the single stress of the device is not accurate.
The invention establishes a threshold voltage degradation model of the SiC power MOSFET under temperature stress and voltage stress, utilizes the global approximation capability of the radial basis neurons capable of approximating any nonlinear function with any precision, and well fuses the single stress degradation model of the SiC power MOSFET under the temperature stress and the voltage stress through the three radial basis neurons, wherein the threshold voltage degradation model is closer to the degradation trend of the device under the actual working condition. By combining the classical physical degradation model of the threshold voltage of the SiC power MOSFET with the data driving model, the effect of the parameter degradation model of the device under the temperature and voltage coupling stress is more accurate, and the universality is stronger.
Disclosure of Invention
The invention aims to provide a threshold voltage degradation model of a SiC power tube under temperature and voltage stress, wherein the threshold voltage degradation model under the temperature stress and the voltage stress of the SiC power tube is respectively established according to an Arrhenius model, an inverse power law model and a degradation time model, and finally, two single stress degradation models are fused into the threshold voltage degradation model of the SiC power MOSFET under the dual stress of the temperature and the voltage through three radial basis neurons.
In order to achieve the purpose, the invention establishes a threshold voltage degradation model of the SiC power tube under temperature and voltage stress, and specifically comprises the following steps:
step 1: and acquiring the temperature stress, the voltage stress and the threshold voltage degradation data of the SiC power MOSFET under the working conditions of temperature and voltage dual stress. Setting the working standard environment temperature of the SiC power MOSFET to be T0Gate source voltage is VGS0The remaining operating conditions remain unchanged. The first group selects n SiC power MOSFETs of the same type at the temperature of T and the grid-source voltage of VGS0The accelerated degradation experiment is carried out under the temperature stress working environment, and the threshold voltage value V of the MOSFET at m moments is collectedth1(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t; the second group selects n SiC power MOSFETs with the same model at the temperature of T0Gate source voltage is VGSThe voltage stress working environment is subjected to accelerated degradation experiment, and threshold voltage values V of the MOSFET at m moments are collectedth2(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t; the third group selects n SiC power MOSFETs with the same type at the temperature of T (the temperature is the same as the working temperature of the first group), and the grid-source voltage is VGS(gate-source voltage and second set of operating voltages) temperature stressPerforming accelerated degradation experiment under voltage stress working environment, and collecting threshold voltage values V of the MOSFET at m momentsth3(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t;
step 2: according to an Arrhenius model, an inverse power law model and a degradation time model, a degradation data set V is obtained for the SiC power MOSFET under temperature stress and voltage stressth1、Vth2Fitting is carried out, and a MOSFET temperature stress degradation model and a voltage stress degradation model are established;
and step 3: establishing a SiC power MOSFET dual-stress fusion degradation model, inputting the temperature stress degradation model and the voltage stress degradation model in the step 2 as radial basis neurons, and inputting a threshold voltage degradation parameter V under the working conditions of temperature stress and voltage stressth3And (3) as a radial basis neuron adjustment threshold value, obtaining a SiC power MOSFET threshold value voltage degradation model based on a physical model and a data driving model under the combined action of temperature stress and voltage stress:
wherein, WijAs a weight vector, the weight vector is,
is a radial basis transfer function, XiFor the ith input vector, b is the neuron adjustment threshold.
The method solves the problem that the degradation modeling can not be accurately carried out due to the fact that the failure mechanism of the characteristic parameters of the device is complex under the condition that the temperature stress and the voltage stress of the SiC power MOSFET are mutually coupled, considers the condition that the degradation rate of the device is simultaneously influenced by stress change and time change, and enables the model to be simple and low in complexity based on the fusion method of the radial basis neurons. The method based on the physical model fusion data driving model is better in universality, and accurate modeling of the degradation trend of the threshold voltage of the SiC power MOSFET under temperature stress and voltage stress can be realized.
Drawings
FIG. 1 is a flow chart of SiC power tube threshold voltage degradation modeling under temperature and voltage stress;
FIG. 2 is a diagram of a radial basis neuron model;
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings of the specification.
As shown in FIG. 1, the SiC power MOSFET is collected under single temperature stress T and single voltage stress VGSAnd temperature T and voltage VGSThreshold voltage degradation data in a dual stress environment; fitting threshold voltage data of the SiC power MOSFET according to the Arrhenius model, the inverse power law model and the degradation time model, establishing single stress degradation models of threshold voltage under temperature stress and voltage stress, and finally fusing the two single stress degradation models by adopting three radial basis neurons to obtain the threshold voltage degradation model of the SiC power MOSFET under the fusion of the temperature stress and the voltage stress.
Establishing a threshold voltage degradation model of the SiC power tube under temperature and voltage stress, wherein the specific implementation mode is as follows:
step 1: the method comprises the following steps of collecting threshold voltage degradation data of the SiC power MOSFET under the working conditions of temperature stress, voltage stress and temperature and voltage stress at the same time:
step 1.1, setting the working standard environment temperature of the SiC power MOSFET to be T0Gate source voltage is VGS0And the rest working conditions are unchanged. Firstly, n SiC power MOSFETs of the same type are selected at the temperature of T and the grid source voltage of VGS0The accelerated degradation experiment is carried out under the temperature stress working environment, and the threshold voltage value V of the MOSFET at m moments is collectedth1(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t;
step 1.2, selecting n SiC power MOSFETs of the same type as those in step 1.1 at the temperature of T0Gate source voltage is VGSThe voltage stress working environment is subjected to accelerated degradation experiment, and threshold voltage values V of the MOSFET at m moments are collectedth2(i，j)Wherein i 1, 2, n, j 1, 2, a.m, the sampling interval is delta t;
step 1.3, selecting n SiC power MOSFETs of the same type in the step 1.1 at the temperature of T (the temperature stress is the same as that in the step 1.1), and the grid-source voltage is VGS(voltage stress same as step 1.2) performing accelerated degradation experiment in temperature stress and voltage stress working environment, and collecting threshold voltage values V of the MOSFET at m momentsth3(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t;
step 2: a degradation data set V obtained by the SiC power MOSFET under temperature stress and voltage stress according to an Arrhenius model, an inverse power law model and a degradation time modelth1、Vth2Fitting is carried out, a temperature stress degradation model and a voltage stress degradation model of the power MOSFET are established, and the method specifically comprises the following steps:
step 2.1, establishing a temperature stress degradation model, firstly according to an Arrhenius model:
wherein D is a sensitive characteristic parameter of the electronic component, V (T) is the degradation rate at T temperature, A is a constant independent of the degradation rate, EaK is the boltzmann constant and T is the ambient temperature for the energy to be activated for the degradation process.
A degradation time model:
ΔP＝A′tn
wherein, Δ P is the variation of the sensitive parameters of the electronic components, a' is the parameters of the degradation model, t is the time for carrying out the accelerated degradation experiment, and n is the coefficient influenced by the temperature and the voltage stress.
SiC power MOSFET threshold voltage degradation rate of
Combination of Arrhenius model and degradation time model on degradation data V of threshold voltage under temperature stressth1Fitting to obtain a degradation model of the SiC power MOSFET under temperature stress, wherein the degradation model is as follows:
wherein A' is a constant, EaThe activation energy required for the threshold voltage degradation at different temperatures, k is the Boltzmann constant, T is the working environment temperature, T is the time for carrying out the accelerated degradation experiment, and n' is the coefficient affected by the temperature stress.
Step 2.2, establishing a voltage stress degradation model, and according to an inverse power law empirical model:
wherein D is a certain sensitive characteristic parameter of the electronic component, V (S) is the degradation rate at the temperature T, B is a undetermined coefficient determined by the reaction, S is the electrical stress applied to the component, n1The coefficients can be determined for activation.
SiC power MOSFET threshold voltage degradation rate of
Threshold voltage degradation data V under voltage stress by combining inverse power law model and degradation time modelth2Fitting to obtain a degradation model of the SiC power MOSFET under single voltage stress, wherein the degradation model is as follows:
wherein B' is a coefficient relating to temperature and time, C is a coefficient relating to a property of the device itself, and VGSFor the gate-source voltage, t is the time for the accelerated degradation experiment to proceed, and n "is the coefficient affected by the voltage stress.
And step 3: establishing a fusion degradation model of the SiC power MOSFET under temperature stress and voltage stress, and taking the temperature stress degradation model and the voltage stress degradation model in the step 2 as the input of three radial basis neurons and the working conditions of the temperature stress and the voltage stressLower threshold voltage degradation parameter Vth3The method is used as a neuron adjustment threshold value to obtain a degradation model of the SiC power MOSFET under the combined action of temperature stress and voltage stress, and comprises the following specific steps:
step 3.1, a radial basis function neuron model diagram is shown in fig. 2, a SiC power MOSFET temperature stress degradation model and a voltage stress degradation model are input into a radial basis function neuron, and a threshold voltage degradation parameter V under the condition of combined action of temperature stress and voltage stressth3As a neuron adjustment threshold;
and 3.2, the radial basis function neuron maps the input vector from a low-dimensional space to a high-dimensional space, and converts the low-dimensional linear indivisible problem into linear divisible, so that the learning speed is accelerated. Selecting three radial basis neurons to fuse the temperature stress degradation model and the voltage stress degradation model, wherein a radial basis transfer function is as follows:
finally, the obtained SiC power MOSFET threshold voltage degradation model under temperature and voltage coupling stress is as follows:
wherein, WijIs a weight vector, xiFor the ith input vector, b is the neuron adjustment threshold.
Claims (3)
1. The SiC power tube threshold voltage degradation model under temperature and voltage stress is characterized by specifically comprising the following steps:
step 1: the method comprises the following steps of obtaining the degradation parameters of the threshold voltage of the SiC power MOSFET under the working conditions of temperature stress, voltage stress and dual stress of temperature and voltage at the same time:
step 1.1, setting the standard working environment temperature of the SiC power MOSFET to be T0Gate source voltage is VGS0The rest working conditions are kept unchanged. Firstly, n SiC power MOSFETs of the same type are selected at the temperature of T and the grid source voltage of VGS0The accelerated degradation experiment is carried out under the temperature stress working environment, and the threshold voltage value V of the power MOSFET at m moments is collectedth1(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t;
step 1.2, selecting n SiC power MOSFETs with the same size as the SiC power MOSFETs in the step 1.1, and controlling the temperature to be T0Gate source voltage is VGSThe accelerated degradation experiment is carried out under the voltage stress working environment, and the threshold voltage value V of the power MOSFET at m moments is collectedth2(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t;
step 1.3, selecting n SiC power MOSFETs with the same type as the SiC power MOSFETs in the step 1.1, wherein the temperature is T (the temperature stress environment is the same as the step 1.1), and the grid-source voltage is VGS(voltage stress environment same as step 1.2) under temperature and voltage stress working environment, performing accelerated degradation experiment, and collecting threshold voltage values V of the power MOSFET at m momentsth3(i，j)Wherein i is 1, 2,.. times, n, j is 1, 2,. times, m, and the sampling interval is Δ t;
step 2: according to an Arrhenius model, an inverse power law model and a degradation time model, a degradation data set V obtained by combining a SiC power MOSFET under temperature stress and voltage stressth1、Vth2Establishing a MOSFET temperature stress degradation model and a voltage stress degradation model;
and step 3: establishing a SiC power MOSFET dual-stress fusion degradation model, inputting the temperature stress degradation model and the voltage stress degradation model in the step 2 as radial basis neurons, and inputting threshold voltage degradation data V under the temperature and voltage stress working conditionsth3And adjusting the threshold value as a radial basis neuron, and finally obtaining a threshold voltage degradation model of the SiC power MOSFET under the combined action of temperature stress and voltage stress.
2. The SiC power MOSFET of claim 1 under temperature and voltage stress degradation model, wherein the single stress degradation model under temperature stress and voltage stress in step 2 comprises the following steps:
(1) according to an Arrhenius empirical model
And the degradation time model Δ P ═ a' tnCombining the two models, fitting the threshold voltage degradation data V collected in step 1.1th1Obtaining a threshold voltage degradation model of the SiC power MOSFET under temperature stress as follows:
wherein A' is a constant, EaThe activation energy required for the threshold voltage degradation at different temperatures, k is the Boltzmann constant, T is the working environment temperature, T is the time for carrying out the accelerated degradation experiment, and n' is the coefficient affected by the temperature stress.
(2) According to an inverse power law empirical model
And a model of time of degradation
Combining the two models, fitting the threshold voltage degradation data V collected in step 1.2th2The obtained threshold voltage degradation model under the voltage stress of the SiC power MOSFET is as follows:
wherein B' is a coefficient relating to temperature and time, C is a coefficient relating to a property of the device itself, and VGSFor the gate-source voltage, t is the time for the accelerated degradation experiment to proceed, and n "is the coefficient affected by the voltage stress.
3. The SiC power MOSFET fusion degradation model under temperature stress and voltage stress of claim 1, wherein the step 3 is based on a threshold voltage degradation model of a three radial basis neuron dual-stress fusion MOSFET, and comprises the following specific steps:
(1) taking a temperature stress degradation model and a voltage stress degradation model of the SiC power MOSFET in the 2 as the input of three radial basis neurons, and taking a threshold voltage degradation parameter V under the combined action of temperature stress and voltage stressth3As a neuron threshold adjustment parameter;
(2) the SiC power MOSFET temperature stress physical model and the voltage stress physical model are fused through three radial basis neurons to obtain a threshold voltage degradation model based on the temperature stress coupling voltage stress condition:
wherein, WijAs a weight vector, the weight vector is,
is a radial basis transfer function, XiFor the ith input vector, b is the neuron adjustment threshold.
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| CN104122492A (en) * | 2014-07-24 | 2014-10-29 | 北京大学 | Method for predicting work voltage of service life of semiconductor device |
| CN109190244A (en) * | 2018-08-31 | 2019-01-11 | 哈尔滨工业大学 | A kind of method for building up of N-channel VDMOSFET degradation model under PBTI effect |
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