CN112100109A - Cable connection fault-tolerant connection device and method - Google Patents
Cable connection fault-tolerant connection device and method Download PDFInfo
- Publication number
- CN112100109A CN112100109A CN202010925311.4A CN202010925311A CN112100109A CN 112100109 A CN112100109 A CN 112100109A CN 202010925311 A CN202010925311 A CN 202010925311A CN 112100109 A CN112100109 A CN 112100109A
- Authority
- CN
- China
- Prior art keywords
- processor
- check code
- port group
- connector
- port
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000013507 mapping Methods 0.000 claims description 24
- 238000004891 communication Methods 0.000 claims description 16
- 238000012795 verification Methods 0.000 claims description 14
- 238000011144 upstream manufacturing Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 230000006870 function Effects 0.000 description 8
- 238000004590 computer program Methods 0.000 description 7
- 238000012937 correction Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 4
- 238000011835 investigation Methods 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000013024 troubleshooting Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0016—Inter-integrated circuit (I2C)
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Hardware Redundancy (AREA)
Abstract
The invention discloses a cable connection fault-tolerant connecting device and method. The method comprises the steps that a first processor is arranged on a mainboard card and connected with an upper device through a first port group; the first processor is connected with a switch device through a second port group, the switch device is connected with the first processor through an I2C bus, and the switch device is connected with a first connector; the first connector is connected with a second connector, and the second connector is connected with the daughter board card; the first processor is connected with the first storage unit; the first processor is connected with the first check code channel; the second check code channel is connected with a second processor, and the second processor is connected with a second storage unit; the second processors are connected with the corresponding first processors. The invention discloses a cable connection fault-tolerant connecting device and a method, wherein a first processor controls the switching of a switch device to realize a second connector connection attempt, and the second processor returns an attempt result to correct errors, so that the efficiency is high and omission is avoided.
Description
Technical Field
The invention relates to the technical field of board card connection, in particular to a cable connection fault-tolerant connection device and method.
Background
The design of the main board card is that a basic function module and an extended function interface are often arranged on the main board, and for different design requirements, the main board card can be interconnected with the main board card through the extended function interface by designing different daughter board cards, so that corresponding function configuration is realized.
The interconnection mode of cables between the boards at present is mainly for connecting main board card and daughter board card through connector or wiring, and in assembling process, to producing the line assembly personnel, the phenomenon that takes place connector or wiring connection mistake in the assembling process takes place occasionally, especially when the daughter board card quantity that the main board card was connected is more. Different problems can be caused in different application scenes due to wrong connection, such as wrong disk sequence of a hard disk connected with a back plate, incapability of normal work of equipment and the like. After the main board card is connected with the daughter board card connector by manpower, whether the connector is connected correctly is detected by manually carrying out signal transmission verification, and the trouble is eliminated. Through manual investigation, it is difficult to avoid the careless omission of manual inspection, once the careless omission is inspected in the subsequent inspection process, the process of unpacking, assembling and disassembling in the investigation may be faced.
Disclosure of Invention
The invention provides a cable connection fault-tolerant connecting device, aiming at solving the problems that whether the connector is connected correctly or not is detected in a mode of manually carrying out signal transmission verification in the prior art, and the troubleshooting is troublesome; and the problem of omission is difficult to avoid through manual investigation.
In order to achieve the above object, the present invention provides a cable connection fault-tolerant connection device, which comprises a main board card and at least one daughter board card connected to the main board card, wherein the main board card is provided with at least one first processor, the daughter board card is provided with at least one second processor, wherein,
the first processor is connected with an upper device through a first port group; the first processor configuring at least one second port group inheriting the first port group; any one of said second port groups is connected to a switch device,
the switch device is connected with the first processor through an I2C bus, and the switch device is connected with a first connector; the first connector is connected with a second connector, and the second connector is connected with the daughter board card;
the first connector is provided with a first check code channel, and the second connector is provided with a second check code channel connected with the first check code channel;
the first processor is connected with the first storage unit; the first processor is connected with the first check code channel through a port; the second check code channel is connected with a second processor, and the second processor is connected with a second storage unit; the second processor is electrically connected with the corresponding first processor.
Preferably, the second processor is electrically connected to a counter, and the counter is electrically connected to the first processor.
Preferably, any one of the second port groups maps a unique first port group of the first port group.
Preferably, any first port group in the first port group is configured with a unique first check code, the first storage unit stores the first check code, any second connector is configured with a unique second check code, and the second storage unit stores the second check code.
Preferably, any second port group in the second port group is connected with a unique upstream port group of the switch device, any upstream port group can be selectively connected with a downstream port group of the switch device, and the downstream port group is connected with the first connector.
The invention provides a cable connection fault-tolerant connection method, which is applied to a cable connection fault-tolerant connection device and comprises the following steps:
s100, configuring a unique first check code for any first port group in a first port group, and configuring a second check code capable of checking the first check code for a second connector;
s200, the first processor controls any switch device to enable one group of second ports to be communicated with the second connector;
s300, the first processor acquires a first check code of a first port group corresponding to a second port group in S200 and transmits the first check code to the second processor;
s400, the second processor determines a second connector for forwarding the first check code and acquires a second check code according to the second connector;
s500, the second processor verifies the second check code and the first check code;
and if the verification is not passed, the first processor controls the switch to switch the uplink port groups so that the rest second port groups are sequentially connected with the first connector and are verified until the verification is passed.
Further, configuring a unique first check code for any one of the first port groups comprises:
configuring a first mapping relation for recording the relation between the communication signal and the first check code,
storing the first mapping relation in the first storage unit;
the obtaining, by the first processor, the first check code of the first port group corresponding to the second port group includes:
the upper device sends different communication signals to any one of the first port groups,
the first processor obtains the communication signal and a first mapping relation, and the first processor obtains a corresponding first check code from the first mapping relation according to the communication signal.
Furthermore, the first processor transmits an upstream port group selection signal to the switch device through an I2C bus, and the switch device controls the corresponding upstream port group to be communicated with the downstream port group according to the selection signal, so that one group of second port groups is communicated with the second connector; any one uplink port group selection signal controls a unique uplink port group to be connected to a downlink port group, and all uplink port group selection signals can traverse an uplink port group.
Furthermore, the second processor checks that the first check code and the second check code fail, the second processor sends a counting signal to a counter, and the counter receives the counting signal to count and sends counting information to the first processor; and the first processor selects a corresponding uplink port group selection signal according to the counting information and sends the signal to the switch device through I2C.
Further, configuring the second connector with a second verification code capable of verifying the first verification code comprises:
configuring a second mapping relationship of the second check code channel to a second check code relationship,
the second mapping relation is stored in a second storage unit;
the second processor obtaining the second check code comprises:
the second processor determines a second check code channel for obtaining the first check code, the second processor obtains the second mapping relationship,
and the second processor acquires the second check code according to the second check code channel and the second mapping relation.
The fault-tolerant connecting device and the fault-tolerant connecting method for cable connection have the following beneficial effects:
connecting an upper computer through a first port group of the first processor, wherein the first processor expands the first port group to form at least one second port group, so that signals of each second port group are consistent with signals of the first port group, any second port group in each second port group is connected to a first connector through the switch device, and the first connector is connected with a second connector; this enables one first connector for each of said second port groups to be used to transmit signals of all of said first port groups;
the first processor transmits a first check code corresponding to the second port group to the second processor through the first connection device and the second connector, the second processor acquires a second check code according to the second connector, the second processor checks the second check code and the first check code to judge whether the second connector is connected to the second port group of the pair, if the check is not passed, the second processor sends information to the first processor, and the first processor controls the switch device to switch the uplink ports, so that another second port group is connected with the first connector, and the first processor sends the first check code of another second port group to the second processor for checking until the check is passed;
therefore, the invention can realize automatic error correction through the switching of the switch device, does not need manual error correction, has high efficiency and does not generate omission; the configured first check code and the second check code have more bits which can be set, and can provide check for more connectors; after the lines are connected, the correction is carried out without changing the lines, so that the fault tolerance is higher, connection errors are detected in subsequent processes, the error correction is carried out again without unpacking and changing the lines, and the error correction is convenient.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a block diagram of an embodiment of a fault-tolerant cable connection arrangement according to the present invention;
FIG. 2 is a block diagram of another embodiment of a cable connection fault-tolerant connection device according to the present invention;
FIG. 3 is a diagram of a switch device according to an embodiment of the present invention;
fig. 4 is a flowchart of a cable connection fault-tolerant connection method according to an embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a cable connection fault-tolerant connecting device.
Example 1
Referring to fig. 1, a cable connection fault-tolerant connection device includes a main board card, where a first processor is disposed on the main board card, the first processor is connected to an upper device through a first port group, and the upper device is disposed on the main board card; said first processor configuring a set of second port groups inheriting said first port group; the second port group is connected with a switch device, the switch device is connected with the first processor through an I2C bus, and the switch device is connected with a first connector; in a specific implementation process, referring to fig. 3, the switch device configures a plurality of uplink port groups, where the uplink port groups are connected to second port groups in the second port groups one by one, the uplink port groups are connected to a switch chip, the switch chip is connected to one downlink port group, the downlink port group is connected to the first connector, the first connector is connected to the second connector, and the second connector is connected to the daughter board card;
the first connector is provided with an additional first check code channel, and the second connector is provided with a second check code channel connected with the first check code channel; the first processor is connected with a first storage unit, and one feasible first storage unit is an EEPROM; the first processor is connected with the first check code channel through a port; the second check code channel is connected with a second processor, the second processor is connected with a second storage unit, and one possible second storage unit is an EEPROM; the second processor is electrically connected with a counter, and the counter is electrically connected with the first processor. One possible first processor and second processor is an FPGA.
In a specific implementation, any one of the second port groups maps to a unique first port group of the first port group.
In a specific implementation process, the first storage unit stores the first check code, and the second storage unit stores the second check code.
In a specific implementation process, any second port group in the second port group is connected to a unique upstream port group of the switch device, any upstream port group may be selectively connected to a downstream port group of the switch device, and the downstream port group is connected to the first connector.
Example 2
Embodiment 2 is implemented on the basis of embodiment 1, and as shown in fig. 2, the first processor is configured with a plurality of second port groups inheriting the first port groups, each of the second port groups is connected to a switch device, each of the switch devices is connected to a first connector, each of the first connectors is connected to a second connector, the plurality of second connectors are disposed on a daughter board, the daughter board is configured with second processor connectors, the second processor is connected to a second storage unit, the second processors are respectively connected to second parity channels of the second connectors, the second processors are respectively connected to counters, the number of the counters is equal to the number of the switch devices, and the counters are respectively connected to the first processors.
Referring to fig. 4, the present invention further provides a fault-tolerant connection method for cable connection, which is applied to the fault-tolerant connection device for cable connection, and includes:
s100, configuring a unique first check code for any first port group in a first port group, and configuring a second check code capable of checking the first check code for a second connector; in a specific implementation process, configuring a unique first check code for any one first port group in the first port group includes:
configuring and recording a first mapping relation of the relation between the communication signal and the first check code; the communication signal is a communication signal transmitted to a first port group by an upper device connected to the first port group of the first processor, and the communication signal transmitted to any one of the first port groups is different from the communication signals of the remaining other first port groups; the first check code is a set of binary numbers.
And storing the first mapping relation in the first storage unit.
Configuring a second connector with a second verification code capable of verifying the first verification code comprises:
configuring a second mapping relationship of the second check code channel to a second check code relationship,
and pre-storing the second mapping relation to the second storage unit. The second check code is a set of binary numbers, and the first check code and the second check code which can be checked by the second processor to pass are identical in value.
S200, the first processor controls any switch device to enable one group of second ports to be communicated with the second connector; in a specific implementation process, during initialization, an initial value of a counter connected to the first processor is 1, the counter sends the initial value 1 to the first processor, the processor selects a first uplink port group selection signal according to 1 and sends the first uplink port group selection signal to the switch device through I2C, and a switch chip of the switch device executes the first uplink port group selection signal to enable the first uplink port group to be communicated with the downlink port group.
And S300, the first processor acquires a first check code of a first port group corresponding to the second port group in S200, transmits the first check code to a first check code channel of the first connector through a check code transmitting port, and transmits the first check code to the second processor through a second check code channel of the second connector.
Wherein, the obtaining, by the first processor, the first check code of the first port group corresponding to the second port group includes:
the upper device sends different communication signals to any one of the first port groups,
the first processor acquires the communication signal, acquires the first mapping relation from the first storage unit, and acquires a corresponding first check code from the first mapping relation according to the communication signal.
S400, the second processor determines a second connector for forwarding the first check code and acquires a second check code according to the second connector; wherein the second processor obtaining the second parity code comprises:
the second processor determines a second check code channel for acquiring the first check code, and the second processor acquires the second mapping relation;
and the second processor acquires the second check code according to the second check code channel and the second mapping relation.
S500, the second processor verifies the second check code and the first check code; and the second processor compares whether the first check code and the second check code are the same or not, if so, the verification is passed, and the switch keeps the connection state of the existing uplink port group and the existing downlink port group.
And if the two port groups are different, the verification fails, and the first processor controls the switch to switch the uplink port groups so that the remaining second port groups are sequentially connected with the first connector and verified until the verification passes. Specifically, if the verification fails, the second processor sends a counting signal to a counter, after the counter receives the counting signal, 1 is added on the basis of the original counting of the counter to obtain new counting information, and the counter sends the new counting information to the first processor; and the first processor selects the next uplink port group selection signal according to the new counting information and sends the next uplink port group selection signal to the switch device through I2C, and a switch chip of the switch device executes the next uplink port group selection signal to connect the next uplink port group with the downlink port group. And the first processor transmits the first check code of the second port group corresponding to the next uplink port group to the second processor, the second processor verifies the new first check code and the new second check code, and if the new first check code and the new second check code fail to pass, the steps are repeated. Wherein an upstream port select signal in the first processor is capable of traversing all upstream port groups of the switch device.
Wherein, the processor mentioned in the detailed description represents a field programmable gate array; EEPROM stands for electrically erasable and programmable read only memory.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It should be noted that in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A cable connection fault-tolerant connecting device comprises a main board card and at least one daughter board card connected with the main board card, and is characterized in that the main board card is provided with at least one first processor, the daughter board card is provided with at least one second processor, wherein,
the first processor is connected with an upper device through a first port group; the first processor configuring at least one second port group inheriting the first port group; any one of said second port groups is connected to a switch device,
the switch device is connected with the first processor through an I2C bus, and the switch device is connected with a first connector; the first connector is connected with a second connector, and the second connector is configured on the daughter board card;
the first connector is provided with a first check code channel, and the second connector is provided with a second check code channel connected with the first check code channel;
the first processor is connected with the first storage unit; the first processor is connected with the first check code channel through a port; the second check code channel is connected with a second processor, and the second processor is connected with a second storage unit; the second processor is electrically connected with the corresponding first processor.
2. The cable connection fault-tolerant connection device of claim 1, wherein the second processor is electrically connected to a counter, the counter being electrically connected to the first processor.
3. The cable connection fault-tolerant connection arrangement of claim 1, wherein any one of the second port groups maps a unique first port group of the first port group.
4. The fault-tolerant connection arrangement according to claim 1, wherein any one of the first port groups is configured with a unique first check code, the first storage unit stores the first check code, any one of the second connectors is configured with a unique second check code, and the second storage unit stores the second check code.
5. The cable connection fault-tolerant connection device of claim 1, wherein any second port group in the second port group is connected with a unique upstream port group of the switch device, any upstream port group can be selectively connected with a downstream port group of the switch device, and the downstream port group is connected with the first connector.
6. A fault-tolerant connection method for cable connection, applied to the fault-tolerant connection device for cable connection according to any one of claims 1 to 4, comprising:
s100, configuring a unique first check code for any first port group in a first port group, and configuring a second check code capable of checking the first check code for a second connector;
s200, the first processor controls any switch device to enable one group of second ports to be communicated with the second connector;
s300, the first processor acquires a first check code of a first port group corresponding to a second port group in S200 and transmits the first check code to the second processor;
s400, the second processor determines a second connector for forwarding the first check code and acquires a second check code according to the second connector;
s500, the second processor verifies the second check code and the first check code;
and if the verification is not passed, the first processor controls the switch to switch the uplink port groups so that the rest second port groups are sequentially connected with the first connector and are verified until the verification is passed.
7. The method of claim 6, wherein configuring a unique first check code for any of the first port groups comprises:
configuring a first mapping relation for recording the relation between the communication signal and the first check code,
storing the first mapping relation in the first storage unit;
the obtaining, by the first processor, the first check code of the first port group corresponding to the second port group includes:
the upper device sends different communication signals to any one of the first port groups,
the first processor obtains the communication signal and a first mapping relation, and the first processor obtains a corresponding first check code from the first mapping relation according to the communication signal.
8. The cable connection fault-tolerant connection method of claim 6, wherein the first processor transmits an upstream port group selection signal to the switch device through an I2C bus, and the switch device controls a corresponding upstream port group to be communicated with a downstream port group according to the selection signal, so that a group of second ports is communicated with the second connector; any one uplink port group selection signal controls a unique uplink port group to be connected to a downlink port group, and all uplink port group selection signals can traverse an uplink port group.
9. The cable connection fault-tolerant connection method according to claim 6, wherein the second processor checks that the first check code and the second check code fail, the second processor sends a counting signal to a counter, and the counter receives the counting signal to count and sends counting information to the first processor; and the first processor selects a corresponding uplink port group selection signal according to the counting information and sends the signal to the switch device through I2C.
10. The cable connection fault-tolerant connection method of claim 6, wherein configuring a second connector with a second check code capable of checking the first check code comprises:
configuring a second mapping relationship of the second check code channel to a second check code relationship,
the second mapping relation is stored in a second storage unit;
the second processor obtaining the second check code comprises:
the second processor determines a second check code channel for obtaining the first check code, the second processor obtains the second mapping relationship,
and the second processor acquires the second check code according to the second check code channel and the second mapping relation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010925311.4A CN112100109B (en) | 2020-09-06 | 2020-09-06 | Cable connection fault-tolerant connection device and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010925311.4A CN112100109B (en) | 2020-09-06 | 2020-09-06 | Cable connection fault-tolerant connection device and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112100109A true CN112100109A (en) | 2020-12-18 |
| CN112100109B CN112100109B (en) | 2022-06-21 |
Family
ID=73757802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010925311.4A Active CN112100109B (en) | 2020-09-06 | 2020-09-06 | Cable connection fault-tolerant connection device and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112100109B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110048A (en) * | 2007-08-22 | 2008-01-23 | 杭州华三通信技术有限公司 | Device for implementing function of mistake examination and correction |
| CN105933097A (en) * | 2016-04-20 | 2016-09-07 | 上海斐讯数据通信技术有限公司 | Testing method and system based on serial port communication |
| CN109416677A (en) * | 2016-07-22 | 2019-03-01 | 英特尔公司 | Support the technology of a variety of interconnection agreements for one group of public interconnecting connector |
-
2020
- 2020-09-06 CN CN202010925311.4A patent/CN112100109B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101110048A (en) * | 2007-08-22 | 2008-01-23 | 杭州华三通信技术有限公司 | Device for implementing function of mistake examination and correction |
| CN105933097A (en) * | 2016-04-20 | 2016-09-07 | 上海斐讯数据通信技术有限公司 | Testing method and system based on serial port communication |
| CN109416677A (en) * | 2016-07-22 | 2019-03-01 | 英特尔公司 | Support the technology of a variety of interconnection agreements for one group of public interconnecting connector |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112100109B (en) | 2022-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111289922B (en) | Cable plugging detection method and related equipment | |
| US11748218B2 (en) | Methods, electronic devices, storage systems, and computer program products for error detection | |
| CN110824387B (en) | Device and method for detecting cable connection | |
| CN100465969C (en) | Method and apparatus for the automatic correction of faulty wires in a logic simulation hardware emulator / accelerator | |
| CN101661453B (en) | Method for identifying blade sequence number in blade server | |
| CN111176913A (en) | Circuit and method for detecting Cable Port in server | |
| CN112100109B (en) | Cable connection fault-tolerant connection device and method | |
| US20170293545A1 (en) | Redundant cable routing management in storage systems | |
| CN111290891B (en) | Computer system and method for testing computer system | |
| CN116662241A (en) | Computer backboard interface address matching system and method | |
| US11854577B2 (en) | Hard disk device simulator, testing system using hard disk device simulators and testing method thereof | |
| CN115480975A (en) | Wiring checking method and device | |
| CN115951266A (en) | Computing system | |
| CN115729872A (en) | Computing device and detection method for PCIE cable connection | |
| US9742654B1 (en) | Communication interface testing | |
| US7409618B2 (en) | Self verifying communications testing | |
| US6901538B2 (en) | Method, system, and recording medium of testing a 1394 interface card | |
| CN117667818B (en) | Signal transmission structure, server and signal transmission method | |
| CN109542702A (en) | A kind of test equipment and test method | |
| TW202113385A (en) | Boundary scan test system and method thereof | |
| US20140129909A1 (en) | Switchable per-lane bit error count | |
| CN114218030B (en) | CPU test method and device | |
| US11500717B2 (en) | Method for detecting data storage system, device and data storage system | |
| CN112462246A (en) | Boundary scan test system and method thereof | |
| CN113407394A (en) | Method, device, equipment and medium for server RAS function test |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |