CN101110048A - Device for implementing function of mistake examination and correction - Google Patents
Device for implementing function of mistake examination and correction Download PDFInfo
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Abstract
The utility model discloses a device with the function of error check and correction. The device comprises a memory controller on the single board, a dual inline memory module (DIMM) and an error check and correction (ECC) unit on the single board. The memory controller is used to output the ECC check code corresponding to the data written into the DIMM to the ECC unit through the written instruction in the process of writing the data into the DIMM; when reading the data from the DIMM, the ECC check code corresponding to the data can be obtained from the ECC unit through the reading instruction. The ECC unit is used to store the ECC check code as per the written instruction and to output the ECC check code to the memory controller through the reading instruction. The utility model can make the ECC come true in the processor, even if the DIMM doesn't support the ECC function.
Description
Technical field
The present invention relates to memory techniques, particularly relate to a kind of error checking and device of correcting function realized.
Background technology
Internal memory is that processor system institute is requisite, such as, the processor system of common PC, notebook computer, server, datacom device and some consumer products.The capacity of internal memory, access speed and stability are the important indicators of processor system performance.
At present, for internal memory allocating method more flexibly is provided to processor system, internal memory is present in the processor system in the memory bar mode usually.That is to say, on the one hand, dynamic RAM (the DRAM of actual storage function will be finished, Dynamic Random access memory) chip is integrated on the printed circuit board (pcb) with standard external interface, form dual inline type internal memory module (DIMM, Dual In-line Memory Module), it is usually said memory bar, on the other hand, the DIMM connector is set on the veneer of processor system, then, DIMM is inserted the DIMM connector of veneer, make that the Memory Controller Hub on the veneer can carry out read and write access to the DIMM that inserts veneer in the processor system.
In processor system, error checking and correction (ECC, Error Check﹠amp; Correct) function is a kind of critical function that guarantees data reliability.Fig. 1 is an apparatus structure synoptic diagram of realizing the ECC function in the prior art.Referring to Fig. 1, because present DIMM can be divided into DIMM that supports the ECC function and the DIMM that does not support the ECC function, therefore, when in processor system, realizing the ECC function, must use the DIMM that supports the ECC function, certainly, the Memory Controller Hub on the veneer also needs to support the ECC function, and the interface signal between each DIMM of Memory Controller Hub and support ECC function can be divided into following several types according to its characteristics:
Clock signal group CK to each DIMM output, provides the work clock of DIMM by Memory Controller Hub, guarantees the clock synchronization of processor system;
Address command signal group ADDR/CMD to each DIMM output, is used for specific address and command information when DIMM provides read-write operation by Memory Controller Hub;
Control signal group CTL, is used for to concrete read operation or the write operation of DIMM indication to each DIMM output by Memory Controller Hub;
Data signal group DQ is exported to the other side respectively by Memory Controller Hub and each DIMM, is used to finish the transmission of data between Memory Controller Hub and DIMM;
ECC data signal group CB is exported to the other side respectively by Memory Controller Hub and each DIMM, is used to finish the transmission of ECC check code between Memory Controller Hub and DIMM.
Referring to Fig. 1, the process of existing techniques in realizing ECC function mainly comprises: when needs are saved in data in the internal memory, Memory Controller Hub is indicated concrete write operation and the pairing DIMM of write operation space by ADDR/CMD signal and CTL signal to DIMM, the data that to store by the DQ signal wire output to the storage space among the corresponding DIMM then, simultaneously, Memory Controller Hub also generates corresponding ECC check code at the data of this storage, by the CB signal line ECC check code is outputed to DIMM; When needs from internal memory during reading of data, Memory Controller Hub is indicated concrete read operation and the pairing DIMM of read operation space by ADDR/CMD signal and CTL signal to DIMM, DIMM exports to Memory Controller Hub by the DQ signal wire with the data of correspondence, simultaneously, the ECC check code of the data correspondence that DIMM also reads this, output to Memory Controller Hub by the CB signal line, Memory Controller Hub is according to the ECC check code that receives from the CB signal line, the data that read from the DQ signal wire are carried out verification, there is mistake if judge the data that read, then can carries out error correction and handle.
By above description as can be seen, the ECC function is a kind of critical function that guarantees data reliability in processor system, in the prior art, when realizing the ECC function in processor system, must use the DIMM that supports the ECC function.But, in the business realizing of reality,, support that the common price of DIMM of ECC function is comparatively expensive, or volume is bigger with respect to the DIMM that does not support the ECC function.When the space of processor system narrow and small, need to use the less DIMM of profile, perhaps, because consideration for cost, when needing to use cheap DIMM, then can only select the DIMM that does not support the ECC function for use, but but make processor system can't realize the ECC function this moment, reduce QoS.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of error checking and device of correcting function realized,, also can in processor system, realize the ECC function so that do not rely on the ECC function of DIMM.
In order to achieve the above object, technical scheme of the present invention is achieved in that
A kind of error checking and device of correcting function realized comprises: the Memory Controller Hub on the veneer, dual inline type internal memory module DIMM and be arranged on ECC performance element on the veneer, wherein,
Memory Controller Hub, be used for when data are write DIMM, export the ECC performance element to by writing the ECC check code that instruction will be corresponding with the data that write DIMM, when reading of data from DIMM, from the ECC performance element, obtain the ECC check code corresponding with the data that read by reading command;
The ECC performance element is used for preserving the ECC check code according to writing instruction, and exports the ECC check code according to reading command to Memory Controller Hub.
This shows, in the present invention, the ECC performance element of preserving the ECC check code is arranged on the veneer, and unlike being integrated in the prior art on the DIMM, therefore, even DIMM does not support the ECC function, promptly do not rely on the ECC function of DIMM, processor system also can utilize the cooperation of the ECC performance element on DIMM and the veneer to realize the ECC function, thereby has improved QoS, makes the present invention have very strong practicality.
In addition, when the present invention has further proposed the ECC performance element is set on veneer, signal topology mode between Memory Controller Hub, DIMM and the ECC performance element three of processor system, this signal topology mode can minimum signal branch, and provided rational build-out resistor position, thereby reduced line reflection; Simultaneously, this signal topology mode is the balanced load design, and therefore the delay inequality of propagating between the signal in can the minimizing group, has improved the signal quality of processor system greatly, has further strengthened practicality of the present invention.
Description of drawings
Fig. 1 is an apparatus structure synoptic diagram of realizing the ECC function in the prior art.
Fig. 2 is that the device of the realization ECC function that proposes of the present invention is formed synoptic diagram.
Fig. 3 inserts as a plurality of DIMM to realize when veneers and each DIMM comprise 2 physics Rank that the device of ECC function forms connection diagram in one embodiment of the invention.
Fig. 4 is the topological mode synoptic diagram of control signal wire CTL in one embodiment of the invention.
Fig. 5 is the topological mode synoptic diagram of address command signal line ADDR/CMD in one embodiment of the invention.
Fig. 6 is the topological mode synoptic diagram of clock cable CK in one embodiment of the invention.
Fig. 7 is the topological mode synoptic diagram of data signal line DQ and ECC data signal line CB in one embodiment of the invention.
Fig. 8 is a synoptic diagram of realizing the DRAM of ECC unit in one embodiment of the invention.
Fig. 9 is the synoptic diagram of the shared system space of the DIMM of use band ECC function in one embodiment of the invention and the way that two kinds of realizations of ECC performance element ECC function is set on veneer.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with drawings and the specific embodiments.
The present invention proposes a kind of device of the ECC of realization function.Fig. 2 is that the device of the realization ECC function that proposes of the present invention is formed synoptic diagram.Referring to Fig. 2, this device mainly comprises: the Memory Controller Hub on the veneer, DIMM and be arranged on ECC performance element on the veneer, wherein,
Memory Controller Hub, be used for when data are write DIMM, export the ECC performance element to by writing the ECC check code that instruction will be corresponding with the data that write DIMM, when reading of data from DIMM, from the ECC performance element, obtain the ECC check code corresponding with the data that read by reading command;
The ECC performance element is used for preserving the ECC check code according to writing instruction, and exports the ECC check code according to reading command to Memory Controller Hub.
Referring to Fig. 2, the DIMM in apparatus of the present invention is identical with the function of DIMM in the prior art, promptly, when Memory Controller Hub need be preserved data, receive the instruction that writes of Memory Controller Hub output, write instruction according to this, the data that Memory Controller Hub is exported are saved in corresponding memory space among the DIMM; When Memory Controller Hub needs reading of data, receive the reading command of Memory Controller Hub output, according to this reading command, export the data of preserving in the corresponding stored space among the DIMM to Memory Controller Hub.
In apparatus of the present invention, Memory Controller Hub receives in processing and the prior art behind the ECC check code of ECC performance element output identical, promptly, Memory Controller Hub is according to the ECC check code that receives, the data that read from DIMM are carried out verification, there is mistake if verification goes out the data that read, then can carries out error correction and handle, thus the reliability of assurance data.
As seen, no matter whether DIMM supports the ECC function, and apparatus of the present invention all can utilize the ECC performance element that is provided with on veneer to realize the ECC function.
Fig. 3 inserts as a plurality of DIMM to realize when veneers and each DIMM comprise 2 physics Rank that the device of ECC function forms connection diagram in one embodiment of the invention.Referring to Fig. 3, in one embodiment of the invention, when a plurality of DIMM are connected on the veneer by the DIMM connector, in order to guarantee that further Memory Controller Hub all can carry out the ECC verification to the data that each DIMM preserves, guarantee the reliability of each DIMM storage data, the present invention can be arranged on the quantity of the ECC performance element on the veneer according to the quantity of DIMM, and each DIMM all has corresponding ECC performance element.In addition, in actual applications, a DIMM can comprise 1 or 2 physical column (Rank), each physics Rank comprises all integrated DRAM on side of DIMM, Memory Controller Hub is when carrying out a read-write operation to DIMM, be that a physics Rank at DIMM carries out, that is to say, Memory Controller Hub sends in single job writes instruction or reading command at physics Rank among the DIMM, correspondingly, the ECC check code of this operation correspondence is also at physics Rank among the DIMM.Therefore, in the present invention, can also further be arranged on the quantity of the ECC performance element on the veneer according to the quantity of physics Rank among the DIMM, and, all corresponding ECC performance element of each the physics Rank among each DIMM.
Therefore, referring to Fig. 3, when a plurality of DIMM insert veneers and each DIMM and comprise 2 physics Rank, all can be the separately corresponding ECC performance element of each physics Rank of each DIMM, such as, the ECC performance element corresponding among Fig. 3 with the physics Rank 0 of DIMM 0, be designated DIMM 0 Rank 0 ECC among the figure, the ECC performance element corresponding with the physics Rank 1 of DIMM 0, be designated DIMM 0 Rank 1 ECC among the figure, the ECC performance element corresponding with the physics Rank 0 of DIMM 1 is designated DIMM 1 Rank 0 ECC among the figure, the ECC performance element corresponding with the physics Rank 1 of DIMM 1 is designated DIMM 1 Rank 1 ECC among the figure.
Because being used to preserve the ECC performance element and the DIMM of ECC check code in apparatus of the present invention is separated from each other, and the ECC performance element is arranged on the veneer, therefore, between Memory Controller Hub, ECC performance element and the DIMM connection of various signal wires then with prior art in different.To comprise in the processor system that a plurality of DIMM and each DIMM comprise that 2 physics Rank are example, the signal wire connected mode between Memory Controller Hub, ECC performance element and the DIMM is:
First, in order to guarantee the operate as normal of DIMM and ECC performance element, Memory Controller Hub must provide clock signal to DIMM and ECC performance element, guarantee the clock synchronization of entire process device system, and, Memory Controller Hub also must provide control signal and address command signal to DIMM and ECC performance element, guarantee that DIMM and ECC performance element can be according to control signal and address command signals, the indicated concrete instruction that writes when obtaining Memory Controller Hub and writing data, and indicated concrete reading command during the Memory Controller Hub reading of data, thereby determine concrete read-write operation, and the related storage space of read-write operation.Therefore, between Memory Controller Hub and DIMM and ECC performance element, all need connection control signal line CTL, address command signal line ADDR/CMD and clock cable.
At first, for control signal wire CTL, each physics Rank of each DIMM all needs to take separately a control signal wire of drawing from Memory Controller Hub, and each ECC performance element also needs to take control signal wire, in Fig. 3, physics Rank 0 among the DIMM 0 and corresponding ECC performance element DIMM 0 Rank 0 ECC thereof take control signal wire CTL0_0, and physics Rank1 among the DIMM 0 and corresponding ECC performance element DIMM 0 Rank 1 ECC thereof take control signal wire CTL0_1.
Secondly, for address command signal line ADDR/CMD, all physics Rank and all the ECC performance elements of all DIMM can be shared, as shown in Figure 3.
At last, for clock cable CK, each physics Rank of each DIMM all takies a clock cable of drawing from Memory Controller Hub, and each ECC performance element also needs to take clock cable, in Fig. 3, the physics Rank 0 of DIMM 0 takies clock cable CK0_0, and the physics Rank 1 of DIMM 0 takies clock cable CTL0_2, and the ECC performance element of the physics Rank 0 of DIMM 0 and physics Rank1 correspondence takies clock cable CTL0_1.
Certainly, it may occur to persons skilled in the art that,, can utilize the mode that in apparatus of the present invention, increases zero propagation clock buffer device that more clock signal is provided if Memory Controller Hub can't be exported enough clocks.
The second, as shown in Figure 3, with identical in the prior art,, all be connected with the data signal line DQ that is used to transmit data between Memory Controller Hub and each DIMM in order in DIMM, to carry out the data write operation.
Three, for the ECC check code can be transmitted, as shown in Figure 3, all be connected with ECC data signal line CB between Memory Controller Hub and each the ECC performance element between Memory Controller Hub and ECC performance element.
In the business realizing of reality, signal quality need relate to by suitable topology and mate and guarantees, expect high-quality signal, must make that then the signal topology is simple as far as possible, balance.Therefore, in order to obtain high-quality signal, the preferable signal wire topology mode that apparatus of the present invention adopted is:
For control signal wire CTL, because each physics Rank need take a control signal wire, and the corresponding read-write mode of ECC performance element and its corresponding physical Rank is identical, write instruction and reading command on the same control signal wire that can the shared drive controller sends, therefore, in order to simplify the signal topology, a physics Rank and corresponding ECC performance element thereof take the same control signal wire of drawing from Memory Controller Hub among the DIMM.As shown in Figure 4, control signal wire is at Memory Controller Hub, topological mode between the ECC performance element three of any one physics Rank among any one DIMM and correspondence thereof is: physics Rank 0 and corresponding ECC performance element 0_0 thereof with DIMM 0 are example, the control signal wire of drawing from Memory Controller Hub is connected to a pin 0 of DIMM 0 connector, the physics Rank 0 of DIMM 0 is by this pin 0 connection control signal line, and, control signal wire is drawn from the via hole of this pin 0, draw a road be among Fig. 4 circuit TL1 place a road, be connected to the ECC performance element 0_0 corresponding with physics Rank 0, in addition, in order to guarantee quality of signals, minimum signal branch, another road of drawing is one tunnel connection Signal Terminal build-out resistor at circuit TL2 place among Fig. 4, and this Signal Terminal build-out resistor is connected to the VTT power supply.
For address command signal line ADDR/CMD, because all DIMM and all ECC performance elements can be shared, therefore, in order to simplify the signal topology, as shown in Figure 5, the address command signal line is at Memory Controller Hub, topological mode between the ECC performance element three of physics Rank among any one DIMM and correspondence thereof is: with DIMM 0 and corresponding ECC performance element thereof is example, the described address command signal line of drawing from described Memory Controller Hub is connected to a pin 1 of DIMM 0 connector, all physics Rank among the DIMM 0 are all by this pin 1 link address command signal line, and, the address command signal line is drawn from the via hole of this pin 1, draw a road be among Fig. 5 the TL1 place a road, be connected to all ECC performance elements corresponding with all physics Rank among the DIMM 0, comprise that with DIMM 0 physics Rank 0 and physics Rank 1 are example, after a road of TL1 place further is divided into the branch of two TL2 such as long transmission line such as grade, connect the ECC performance element 0_0 and the ECC performance element 0_1 of physics Rank 0 and physics Rank 1 correspondence respectively; In order to guarantee quality of signals, minimum signal branch, another road of drawing promptly among Fig. 5 a road of the TL3 place, is connected to pull-up resistor.
For clock signal C K, realize the output of multipath clock signal to utilize the zero propagation clock buffering buffer device that increases in apparatus of the present invention, and it is example that each DIMM and each ECC performance element take a clock cable respectively, as shown in Figure 6, clock cable is at Memory Controller Hub, zero propagation clock buffering buffer device, topological mode between the ECC performance element three of physics Rank among any one DIMM and correspondence thereof is: with DIMM 0 and corresponding ECC performance element thereof is example, Memory Controller Hub by and zero propagation clock buffer device between a clock cable clock signal C K is outputed to zero propagation clock buffer device, zero propagation clock buffer device drive goes out the multipath clock signal CK of the clock signal zero propagation of exporting with described Memory Controller Hub, comprise that with DIMM 0 physics Rank 0 and physics Rank 1 are example, the physics Rank 0 of DIMM 0 receives the road clock signal C K that drives out respectively with physics Rank 1 by different clock cables, and ECC performance element 0_0 and the ECC performance element 0_1 corresponding with physics Rank 0 among the DIMM 0 and physics Rank 0 receive independent one tunnel clock signal C K that drives out, be a road of TL0 and TL1 place, particularly, after needing further a road of TL0 and TL1 place to be divided into the branch of long transmission line TL2 such as two, connect the ECC performance element 0_0 and the ECC performance element 0_1 of physics Rank 0 and physics Rank 1 correspondence respectively.In order to guarantee the quality of clock signal, minimum signal branch, no matter be directly by the Memory Controller Hub clock signal, still above-mentioned zero propagation clock buffering buffer device clock signal, referring to Fig. 6, the clock signal that two ECC performance elements of the physics Rank 0 of DIMM 0 and physics Rank 1 correspondence are received outputs to the build-out resistor between these two ECC performance elements simultaneously, just, need further a road of TL0 and TL1 place to be differentiated one the tunnel, be among Fig. 6 the TL3 place a road, be connected to build-out resistor.
For data signal line DQ, need not to be connected to the ECC performance element owing to only being connected to DIMM, therefore, when the signal topology design, the respective pins that directly will be connected to from the data signal line DQ that Memory Controller Hub is drawn on the connector of each DIMM gets final product.
For ECC data signal line CB, owing to only need be connected to the ECC performance element need not to be connected to DIMM, therefore, as shown in Figure 7, when the signal topology design, a kind of topological mode preferably is: the ECC performance element that need use for a DIMM, the ECC data signal line CB that draws from Memory Controller Hub behind a build-out resistor R2, by different circuit branch promptly two circuit branches at two TL2 places be connected respectively to this DIMM in two two ECC performance elements that physics Rank is corresponding.
Need to prove, when described ECC performance element is that each DRAM integrated among second generation Double Data Rate DDR2DRAM and the DIMM is during also for DDR2 DRAM, because DDR2DRAM inside has been integrated with the terminal build-out resistor, can guarantee the quality of ECC data-signal, therefore, need not in the signal topological diagram shown in Figure 7 is that two ECC performance elements increase the terminal build-out resistor.And when described ECC performance element be each DRAM integrated among Double Data Rate DDR DRAM and the DIMM during also for DDR DRAM, then need be that two ECC performance elements increase the terminal build-out resistors in signal topological diagram shown in Figure 7.As shown in Figure 7, the described ECC data signal line CB that draws from described Memory Controller Hub further is connected to the pull-up resistor of TL3 place circuit before build-out resistor R2.
After apparatus of the present invention adopt above-mentioned signal topology mode, following advantage is arranged:
1, line reflection is reduced in the branch of minimum signal, rational build-out resistor position;
2, every kind of signal topology is balanced load, can the minimizing group between the signal propagation delay poor;
3, distinguish preceding cabling TL0 of DIMM connector and cabling afterwards.The isometric cabling of TL0 line segment of every kind of signal, the track lengths of TL1, TL2, TL3 then can design with reference to the length of arrangement wire of used DIMM, has made things convenient for wires design.
Need to prove, in apparatus of the present invention, for with DIMM in the bit wide of integrated DRAM mate mutually, as shown in Figure 8, each ECC performance element all can utilize the DRAM of one 8 bit bit wide to realize, perhaps utilizes the DRAM of two 4 bit bit wides to realize, and, be used to realize the DRAM of ECC performance element, be designated as DRAM1, need meet the following conditions:
The number of the logic Bank of DRAM1 equals the number of the logic Bank of corresponding DIMM;
And/or the velocity stage of DRAM1 is not less than the velocity stage of corresponding DIMM;
And/or when the frequency of operation of DRAM1 equaled the frequency of operation of corresponding DIMM, CAS signal output delay (CL) maximal value of DRAM1 was not more than the CL maximal value of corresponding DIMM;
And/or when the DRAM1 that adopts one 8 bit bit wide realized the ECC performance element, the memory capacity of this DRAM1 equaled 1/8 of a corresponding physics Rank capacity; When the DRAM1 that adopts two 4 bit bit wides realized the ECC performance element, the memory capacity of each DRAM1 equaled 1/16 of a corresponding physics Rank capacity.
Hypothesis adopts a DDR2 SODIMMRaw Card A who meets " (Unbuffered PC2-4200/3200DDR2 SDRAM SO-DIMM Reference Design Specification " of JEDEC issue to save as example in designing below, describes in detail to adopt above-mentioned signal topology mode to realize the line process of walking in apparatus of the present invention.
The output timing of Memory Controller Hub can be regulated by register.DDR2 SODIMM Raw Card A is a two Rank DIMM, does not support the ECC function, uses the ECC performance element of the DDR2SDRAM of two 8bit as correspondence on veneer.
Suppose pcb board material selection use FR4, thick 0.5 ounce of internal layer copper, and the hypothesis cabling substantially all is a PCB internal layer cabling, number of vias is few as far as possible on the every signal wire, preferably be no more than two, so referring to Fig. 4 to Fig. 7, when signal adopted topological mode as indicated above, the length of every section cabling can be by following parameter area design.
Control signal CTL cabling is recommended:
| Line segment | TL0 | TL1 | TL2 | R |
| Length (inch) | 1.9-4.5 | 2.2-2.4 | 0.2-0.5 | (22-56)Ω±5％ |
Address command signal ADDR/CMD cabling is recommended:
| Line segment | TL0 | TL1 | TL2 | TL3 | R |
| Length (inch) | 1.9-4.5 | 2.2-2.4 | 0.1-0.2 | 0.2-0.5 | (22-56)Ω±5％ |
Clock signal C K cabling is recommended:
| Line segment | TL0 | TL1 | TL2 | TL3 | R1 |
| Length (inch) | 1.9-4.5 | 1.0-1.2 | 0.1-0.13 | 0.3-0.4 | 100Ω±5％ |
Data-signal DQ and ECC data-signal CB cabling are recommended:
| Line segment | TL0 | TL1 | TL2 | R2 |
| Length (inch) | 1.9-4.5 | 0.44-0.46 | 0.07-0.08 | 22Ω±5％ |
Basic wiring rule is:
All signal single-ended impedance are controlled to be 50 Europe, and differential impedance is controlled to be 100 Europe
The CK signal: differ between differential lines in the 10mil, differ between differential pair in the 25mil, differential clocks between satisfy the 3H principle, with other signals at a distance of more than the 20mil.
The CTL signal: isometric cabling, differ in the 20mil, distance between centers of tracks 12-15mil, with other signals at a distance of more than the 20-25mil.
The ADDR/CMD signal: isometric cabling, differ in the 20mil, distance between centers of tracks 12-15mil, with other signals at a distance of more than the 20-25mil.
CB signal: isometric cabling, differ in the 20mil, distance between centers of tracks 12-15mil, with other signals at a distance of more than the 20-25mil.
In addition, need to prove that when the processor system space was narrow and small, the way of using the present invention that the ECC performance element is set still can be saved system space than the way of the DIMM that uses the bigger band ECC function of volume on veneer.
When adopting the way of prior art, such as, use the DIMM such as the DDR2 UDIMM of the band ECC function of 25 degree oblique cuttings, and apparatus of the present invention use flat insert not with the DIMM such as the DDR2 SODIMM of ECC function, referring to shown in Figure 9, apparatus of the present invention are saved 36% PCB plane space than the way of prior art.From height, in apparatus of the present invention not the height with the DDR2SODIMM of ECC function have only 9.2mm, and the DDR2 UDIMM of the band ECC function of 25 degree oblique cuttings reaches as high as 19.49mm in the prior art way, highly reduce about 10mm, therefore, with respect to prior art, when realizing the ECC function, apparatus of the present invention can save system space.
In a word, the above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (13)
1. realize error checking and the device of correcting function for one kind, it is characterized in that, comprising: the Memory Controller Hub on the veneer, dual inline type internal memory module DIMM and be arranged on the veneer error checking with correct the ECC performance element, wherein,
Memory Controller Hub, be used for when data are write DIMM, export the ECC performance element to by writing the ECC check code that instruction will be corresponding with the data that write DIMM, when reading of data from DIMM, from the ECC performance element, obtain the ECC check code corresponding with the data that read by reading command;
The ECC performance element is used for preserving the ECC check code according to writing instruction, and exports the ECC check code according to reading command to Memory Controller Hub.
2. device according to claim 1 is characterized in that, described DIMM and described ECC performance element are corresponding one by one;
Described Memory Controller Hub when any one DIMM is carried out said write data and reading of data, exports said write instruction, reading command and ECC check code to the ECC performance element of this any one DIMM correspondence.
3. device according to claim 1 is characterized in that, described ECC performance element comprises: with the corresponding respectively ECC performance element of each physics Rank among the described DIMM;
Described Memory Controller Hub, the physics Rank of the described DIMM that relates to when writing data and reading of data exports said write instruction, reading command and ECC check code to the ECC performance element of this physics Rank correspondence.
4. device according to claim 1 is characterized in that, described ECC performance element is: the dynamic RAM DRAM of one 8 bit bit wide, the perhaps DRAM of two 4 bit bit wides.
5. device according to claim 4 is characterized in that the number of the logic Bank of described DRAM equals the number of the logic Bank of described DIMM;
And/or the velocity stage of described DRAM is not less than the velocity stage of described DIMM;
And/or when the frequency of operation of described DRAM equaled the frequency of operation of described DIMM, the maximal value of the CAS signal output delay CL of described DRAM was not more than the CL maximal value of described DIMM;
And/or when being the DRAM of one 8 bit bit wide, the memory capacity of this DRAM equals 1/8 of a physics Rank capacity; When being the DRAM of two 4 bit bit wides, the memory capacity of each DRAM equals 1/16 of a physics Rank capacity.
6. device according to claim 3 is characterized in that, described Memory Controller Hub is by control signal wire and address command signal line, to described ECC performance element output said write instruction and described reading command.
7. device according to claim 6, it is characterized in that, the described control signal wire of drawing from described Memory Controller Hub is connected to a pin of DIMM connector, the physics Rank of described DIMM is by this pin connection control signal line, and, described control signal wire is drawn from the via hole of this pin, that draws a road is connected to the corresponding ECC performance element of physics Rank that connects with described pin, another road of drawing connects the Signal Terminal build-out resistor, and this Signal Terminal build-out resistor is connected to power supply.
8. device according to claim 6, it is characterized in that, the described address command signal line of drawing from described Memory Controller Hub is connected to a pin of DIMM connector, all physics Rank of described DIMM are all by this pin link address command signal line, and, described address command signal line is drawn from the via hole of this pin, and that draws a road is connected to all ECC performance elements corresponding with all physics Rank among the described DIMM, and another road of drawing is connected to pull-up resistor.
9. device according to claim 3 is characterized in that, this device further comprises: zero propagation clock buffering buffer device;
Described Memory Controller Hub exports clock signal C K to zero propagation clock buffer device, zero propagation clock buffer device drive goes out the multipath clock signal CK of the clock signal zero propagation of exporting with described Memory Controller Hub, each physics Rank among the described DIMM receives the road clock signal C K that drives out respectively, and all ECC performance elements corresponding with all physics Rank among the described DIMM receive independent one tunnel clock signal C K that drives out.
10. according to claim 1 or 9 described devices, it is characterized in that, in described DIMM, comprise two physics Rank, and all ECC performance elements are when described Memory Controller Hub or zero propagation clock buffer device receive independent one tunnel clock signal C K,
The clock signal that two ECC performance elements of these two physics Rank correspondences are received outputs to the build-out resistor between these two ECC performance elements simultaneously.
11. device according to claim 3 is characterized in that, described Memory Controller Hub and described ECC performance element are carried out the mutual of described ECC check code by ECC data signal line CB.
12. device according to claim 11 is characterized in that, the described ECC data signal line CB that draws from described Memory Controller Hub is connected to all ECC performance elements corresponding with all physics Rank among the described DIMM after a build-out resistor.
13. device according to claim 12, it is characterized in that, when described ECC performance element was Double Data Rate DDR DRAM, the described ECC data signal line CB that draws from described Memory Controller Hub further was connected to pull-up resistor before described build-out resistor.
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| CNB2007101206374A CN100527091C (en) | 2007-08-22 | 2007-08-22 | Device for implementing function of mistake examination and correction |
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