CN102968355A - Intel Brickland-EX platform-based memory error correction method - Google Patents

Abstract

The invention provides an Intel Brickland-EX platform-based memory error correction method. According to the method, based on an ECC (Error Checking and Correction) technology, 16bit is reserved in ECC particles of a memory DRAM (Dynamic Random Access Memory) as a backup unit, and data errors from two different DRAM particles are simultaneously corrected by preparing to back up error DRAM particles at any time, so that the error correction efficiency is doubled, meanwhile, the transmission band width of a cache line is reduced, the probability of memory error can be reduced by 50 percent, and the reliability and the stability of the system are greatly improved.

Description

A kind of internal memory error correction method based on the Intel-Brickland-EX platform

Technical field

The present invention relates to the Computer Applied Technology field, specifically a kind of internal memory error correction method based on the Intel-Brickland-EX platform.

Background technology

In the application of modern service device, the reliability and stability of system are subject to increasing attention, especially in financial circles, and bank, military project, the fields such as scientific research, the user has very harsh requirement especially to Systems balanth.

As everyone knows, the most traditional internal memory error correction method is by extra parity code data to be carried out odd even to judge, thereby learns the correctness of data result; Afterwards the more advanced ECC error correcting technique of internal memory support again can use less and outer check code that data are carried out truly error correction; But the ECC technology can only be corrected the mistake that 1 bit data occurs.

Summary of the invention

The purpose of this invention is to provide a kind of method of strengthening the disk array reliability.

The objective of the invention is to realize in the following manner, based on the ECC error correcting technique, in the ECC of memory dram verification particle, reserve 16bit as backup units, and the mode of preparing that at any time the DRAM particle of makeing mistakes is backed up can correct the error in data from two different DRAM particles simultaneously, promotes 2 times error correction efficient; Reduce simultaneously the transmission bandwidth of cache line, reduced the probability that 50% internal memory is made mistakes, significantly improve the reliability and stability of system.Such idea is dropped into product design produce, will certainly bring very high practical value and commercial value

Error correction step is as follows:

1) arranges by BIOS, CPU cache line is torn open be two halves, to reduce the main memory access bus bandwidth, improve system reliability

2) in internal memory, mark off the address location that 16bit backups;

3) by the BIOS monitoring internal memory situation that reports an error, and error correction strategies is set, if single DRAM reports an error, then utilizes common ECC mechanism to carry out verification;

4) if simultaneously two DRAM report an error, then at first address and the data of the DRAM particle that makes a mistake all are copied in the 16bit backup units, and abandon this fault DRAM particle, then utilize common ECC mechanism to revise second DRAM mistake.

The invention has the beneficial effects as follows: the efficient highly reliable internal memory error correction method based on Intel Brickland-EX platform is based on the ECC error correcting technique, in the ECC of memory dram verification particle, reserve 16bit as backup units, and the mode of preparing that at any time the DRAM particle of makeing mistakes is backed up can correct the error in data from two different DRAM particles simultaneously, promotes 2 times error correction efficient; Reduce simultaneously the transmission bandwidth of cache line, reduced the probability that 50% internal memory is made mistakes, significantly improve the reliability and stability of system.Such idea is dropped into product design produce, will certainly bring very high practical value and commercial value.

Description of drawings

Fig. 1 is the cache line structural representation after splitting;

Fig. 2 is the process flow diagram of two DRAM mistakes of simultaneously error correction.

Embodiment

Explain below with reference to Figure of description method of the present invention being done.

A kind of efficient highly reliable internal memory error correction method based on Intel Brickland-EX platform of the present invention, CPU cache line to be torn open be two halves, reduce the main memory access bus bandwidth, and in the ECC of memory dram verification particle, reserve 16bit as backup units, the DRAM particle that replacement makes a mistake, recycling ECC mechanism is processed from second DRAM particle mistake, CPU is split as two by Memory Buffer with complete cache line: reserve 16bit as backup units in the ECC of memory dram verification particle, and the mode of preparing that at any time the DRAM particle of makeing mistakes is backed up can correct the error in data from two different DRAM particles simultaneously, promotes 2 times error correction efficient; Can reduce the probability that 50% internal memory is made mistakes; Reduce simultaneously the transmission bandwidth of cache line, reduced the probability that 50% internal memory is made mistakes, significantly improve the reliability and stability of system.

Except the described technical characterictic of instructions, be the known technology of those skilled in the art.

Claims (1)

1. internal memory error correction method based on the Intel-Brickland-EX platform, it is characterized in that the error correcting technique based on ECC, in the ECC of memory dram verification particle, reserve 16bit as backup units, and prepare at any time the mode that the DRAM particle of makeing mistakes backs up is corrected error in data from two different DRAM particles simultaneously, promote 2 times error correction efficient; Reduce simultaneously the transmission bandwidth of cache line, reduced the probability that 50% internal memory is made mistakes, significantly improve the reliability and stability of system, error correction step is as follows:

1) arranges by BIOS, CPU cache line is torn open be two halves, to reduce the main memory access bus bandwidth, improve system reliability

2) in internal memory, mark off the address location that 16bit backups;

3) by the BIOS monitoring internal memory situation that reports an error, and error correction strategies is set, if single DRAM reports an error, then utilizes common ECC mechanism to carry out verification;

4) if simultaneously two DRAM report an error, then at first address and the data of the DRAM particle that makes a mistake all are copied in the 16bit backup units, and abandon this fault DRAM particle, then utilize common ECC mechanism to revise second DRAM mistake.

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