CN112086401A - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN112086401A
CN112086401A CN201910508001.XA CN201910508001A CN112086401A CN 112086401 A CN112086401 A CN 112086401A CN 201910508001 A CN201910508001 A CN 201910508001A CN 112086401 A CN112086401 A CN 112086401A
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China
Prior art keywords
gate structure
substrate
hard mask
mask layer
forming
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CN201910508001.XA
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Chinese (zh)
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201910508001.XA priority Critical patent/CN112086401A/en
Publication of CN112086401A publication Critical patent/CN112086401A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention provides a semiconductor device and a forming method thereof, comprising the following steps: providing a substrate, wherein the substrate comprises a cutting area and a non-cutting area; forming a hard mask layer on the substrate; etching the substrate with partial thickness by taking the hard mask layer as a mask to form fin parts which are arranged in a discrete mode; removing the hard mask layer on the top of the fin part in the non-cutting area; forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part, and the top surface of the pseudo-gate structure is flush with the top surface of the hard mask layer; the invention simplifies the process of obtaining the rectangular line end and simultaneously improves the performance of the formed semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. The device is widely used as the most basic semiconductor device at present, and the traditional planar device has weak control capability on channel current, short channel effect is generated to cause leakage current, and finally the electrical performance of the semiconductor device is influenced.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin FET includes: the semiconductor device comprises a fin part and an isolation structure, wherein the fin part and the isolation structure are positioned on the surface of a semiconductor substrate, the isolation structure covers part of the side wall of the fin part, and the isolation structure is positioned on the substrate and crosses a grid structure of the fin part; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as the size of semiconductor devices is continuously reduced and the density of devices is increased, how to ensure the formation of good quality semiconductor devices is a problem which is urgently needed to be solved at present.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which ensure that the formed semiconductor device has higher quality.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a cutting area and a non-cutting area; forming a hard mask layer on the substrate; etching the substrate with partial thickness by taking the hard mask layer as a mask to form fin parts which are arranged in a discrete mode; removing the hard mask layer on the top of the fin part in the non-cutting area; and forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part, and the top surface of the pseudo-gate structure is flush with the top surface of the hard mask layer.
Optionally, the hard mask layer is made of silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide.
Optionally, the process for forming the hard mask layer includes a chemical vapor deposition method, an atomic layer vapor deposition method, or a physical vapor deposition method.
Optionally, the step of removing the hard mask layer on the fin portion of the non-cutting region includes: forming a photoresist layer on the substrate, wherein the hard mask layer on the fin part of the non-cutting area is exposed out of an opening of the photoresist layer; taking the photoresist layer as a mask; and removing the hard mask layer on the fin part of the non-cutting area.
Optionally, the substrate with a part of thickness is etched by a dry method to form fin portions which are arranged separately.
Optionally, after forming the pseudo gate structure, the method further includes: removing the pseudo gate structure; and forming a gate structure on the substrate, wherein the gate structure crosses the fin part.
Optionally, the gate structure includes a gate dielectric layer and a metal gate.
Optionally, the semiconductor device further includes an isolation structure, and the isolation structure covers a portion of the sidewall of the fin.
Optionally, after the dummy gate structure is formed, a top surface of the dummy gate structure is polished by using a chemical mechanical polishing method.
The present invention also provides a semiconductor device formed by the above method, comprising: a substrate including a cutting region and a non-cutting region; the fin parts are separately arranged on the substrate; the hard mask layer is positioned at the top of the fin part of the cutting area; and the pseudo-gate structure is positioned on the substrate, spans the fin part and has the top surface flush with the top of the hard mask layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
forming a hard mask layer on a substrate, etching the substrate with partial thickness by taking the hard mask as a mask to form fin parts which are arranged separately, removing the hard mask layer at the top of the fin part in a non-cutting area on the substrate at the moment, wherein the hard mask layer at the top of the fin part in the cutting area exists, and the combined height of the fin part in the cutting area and the hard mask layer is higher than the height of the fin part in the non-cutting area; meanwhile, when the dummy gate structure is subsequently removed to form the gate structure, no redundant gap exists between the gate structure and the fin portion, and the gate structure is free of holes or gaps during formation, so that the gate structure with good quality can be formed, the quality of the formed semiconductor device is improved, the phenomena of failure and the like of the semiconductor device in the use process are reduced, and the use range of the semiconductor device is enlarged.
Drawings
Fig. 1 to 6 are schematic structural views of a process of forming a semiconductor device in one embodiment;
fig. 7 to 13 are schematic structural views of a semiconductor device formation process in the first embodiment of the present invention;
fig. 14 to 19 are schematic structural views of a semiconductor device formation process in a second embodiment of the present invention.
Detailed Description
In a semiconductor device, a polysilicon gate cut mask (P2) is usually used to obtain a rectangular-shaped line end (rectangular-shaped line end), so that a gate pattern can be better controlled and the density of the semiconductor device can be improved, and a specific method for forming the semiconductor device is as follows:
referring to fig. 1, a substrate 1 is provided, the substrate 1 comprising a cutting region 11 and a non-cutting region 12.
Referring to fig. 2, a plurality of fins 2 are formed on the substrate 1 in a discrete arrangement.
Referring to fig. 3, a dummy gate structure 3 is formed on the substrate 1 to cross the fin 2.
Referring to fig. 4, an opening 4 is formed in the dummy gate structure 3 of the cutting region 11.
Referring to fig. 5, the opening 4 is filled with an insulating layer 5.
Referring to fig. 6, the dummy gate structure 3 is removed to form a gate structure 6.
The inventors have found that obtaining rectangular line ends using this method results in a semiconductor device having poor stability of use properties, while the semiconductor device is formed with a low degree of integration. The reason that the integration level of the formed semiconductor device is low is that when an insulating layer is formed, the insulating layer is filled in an opening formed by a pseudo-gate structure, and the pseudo-gate structure is arranged between the formed insulating layer and the fin part, so that a certain distance exists between the fin part and the insulating layer, and the waste of a formed space is caused; the reason that the formed semiconductor device has poor stability in the using process is that when the dummy gate structure is removed to form the gate structure, because the smaller gap is formed between the fin portion and the insulating layer, when the gate structure is formed, the air pressure in the gap has a strong adverse effect on the formation of the gate structure, a hole or a gap is easily formed in the gate structure, and the hole or the gap easily causes the failure of the using function of the semiconductor device, so that the use of the semiconductor device is limited.
The inventor researches and discovers that a hard mask layer is formed on a substrate, the hard mask layer is used as a mask to etch the substrate with a part of thickness, so that a fin part is formed, the hard mask layer is arranged on the top surface of the formed fin part, at the moment, the hard mask layer on the top of the fin part of a non-cutting area is removed, when a pseudo-gate structure is formed, the hard mask layer on the top of the fin part of the cutting area directly cuts off the formed pseudo-gate structure, so that a rectangular line end can be obtained, and the forming mode simplifies the process for obtaining the rectangular line end on one hand; on the other hand, when the dummy gate structure is removed to form the gate structure, no additional reaction force is applied to the gate structure, so that no gap or hole exists in the formed gate structure, the quality of the formed gate structure is ensured, and the performance of the formed semiconductor device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
First embodiment
Fig. 7 to 13 are schematic structural views of a semiconductor device formation process in the first embodiment of the present invention.
Referring first to fig. 7, the substrate 100 is provided, the substrate 100 including a dicing area 110 and a non-dicing area 120.
In this embodiment, the substrate 100 is made of monocrystalline silicon; in other embodiments, the substrate 100 may be monocrystalline silicon, polycrystalline silicon, or amorphous silicon; the substrate 100 may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like.
Referring to fig. 8, a hard mask layer 200 is formed on the substrate 100.
In this embodiment, the hard mask layer 200 is made of silicon nitride; in other embodiments, the material of the hard mask layer 200 may also be silicon oxide, silicon oxynitride, or silicon carbide.
In this embodiment, the hard mask layer 200 covers the fin formation position.
In this embodiment, the hard mask layer 200 is formed by an atomic layer deposition method; in other embodiments, the hard mask layer 200 may be formed by a chemical vapor deposition method or a physical vapor deposition method.
In this embodiment, the atomic layer deposition method parameters include: the gas used is SiH2Cl2And NH3The flow rate of the mixed gas is 1500 sccm-4000 sccm, the pressure is 1 mtorr-10 mtorr, the temperature is 200 ℃ -600 ℃, and the deposition times are 30-100 times.
Referring to fig. 9, the substrate 100 with a certain thickness is etched by using the hard mask layer 200 as a mask, and fins 300 arranged separately are formed on the substrate 100.
In this embodiment, the substrate 100 with a certain thickness is dry etched to form the fin portion 300; in other embodiments, the fin 300 may be formed by wet etching a portion of the thickness of the substrate 100.
In this embodiment, the parameters of the dry etching include: the adopted etching gas comprises HBr and Ar, wherein the flow rate of HBr is 10 sccm-1000 sccm, and the flow rate of Ar is 10 sccm-1000 sccm.
Referring to fig. 10, a photoresist layer 201 is formed on the substrate 100, and an opening of the photoresist layer 201 exposes the hard mask layer 200 in the non-cutting region 120.
In this embodiment, krypton fluoride (KrF) is used as the material of the photoresist layer 201; in other embodiments, argon fluoride (ArF) may also be employed.
Referring to fig. 11, the hard mask layer 200 on the fin 300 in the non-cutting region 120 is removed by using the photoresist layer 201 as a mask.
In this embodiment, the hard mask layer 200 on the fin portion 300 of the non-cutting region 120 is removed by anisotropic dry etching; in other embodiments, the hard mask layer 200 may be removed by wet etching.
In this embodiment, the dry etching parameters include: the gas used comprises CF4Gas and CHF3Gas, CF4The flow rate of the gas is 8sccm to 500sccm, CHF3The flow rate of the gas is 30 sccm-200 sccm, the pressure of the chamber is 10 mtorr-2000 mtorr, the source radio frequency power is 100W-1300W, the bias voltage is 80V-500V, and the time is 4 seconds-500 seconds.
Referring to fig. 12, the photoresist layer 201 is removed.
In this embodiment, an ashing process is used to remove the photoresist layer 201; in other embodiments, the photoresist layer 201 may be removed by using a chemical solution.
Referring to fig. 13, a dummy gate structure 400 is formed on the substrate 100, the dummy gate structure 400 crosses over the fin 300, and a top surface of the dummy gate structure 400 is flush with a top surface of the hard mask layer 200.
In this embodiment, the dummy gate structure 400 is cut in the cutting region 110 to form a cut-off dummy gate structure, and this cuts the formed dummy gate structure 400 directly by using the fin 300 having the hard mask layer 200, so as to obtain a rectangular line end, which simplifies the process of obtaining the rectangular line end on the one hand; on the other hand, when the dummy gate structure 400 is subsequently removed to form the gate structure, no additional force acts on the gate structure, so that the quality of the formed gate structure is improved, and the use performance of the formed semiconductor device is improved.
In this embodiment, after the deposition of the dummy gate structure 400 is formed, the top surface of the dummy gate structure 400 is further polished by a chemical mechanical polishing method, so that the top surface of the dummy gate structure 400 is flush with the top surface of the hard mask layer 200.
In other embodiments, a mechanical polishing method is further employed to make the top surface of the dummy gate structure 400 flush with the top surface of the hard mask layer 200.
In this embodiment, the reason why the top surface of the dummy gate structure 400 is flush with the top surface of the hard mask layer 200 by using a chemical mechanical polishing method is that: the chemical mechanical polishing integrates the advantages of chemical polishing and mechanical polishing, the efficiency of removing the redundant pseudo-gate structure 400 can be guaranteed, the perfect surface of the pseudo-gate structure 400 is obtained, and the surface flatness of the pseudo-gate structure 400 is high.
A semiconductor device formed using the above method, comprising: a substrate 100 including a cutting region 110 and a non-cutting region 120; fins 300, discretely arranged on the substrate 100; a hard mask layer 200 on top of the fin 300 in the cutting region 110; the dummy gate structure 400 is located on the substrate 100, crosses the fin 300, and has a top surface flush with a top surface of the hard mask layer 200.
Second embodiment
FIGS. 14 to 19 are schematic structural views illustrating a process of forming a semiconductor device according to a first embodiment of the present invention
In this embodiment, the process from providing the substrate to forming the fin portion is the same as that of the first embodiment, and a detailed description thereof will be omitted, specifically referring to fig. 7 to 9.
Referring to fig. 14, an isolation structure 500 is formed on the substrate 100, wherein the isolation structure 500 covers a portion of the sidewall of the fin 300.
In this embodiment, the isolation structure 500 is formed on the substrate 100; in other embodiments, the isolation structure 500 may not be formed on the substrate 100.
In this embodiment, the isolation structure 500 is made of silicon oxide; in other embodiments, the material of the isolation structure 500 may also be silicon nitride or silicon oxynitride.
In this embodiment, the isolation structure 500 is a Shallow Trench Isolation (STI) structure formed in a conventional manner.
In this embodiment, the isolation structure 500 protects the substrate 100, and the isolation structure 500 may also be used as an etching stop layer for a subsequent etching process.
In this embodiment, the isolation structure 500 is formed by a conventional process.
Referring to fig. 15, a photoresist layer 201 is formed on the substrate 100, and an opening of the photoresist layer 201 exposes the hard mask layer 200 in the non-cutting region 120.
In this embodiment, the material of the photoresist layer 201 is argon fluoride (ArF).
Referring to fig. 16, the hard mask layer 200 on the fin 300 in the non-cutting region 120 is removed by using the photoresist layer 201 as a mask.
In this embodiment, the hard mask layer 200 is removed by the same method as in the first embodiment.
Referring to fig. 17, the photoresist layer 201 is removed.
In this embodiment, an ashing process is used to remove the photoresist layer 201.
Referring to fig. 18, a dummy gate structure 400 is formed on the substrate 100, the dummy gate structure 400 crosses over the fin 300, and a top surface of the dummy gate structure 400 is flush with a top surface of the hard mask layer 200.
In this embodiment, the dummy gate structure 400 is formed by a conventional process, where the dummy gate structure 400 includes a gate dielectric layer (not shown) and a gate layer, and the gate layer is made of polysilicon.
Referring to fig. 19, the dummy gate structure 400 is removed, and a gate structure 600 is formed on the substrate 100, wherein the gate structure 600 crosses the fin 300.
In this embodiment, the dummy gate structure 400 is removed by a wet etching process, and the dummy gate structure 400 is removed by the wet etching process using tetramethylammonium hydroxide (TMAH) as an etching solution.
In other embodiments, the dummy gate structure 400 may be removed by a dry etching process, and HBr gas or SF6 gas may be used as an etching gas.
In this embodiment, the gate structure 600 is formed by a conventional process.
In this embodiment, the gate structure 600 includes a gate dielectric layer 610 and a metal gate 620.
In this embodiment, the gate dielectric layer 610 is made of a high-K dielectric material, which may be HfO2HfSiO, HfSiON, HfTaO, HfZrO, or Zr O2And the like. The gate dielectric layer 610 may be formed by a chemical vapor deposition process, an atomic layer vapor deposition process, or a sputtering process.
In this example, a sputtering process was used on Ar and O2Sputtering pure Hf target in the atmosphere with the power of 50-100W and the pressure of 1-10 Pa, and depositing HfO2And a gate dielectric layer.
In this embodiment, the material of the metal gate 620 includes Ti, TiW, TiN, W, or the like.
In this embodiment, since the hard mask layer 200 on the top of the fin portion 300 of the cutting region 110 is directly used to cut the dummy gate structure 400, when the dummy gate structure 400 is removed to form the gate structure 600, no additional force acts on the gate structure 600, so as to ensure the formation of the gate structure 600 with good quality, thereby improving the quality and the use performance of the formed semiconductor device.
A semiconductor device formed using the above method, comprising: a substrate 100 including a cutting region 110 and a non-cutting region 120; fin portions 300 separately arranged on the substrate 100; an isolation structure 500 on the substrate 100; a hard mask layer 200 on top of the fin 300 in the cutting region 110; a gate structure 600 including a gate dielectric layer 610 and a metal gate 620, located on the substrate 100, and crossing the fin 300, wherein the top surface of the fin is flush with the top surface of the hard mask layer 200, and the gate dielectric layer 610 covers part of the top surface and part of the sidewall surface of the fin 300; and a metal gate 620 covering the gate dielectric layer 610.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a cutting area and a non-cutting area;
forming a hard mask layer on the substrate;
etching the substrate with partial thickness by taking the hard mask layer as a mask to form fin parts which are arranged in a discrete mode;
removing the hard mask layer on the top of the fin part in the non-cutting area;
and forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure crosses the fin part, and the top surface of the pseudo-gate structure is flush with the top surface of the hard mask layer.
2. The method for forming a semiconductor device according to claim 1, wherein a material of the hard mask layer comprises silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide.
3. The method of claim 1, wherein the hard mask layer is formed by a process comprising chemical vapor deposition, atomic layer vapor deposition, or physical vapor deposition.
4. The method of forming a semiconductor device of claim 1, wherein removing the hard mask layer over the fin in the non-cutting region comprises:
forming a photoresist layer on the substrate, wherein the hard mask layer on the fin part of the non-cutting area is exposed out of an opening of the photoresist layer;
taking the photoresist layer as a mask;
and removing the hard mask layer on the fin part of the non-cutting area.
5. The method for forming the semiconductor device according to claim 1, wherein the fin portions which are arranged discretely are formed by dry etching a part of the thickness of the substrate.
6. The method of forming a semiconductor device according to claim 1, further comprising, after forming the dummy gate structure:
removing the pseudo gate structure;
and forming a gate structure on the substrate, wherein the gate structure crosses the fin part.
7. The method of forming a semiconductor device of claim 6, wherein the gate structure comprises a gate dielectric layer and a metal gate.
8. The method of claim 1, further comprising an isolation structure covering a portion of sidewalls of the fin.
9. The method for forming a semiconductor device according to claim 1, wherein after the dummy gate structure is formed, a top surface of the dummy gate structure is polished by chemical mechanical polishing.
10. A semiconductor device formed by the method of any of claims 1 to 9, comprising:
a substrate including a cutting region and a non-cutting region;
the fin parts are separately arranged on the substrate;
the hard mask layer is positioned at the top of the fin part of the cutting area;
and the pseudo-gate structure is positioned on the substrate, spans the fin part and has the top surface flush with the top of the hard mask layer.
CN201910508001.XA 2019-06-12 2019-06-12 Semiconductor device and method of forming the same Pending CN112086401A (en)

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